26.5 A Practical Si Nanowire Technology with Nanowire ... - IEEE Xplore

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Process Development Team, CAE Team*, Semiconductor R&D center, Samsung Electronics Co. San #16, Banwol-dong, Hwasung-city, Gyeonggi-do, 445-701, ...

A Practical Si Nanowire Technology with Nanowire-on-Insulator structure for beyond 10nm Logic Technologies Sung-Gi Hur, Jung-Gil Yang, Sang-Su Kim, Dong-Kyu Lee, Taehyun An, Kab-Jin Nam, Seong-Je Kim*, Zhenhua Wu*, Wonsok Lee*, Uihui Kwon*, Keun-Ho Lee*, Youngkwan Park*, Wouns Yang, Jungdal Choi, Ho-Kyu Kang and EunSung Jung Process Development Team, CAE Team*, Semiconductor R&D center, Samsung Electronics Co. San #16, Banwol-dong, Hwasung-city, Gyeonggi-do, 445-701, Korea, Tel: +82-31-208-0115, Email: [email protected] Abstract

Results and Discussions

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9nm and thin equivalent oxide thickness (EOT) of 0.9nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

In order to maximize on-current with the high conductivity ( =ns·q·µeff) of Si NW, electron density (ns) and effective mobility (µeff) with various EOT of GOX and DNW were simulated. As DNW or EOT was decreased, ns was highly increased up to ~1020 cm-3 at 4nm DNW and 0.9nm EOT while µeff was decreased down to ~50 cm2/Vs, as shown in Fig.3. Thus, at 0.9nm EOT, DNW with peak µeff was shifted from 4nm to 13nm, as shown in Fig. 4, different from reported 4nm DNW having peak µeff at 2.5nm EOT [4]. This was because volume inversion characteristic in thinner EOT could be obtained even at large DNW of 13nm. As shown in Fig. 5, for the sake of an optimum DNW regarding higher on-current, conductivity was calculated with various DNW and higher conductivity was obtained at 9nm DNW. Based on above simulation results, electrical properties of Si NW FETs with DNW of 9, 11 and 13nm at scaled EOT of 0.9nm were characterized. As predicted, Si NW of DNW=9nm showed the best ION-ISOFF performance in Fig. 6. In addition, VT dependencies of ION and ISOFF characteristics as a function of DNW were shown in Figs. 7 (a) and (b). Both ION and ISOFF performances of Si NW with DNW=9nm were improved at the same VT. Moreover, according to the analysis of LG dependency of RTOT (=RCH+REXT), RTOT at 9nm DNW was reduced by the lowest RCH (62 Ω-μm) while there was no significant reduction of REXT, as shown in Fig. 8 (a) and (b), which was well-matched to ION improvement results, as shown in Fig. 6. However, further experimental investigations on DNW below 9nm are needed because ISOFF improvement was observed up to 9nm DNW. Also, the short channel effect of the fabricated Si NW was characterized by LG dependence of sub-threshold swing (SS) and drain induced barrier lowering (DIBL) with various DNW in Fig. 9. SS characteristics were almost same and DIBL differences were negligible in various DNW thank to inherent good gate controllability of GAA structure. Furthermore, the reliability characteristics of Si NWs were investigated with DNW. High drain leakage current was observed as DNW was decreased, as shown in Fig. 10 (a) and its leakage source came mainly from the high gate oxide leakage according to ID, IS and IG analysis of Fig. 10 (b). The reason was that the gate to S/D overlap region was increased by wide lateral etching of SiGe layer beneath S/D region as shown in Fig. 10 (c). This gate to S/D overlap region can be minimized by optimizing the epi-thickness of Si layer and the etching condition of sacrificial SiGe layer. The time-zero dielectric breakdown (TZDB) and the positive bias temperature instability (PBTI, gate stress bias at VT shift of 50mV) were

Introduction NW transistor architecture is regarded as one of the most promising candidates for the sub-10nm logic era because existing FinFET will face scaling limitations beyond that technology node [1-3]. However, in previous NW works [2], most Si NW MOSFET was investigated with thicker gate oxide (Gox) and larger gate length (LG) and the solutions for the high capacitance issues were not reported yet. Therefore, in this paper, we report a Si NW MOSFET technology with scaled Gox and LG as well as capacitance reduction for the sub-10nm logic devices application. Fabrication of Si NW transistors Undoped Si NW NFETs with high-k (HK)/metal gate (MG) stacks were fabricated. Fig. 1 shows the schematic diagrams of the Si NW fabrication process. First, Si and SiGe epitaxial layers were grown on a Si substrate and Si/SiGe active fin patterns were formed. After the p-well implantation and Fin recess process, the dummy poly-Si gate was formed. Raised S/D process with ion-implantation was followed. Si NWs were released by anisotropic wet etching of SiGe and DNW was controlled by the wet-etching conditions. After NW release, an HfOx-based HK and a TiN-based MG were formed by a gate-last process. Finally, metallization process was followed. Fig. 2 shows cross-sectional TEM images of an undoped Si NW, whereby the gate-all-around (GAA) HK/MG stacks are clearly visible.

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shown in Figs. 11 and 12 as a function of DNW. As DNW was decreased, TZDB was decreased from 2.94V to 2.79V because electrical field was increased at NW with smaller curvature. But, the PBTI of all DNW was similar and slightly degraded compared to FinFET, which could be possibly due to various orientations of Si NW. NW performances of this work were summarized compared to other published NW results in the Table I [1-3]. The fabricated Si NW with the scaled DNW and thin EOT was demonstrated with good DC performance like superior ISOFF and SS characteristics. The relative DC & AC performances of Si NW devices were simulated in Fig. 13 as functions of DNW and the number of stacked NWs. Though Si NW of 9nm DNW obtained the best DC performance in above results, 14nm DNW showed better DC & AC performances than those of 9nm DNW in terms of same footprint criteria because of much increased channel area and carrier amount. For higher performance beyond 10nm logic device, multiple-NWs are necessary. As an example, triple-NW with 14nm DNW showed ~40% ION improvement compared to that of FinFET. However, AC performance even with triple-NW was increased only by 5% due to the increased capacitance of multiple-NW, as shown in Fig. 14.

In order to overcome high capacitance issue of multipleNWs, Nanowire-On-Insulator (NOI) structure was depicted in Fig. 15. As a result of Fig 13, the AC performance of this new multiple-NOI structure was improved by ~20% compared to conventional triple NW structure. Summary Si nanowire was simulated and experimentally investigated with various DNW and EOT. Single NW with 9nm DNW showed the best ION-IOFF performance with the low RCH and the enhanced gate controllability. However, in terms of reliability and AC performance, it is found that DNW should be increased over 9nm and multiple-NW is needed to meet DC performance target at sub-10nm. 20% AC performance was improved with a newly proposed triple NOI structure, which can hold one of promising candidates for sub-10nm logic technology. References: [1] C. Dupré et al., IEDM, 749-752 (2000). [2] S. D. Suk et al., IEDM, 717-720 (2008) [3] S. Bangsaruntip et al., IEDM, 297-300 (2009). [4] S. D. Suk et al., IEDM, 891-894 (2007).

Fig. 1 Schematic diagrams of a Si NW nFET fabrication process: (a) Si/SiGe epitaxial growth, (b) Si/SiGe active pattern definition, (c) NW formation and (d) HK/MG deposition and metallization. Various NWs were made by selective wet etch of SiGe against Si.

Fig. 2 Cross-sectional TEM images of an integrated Si NW: (a) along the gate direction and (b) along the NW direction, whereby the gate-all-around (GAA) HK/MG stacks are clearly shown.

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Fig. 3 Cross-sectional contour plots of electron density and its x-cut profile of Si NW with DNW=4, 9 and 13nm at various EOT conditions. As DNW or EOT was decreased, ns was highly increased 20 -3 up to ~10 cm at 4nm DNW and 0.9nm EOT.

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Fig. 4 Effective mobility for various DNW. DNW with peak μeff was shifted from 4nm to 13nm at scaled 0.9nm EOT.

Fig. 5 Conductivity as a function of DNW at 0.9nm EOT. 9nm DNW showed higher conductivity.

Fig. 6 ION-ISOFF correlation. DNW=9nm shows around 60% higher performance than that of DNW=13nm. ION =(ID at VD=VG=0.8V), ISOFF =(IS at VD=0V, VG=0.8V) Fig. 7 (a) VT-ION and (b) VT-ISOFF. The DNW= 9nm Si NW device shows the best ION and lowest ISOFF at the same VT, because it features the low RCH and electrostatic improvement, respectively.

Fig. 8(a) LG-RTOT and (b) DNW-RTOT (RTOT =RCH+REXT) for various DNW at LG=24nm. The DNW=9nm Si NW device shows a decreased RCH (62 -um) due to the increased electron density, which is well-matched to simulation results as shown in Fig. 3.

Fig. 9 LG dependences of DIBL and SS. SS characteristics were almost same and DIBL differences were negligible in various DNW thank to inherent good gate controllability of GAA structure.

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Fig. 10 (a), (b) and (c) show the VG-VT vs. ID characteristics for various DNW, the IDOFF for 9nm DNW , ID, IS, IG-VG and a schematic diagrams of the gate and S/D overlap at the bottom gate. High drain leakage current was observed as DNW was decreased. It leakage source came mainly from the high gate oxide leakage according to ID, IS and IG analysis. The reason was that the gate to S/D overlap region was increased by wide lateral etching of SiGe layer beneath S/D region. Fig. 11 TZDB as a function of DNW. As DNW decreases, TZDB decreases from 2.94V to 2.79V. However, it is satisfied with a criteria from FinFET result.

Table I. Performance comparison of Si NW MOSFETs from this work to other published results

Fig. 12 PBTI characteristics as a function of DNW. Around 2V PBTI results were obtained, which was slightly degraded with existing FinFET.

Fig. 13 Relative DC and AC performances of Si NW devices as a function of DNW and of the number of stacked NWs. The performances are normalized by same footprint.

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Fig. 14 Relative gate capacitance as a function of DNW and the number of stacked NWs.

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Fig. 15 A new Nanowire-on-Insulator (NOI) transistor structure aimed at reduced the gate capacitance. This structure can decrease the total capacitance by more than 20% with 7nm SiO2 layers at each side of the bottom gates of the NWs.

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