3-D Silicon Integration and Silicon Packaging ... - IEEE Xplore

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias John U. Knickerbocker, Member, IEEE, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, and John M. Cotte

Abstract—System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 m) interconnection is described. This silicon carrier package contains silicon through-vias and offers 16 increase over standard chip I/O, a 20 to 100 increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single “virtual chip.” Index Terms—Chip integration, high bandwidth, integrated decoupling capacitors, interconnection, silicon packaging, silicon through-vias, 3-D.

I. INTRODUCTION

S

YSTEM-ON-CHIP (SOC) has supported reduced costs and improved time-to-market [1] and has fueled semiconductor growth from pervasive electronic applications through

Manuscript received December 5, 2005; revised March 17, 2006. This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) under the Chip-to-Chip Optical Interconnects (C2OI) Program, Agreement MDA972-03-3-0004, in part by DARPA under the PERCS Program, Agreement NBCH30390004, and in part by the Maryland Procurement Office under Contract H98230-04-C-0920. J. U. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. P. Buchwalter, R. R. Horton, R. J. Polastre, S. L. Wright, and J. M. Cotte are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). E. J. Sprogis is with the IBM T. J. Watson Research Center, Essex Junction, VT 05452 USA. H. Gan is with the IBM T. J. Watson Research Center, Hopewell Junction, NY 12533 USA. Digital Object Identifier 10.1109/JSSC.2006.877252

Fig. 1. Evolution of memory density over time [2].

more complex computing products. An example shown in Fig. 1 is the evolution of memory density over time [2] which shows support to Moore’s law [3] through 1998. Moore’s law states chip integration advancements are comprised of 50% lithography, 25% device and circuit innovations and 25% from chip size which collectively provide a performance doubling every 18 months. Fig. 1 also shows a slow down in memory density scaling post 1998. Is Moore’s law borken? Is circuit scaling coming to an end? Should we be considering alternate technologies? Chen has reported an expectation for continued CMOS circuit scaling but also shows a parallel roadmap approach to provide subsystem scaling over time and development of post CMOS technologies and quantum computing [4]. For subsystem research, subsystem scaling may include 3-D silicon integration and 3-D packaging especially where increasing cores per processor chip need increasing bandwidth to memory for high-performance operation [4]. Package integration has also progressed over time with increasing perimeter and area array interconnection density, but the rate of integration has fallen far behind chip circuit integration and has clearly not kept pace with Moore’s law even if the rate of chip integration has been reduced in recent years. For chip-to-package interconnection, area array (flip-chip) technology has provided the highest level of chip integration using I/O per cm . traditional organic and ceramic packages at Higher density chip-to-package or three-dimensional (3-D) chip-to-chip integration may leverage silicon through-via interconnection, as is illustrated in Fig. 2. Chip stacking, silicon carrier packaging, and 3-D chip circuit and wiring integration offer an even higher level of silicon integration where orders of magnitude I/O density advancement may be possible. Technology advancements and manufacturing learning are required

0018-9200/$20.00 © 2006 IEEE

KNICKERBOCKER et al.: 3-D SILICON INTEGRATION AND SILICON PACKAGING TECHNOLOGY USING SILICON THROUGH-VIAS

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TABLE I EMERGING 3-D TECHNOLOGIES

Fig. 2. Silicon integration comparison for ceramic and organic packaging, silicon carrier and chip stack and 3-D silicon circuits and wiring.

to overcome key challenges and to achieve lower costs. Advantages include minaturization, increased bandwidth, higher performance, reduced power, and the ability to integrate heterogeneous technologies [5]–[7]. As depicted in Fig. 2, 3-D circuit integration may hold the opportunity for the highest level of circuit integration with stacked active devices [5], [8] and may require complete circuit and architecture design innovations at each level or 3-D design tools to best take advantage of this emerging technology. Chip stacking, silicon carrier, or silicon packaging technologies shown with intermediate interconnection density in Fig. 2 may provide another means to develop 3-D structures which enhance system integration and performance. Key technology challenges include design, design tools, test, alignment and assembly, and cooling, depending on the level of integration and power. Benefits in product quality and cost can be expected as industry 3-D infrastructure and manufacturing mature. Examples of silicon integration using SOP and SOC at IBM have been reported for manufactured products and in research demonstrations. In high-performance server products using SOP thin-film multi-chip modules [9] and ceramic modules [10], 97-3 PbSn solder interconnections up to 7018 signal I/O were used at 200- m pitch for a density up to 2500 I/O per cm . Research on SOC advanced interconnection density MEMS or VLSI-MEMS [6] has demonstrated interconnection density at 300 electrical connections per mm (30 000 per cm ) using 15- m-diameter copper studs with a tin cap and reported a 99.9% yield. Research on a SOP silicon carrier used for a parallel optical tranceiver [7] demonstrated 25- m solder interconnection at a 50- m pitch with a limited number of total I/O but with a density of 40 000 I/O per cm using AuSn eutectic solder to create a terabit per second parallel tranceiver module. A recent electrical integrity demonstration of a transferred ring ocillator using 130-nm silicon-on-insulator (SOI) CMOS devices and circuits [5] illustrates the potential opportunity to scale 3-D integrated circuits to a much higher level of SOC integration. In each of these research demonstrations, a path

forward to volume manufacturing should consider the business applications and manufacturing practices to enable product value at low cost. Practical considerations influencing 3-D product definition using SOC versus SOP include the number of devices to be integrated, testability and overall yield. A summary of emerging 3-D technology integration is shown in Table I which includes 3-D circuits connected with area array silicon through-vias, 3-D cooling, 3-D MEMS, silicon packaging and integration of these structures by SOC and SOP/SIP. An example of emerging technology is the new silicon through-via compared to traditional back-end of line wiring and vias in the wafer build up layers. Recent publications have described research including approaches for 3-D integrated circuits and chip stacking, each having vias which permit silicon-on-silicon stacking. In one approach, SOI technology permitted very small vias to join active circuits in two layers of silicon [5], [8]. In another approach, 10- m copper conductors provided through silicon electrical interconnection at 20- m pitch [11]. Limited or no information was reported on the robustness of these via structures based on application or reliability stressing. Fine-pitch interconnection for silicon-on-silicon has also been reported with a wide variety of bonding and electrical interconnection approaches between silicon die in chip stacks or packages using silicon. For example, anistropic conductive polymers were used to bond 25- m thinned die [12]. Fifty- m AuSn bumps [13] and finepitch solder have been reported to join silicon chips to stacked silicon packages [14]. Cu studs with Sn cap have also been used to join fine-pitch features between silicon chips in a stack [15]. Limited data was reported on the manufacturability of these technologies and their reliability toward product applications. In this paper, we show examples of potential product applications for 3-D silicon-on-silicon technology and silicon carrier packaging technology. Examples of process flow for fabrication and assembly are reported. A comparison of bandwidth between package options is shown. Examples of technology demonstrations include: 1) silicon through-via structures; 2)

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electrical characterization of wiring on a silicon package; 3) assembly using PbSn and SnCu solder microbumps; 4) an example of fine-pitch probes for wafer level testing; and 5) a summary of reliability testing results for the 50- m-pitch solder interconnections. II. SILICON CARRIER PACKAGING TECHNOLOGY AND APPLICATIONS Silicon carrier packaging technology includes: 1) silicon through-vias; 2) high-density signal wiring and voltage distribution; 3) fine-pitch interconnection such as permanent copper-to-copper stud bonding or reworkable high-I/O solder interconnection; 4) high-I/O testing such as known good die (KGD) testing and assembled module testing; and 5) integrated function such as decoupling capacitors. The critical technology needs vary based on design, manufacturing, application and relative cost compared to competing solutions. Discussed below are three potential applications of IBM’s silicon carrier technology. First, a parallel optical transceiver integrating heterogeneous components on a silicon carrier package as has been previously reported by Patel et al. [7] is discussed. Second, a silicon carrier package having integrated decoupling capacitance as an interposer directly under an active chip is presented. Third, a high-density package with high-density interconnection for interconnecting multiple chips or chip stacks as a mini-multi-chip module (MMCM) or “virtual chip” is detailed.

Fig. 3. Parallel optical transceiver using silicon carrier [7].

III. PARALLEL OPTICAL TRANSCEIVER The design, fabrication, characterization, and structure of the parallel optical transceiver have been described previously in detail [7]. The silicon carrier of Fig. 3 incorporated electrical silicon through-vias, high-speed wiring, and a rectangular through-carrier cavity. Furthermore, it provided a platform to house the laser diode driver (LDD) or transimpedance amplifier (TIA) IC and a vertical cavity surface-emitting laser (VCSEL) or photodiode (PD) opto-electronic chip (OE). This was achieved utilizing conventional assembly processes to integrate these heterogeneous components onto an organic chip carrier with build up layers. The process flow for the silicon carrier including silicon through-via processes, wiring interconnection using traditional copper back-end-of-line (BEOL) processes and assembly is illustrated in Fig. 4. The roughly 300- m-thick free-standing silicon carrier fabrication included via definition, sidewall insulation via metallization, connection to terminals or surface wiring on the silicon carrier, wafer thinning, and metallization prior to assembly. The critical technology required silicon processing, ability to support the OE and transceiver structure, ability to fabricate silicon through-vias, and ability to accommodate thermal excursions in processing without failure due to coefficient of thermal expansion mismatch between silicon through-via conductors, liner, insulator, and silicon. IV. SINGLE CHIP SILICON PACKAGE AND INTEGRATED DECOUPLING CAPACITOR PACKAGES Chip design targets minimum die size to maximize die per wafer for low cost. A high-performance or high-I/O device may

Fig. 4. Silicon carrier process flow [7].

benefit from the design, fabrication and use of a silicon carrier package that provides fine-pitch redistribution for I/O bound die or integrated decoupling capacitors where on-chip decoupling capacitance may be limited [16], [17]. The die may be attached to the silicon package using permanent copper-to-copper bonding or reworkable solder bonding. After bonding, the die or chip stack with underlying silicon package or decoupling capacitor may be placed as an individual die. Fig. 5 illustrates cross-section schematics of silicon carrier packages of a single die with a redistribution wiring or a single die with underlying silicon with integrated decoupling capacitors. In the case of integrated decoupling capacitors, the silicon carrier can be fabricated with parallel metal conductors with an insulator between them or trench capacitors such as is employed with eDRAM technology [17]. The decoupling capacitor directly under the chip can support reduced noise with low-inductance decoupling for simultaneous switching. Compared to discrete capacitors on package, system performance may be enhanced or power reducted using silicon integrated decoupling capacitors based on


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Fig. 5. Schematic cross section of silicon carrier packages with (a) redistribution and (b) integrated decoupling capacitors.

Fig. 7. Bandwidth comparison for a silicon carrier package, ceramic, organic, and PWB [16].

Fig. 6. Schematic cross section of silicon package supporting high-bandwidth chip-to-chip wiring (MMCM).

TABLE II SUBSTRATE COMPARISON PARAMETERS [17]

modeling. Portable product applications could achieve lower power operation and thus longer battery life. V. MINI-MULTI-CHIP MODULES (MMCMS) Fig. 6 shows a schematic cross section of a silicon carrier package which provides high-bandwidth chip interconnection using fine-pitch solder interconnection such as 50- m chip I/O pitch [16]–[20]. Fig. 7 shows a comparison of the relative bandwidth of silicon packaging compared to organic, ceramic, and printed wiring board (PWB) per layer. Table II shows the corresponding parameter file. For chip-to-chip interconnection using a silicon package over short distances such as 10 mm, bandwidth can be eight times the bandwidth of organic packages and greater for comparison to ceramic or PWBs. Silicon carrier packages that support these high I/O between die on a silicon carrier packages may also benefit from reworkable solder interconnections and use of KGD. The high-bandwidth interconnection between die may provide new opportunities for heterogeneous chip integration, opportunity to develop new architectures with microprocessor to memory chip stacks with reduced latency and 2-D or 3-D structures with “virtual chip like” system benefits. VI. SILICON CHIP STACKING AND SILICON PACKAGING TECHNOLOGY Three-dimensional silicon-on-silicon stacks and silicon packages have been fabricated as either thick free-standing silicon or as thin carriers which are under 150 m in thickness and require mechanical support during processing or handling [16]. VII. SILICON THROUGH-VIA A process sequence comparison for via formation in thin carriers is shown in Table III. Here, the via process sequence is

compared for via first and via last processes. A more extensive update on silicon through-vias has been reported [18]. Fig. 8 shows cross sections of silicon through-vias for 50- mthick silicon and 300- m-thick silicon packages. A dielectric, liner, copper, and composite provide low coefficent of thermal expansion for thermal excursions with deep vias for 300- m -thick silicon packages, whereas for thinner silicon packages, annular vias or high aspect ratio vias have been developed [17], [18]. In contrast, a handle wafer is used to support wafer prom cessing and is later laser released or debonded for thin silicon carriers where the thin silicon carrier is bonded to a supporting ceramic or organic structure. Free standing silicon packages and supported thin silicon carrier packages used BEOL copper processing in addition to silicon through-vias to provide for signal wiring, power and reference planes for reported electrical characterization. VIII. FINE-PITCH WIRING Coplanar waveguides have been fabricated, characterized, and modeled [16], [21]. Characterization included feature sizes ranging from under one micron to several microns for lines and spaces. Signal integrity and voltage distribution modeling, simulation and measurement have been made where co-planar waveguides, previously reported [7], [21], [22], were used for

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TABLE III PROCESS STEPS FOR SILICON THROUGH-VIAS

(a)

(b)

TABLE IV TIME DOMAIN MEASUREMENT RESULTS OF CO-PLANAR WAVEGUIDE (CPW) TRANSMISSION

(c)

Fig. 8. Silicon via cross section for (a) high aspect ratio via and (b), (c) annular vias with silicon < 150 m and 70 by 300 m silicon through-via composite conductors, respectively. Fig. 9. Microbump fabrication sequence.

time domain signal characterization, given in Table IV. Results showed that high-speed signal integrity can be supported such as between chips at 6 GHz over 5-mm length.

solder bumps on 125- m pitch for chip interconnection and 250- m-pitch interconnection to a glass ceramic package.

IX. FINE-PITCH MICROBUMPS AND ASSEMBLY

X. KNOWN GOOD DIE AND RELIABILITY TESTING

Test vehicles also included dies with I/O ranging from 2160 to over 10 000. For test die with 10 000 microbumps, either 37-63 Pb-Sn eutectic solder or lead-free solder of Sn-Cu 99.3-0.7 was used following the process steps shown in Fig. 9. Fig. 10 shows an example of a 25- m-diameter bump, a microbump joint under 20- m height, an array of 50- m-pitch microbumps, and an assembled chip on silicon carrier. Assembly of the test die to a silicon carrier package was conducted using a precision alignment bonder and early demonstrations were able to achieve 99.99% yield where the die had 10 000 I/O with eutectic solder. Mechanical pull testing demonstrations with fewer I/O per die showed 100% “taffy pulls” and mechanical pull and shear results in excess of 2 to 4 grams force per I/O [19]. Silicon die on silicon packages on either ceramic or organic packages have also been assembled. One example shown in Fig. 11 shows a test vehicle with 75- m

To demonstrate a path forward for KGD, test probes were fabricated at a 50- m pitch and corresponding microbumps were successfully contacted as shown in Fig. 12. Electrical continuity tests of microbump chains showed the 20–25- mdiameter microbumps to have approximately 5 to 26 m resistance depending on the test structure used. Electromigration (EM) testing of the microjoined solder has shown samples of over 2000 hours without failure at 150 C and 62.5 mA per microbump. Other reliability tests, including additional EM tests at higher currents, has also been reported [19], [20]. Non-underfilled samples as well as underfilled samples were deep-thermally-cycled (DTC) from 55 C to 125 C and survived over 2000 cycles without failures. Samples were also subjected to high-temperature storage (HTS) for 2000 hours at 150 C without failure. Temperature–humidity-bias voltage (THB) tests have shown samples with and without underfill


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TABLE V SILICON CARRIER SILICON THROUGH-VIA AND MICROBUMP RELIABILITY CHARACTERIZATION SUMMARY FOR 25-m-DIAMETER ON 50-m PITCH SOLDER BUMP ARRAY [17]–[20]

Fig. 10. (a) Solder microbump. (b) Interconnection. (c) Array of microbumps at 50-m pitch. (d) Assembly.

Microbumps can support KGD test and high-I/O density for heterogeneous chip integration. Initial assembly, mechanical testing, and reliability testing showed positive results toward potential product applications. Further exploratory test vehicle designs, silicon through-via structures, fabrication processes, 3-D chips stacks, electrical, mechanical and physical characterization, and reliability assessments are planned. Fig. 11. Silicon die on silicon package on glass–ceramic substrate.

ACKNOWLEDGMENT

(a)

(b)

Fig. 12. (a) Single test probe tip from 50-m probe pitch array and (b) example of single solder ball microbump contact, also from the 50-m-pitch solder bump array.

The authors wish to acknowledge support from C. Schuster, C. Baks, F. Doany, J. Rosner, S. Cordes, B. Webb, G. McVicker, S. Sri-Jayantha, and D. Manzer. The authors also wish to acknowledge other IBM employees from the Terabus team, the PERCS team, the MRL & CSS teams at Yorktown Heights, NY, and the S&TG support from locations including Austin, TX, Burlington, VT, East Fishkill, NY, and Poughkeepsie, NY, and the management support from T. Chainer, D. Seeger, and T. C. Chen. REFERENCES

can support 85% RH, 85 C and 10 V in excess of 1000 hours without failure. Table V shows a summary of reliability testing for several of the silicon-on-silicon test vehicles characterized to date. XI. CONCLUSION AND OUTLOOK Silicon carrier packages have been designed, fabricated, and characterized, including silicon through-vias, multiple levels of BEOL wiring, high-I/O interconnection and high-I/O test probe structures at 50- m pitch [16]–[21]. Novel opportunities for SOP integration leveraging a silicon carrier were discussed through the examples of a new parallel optical tranceiver module, a single-chip module, and a mini-multi-chip module. The silicon carrier can support high-performance electrical transmission rates and optics.

[1] C. A. Scholten, “System-on-a-chip: what industry needs to do,” Solid State Technol., vol. 43, no. 3, pp. 121–123, 2000. [2] J. H. Yoon, “Advanced DRAM technology status and future directions,” in Proc. JEDEX, San Jose, CA, Mar. 2005. [3] G. Moore, “Cramming more components onto integrated circuits,” Electronics, Apr. 19, 1965. [4] T. C. Chen, “Where Si-CMOS is going: trendy hype vs real technology,” presented at the IEEE ISSCC, San Francisco, CA, 2006, Keynote Address. [5] K. W. Guarini et al., “Electrical integrity of state-of-the-art 0.13 m SOI CMOS devices and circuits transferred for three-dimensional (3-D) integrated circuit (IC) fabrication,” in IEDM Tech. Dig., 2002, pp. 943–945. [6] M. Despont et al., “Wafer-scale microdevice transfer/interconnect: its application in an AFM-based data-storage system,” J. Microelectromech. Syst, vol. 13, no. 6, pp. 895–901, 2004. [7] C. S. Patel et al., “Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver,” presented at the 55th Electronic Components and Technology Conf. (ECTC), Lake Buena Vista, FL, 2005.

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[8] A. W. Topol, “ Enabling SOI-based assembly technology for threedimensional (3d) integrated circuits (ICs),” in IEDM Tech. Dig., 2005, pp. 352–355. [9] E. D. Perfecto et al., “Thin-film multichip module packages for high-end IBM servers,” IBM J. Res. Develop., vol. 42, no. 5, pp. 597–606, 1998. [10] J. U. Knickerbocker et al., “An advanced multichip module (MCM) for high-performance UNIX servers,” IBM J. Res. Develop., vol. 46, no. 6, 2002. [11] K. Takahaski et al., ASET (Japan), “Process integration of 3-D chip stack with vertical interconnection,” presented at the 54th Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, 2004. [12] M. Feil et al., “The challenge of ultra thin chip assembly,” presented at the 54th Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, 2004. [13] M. Hunter et al., “Assembly and reliability of flip chip solder joints using miniaturized Au/Sn bumps,” presented at the 54th Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, 2004. [14] V. Kripesh et al., “Three-dimensional system-in-package using stacked silicon platform technology,” IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 377–386, Aug. 2005. [15] M. Umemoto et al., ASET (Japan), “High-performance vertical interconnection for high-density 3D chip stacking package,” presented at the 54th Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, 2004. [16] J. U. Knickerbocker et al., “Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine pitch chip interconnection,” IBM J. Res. Develop., vol. 49, no. 4/5, pp. 725–753, 2005. [17] J. U. Knickerbocker et al., “System-on-package (SOP) technology, characterization and applications,” presented at the 56th Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2006. [18] P. Andry et al., “A CMOS-compatible process for fabricating electrical through-vias in silicon,” presented at the 56th Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2006. [19] H. Gan et al., “Pb-free micro-joints for the next generation microsystems: the fabrication, assembly and characterization,” presented at the 56th Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2006. [20] S. L. Wright et al., “Characterization of micro-bump C4 interconnects for Si-Carrier SOP applications,” presented at the 56th Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2006. [21] C. S. Patel, IBM Internal Communication and Reports. IBM T. J. Watson Research, Yorktown Heights, NY, 2005–2006. [22] A. Deutsch et al., “Frequency-dependent losses on high-performance interconnections,” IEEE Trans. Electromagn. Compat., vol. 43, no. 4, pp. 446–465, Nov. 2001. John U. Knickerbocker (M’06) received the B.S. and M.S. degrees in ceramic engineering from the State University of New York at Alfred, and the Ph.D. degree in ceramic engineering from the University of Illinois at Urbana-Champaign. He is currently an IBM Distinguished Engineer and the manager of the System-on-Package (SOP) Group. In 1983, he joined the IBM facility at East Fishkill, NY, where he held a series of engineering and management positions, including Director of IBM worldwide packaging development, manager of package lead reduction and packaging strategist. In 2003, he joined the IBM Research Division, Yorktown Heights, NY, where he has led the development of next-generation silicon carrier packaging and integration. He has authored or coauthored 130 patents or patent applications and more than 26 papers and publications. Dr. Knickerbocker has received an IBM Corporate Award and three Division Awards, including IBM Outstanding Achievement Awards, three IBM Patent Portfolio Award Awards, and 30 Invention achievement awards. He serves as a member of the SEMATECH 3-D working group and has served on the technical advisory boards of multiple universities. He is a member of IMAPS and a Fellow of the American Ceramic Society.

Chirag S. Patel (M’03) received B.S., M.S. and PhD degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1995, 1996, and 2001, respectively. He is currently a Research Staff Member in the Science and Technology Department at the IBM Thomas J. Watson Research Center, Yorktown Heights,


NY. He joined the IBM Research Division in 2001, where he has worked on advanced and exploratory packaging technologies. He is an author or coauthor of more than 35 technical papers.

Paul S. Andry received the B.Sc. degree in physics from the University of Waterloo, ON, Canada, in 1986, the M.Sc. degree in physics from the Université de Sherbrooke, QC, Canada, in 1990, and the Ph.D. degree in materials science from the University of Vermont, Burlington, in 1997. He is currently a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. He joined IBM in 1997, working in the Advanced Display Technology Laboratory on a variety of projects including prototypes of world’s highest information content display, as well as the world’s first a-Si driven OLED display. After serving as Technical Assistant to the VP of Science and Technology, he returned to technical work in the System on Package Group where he has been working on development of key technology elements and applications of silicon carrier technology. He is a coeditor of the book Thin Film Transistors (Marcell-Dekker, 2003), author or coauthor of more than 20 professional publications, and holder of 20 issued or pending patents.

Cornelia K. Tsang received the B.S. and M.S. degrees in materials science and engineering from the Massachusetts Institute of Technology, Cambridge, in 2000 and 2001, respectively. She joined the IBM Research Division, Yorktown Heights, NY, in 2001 and has worked since then in the System-on-Package Group on novel process development and integration of silicon carrier packages.

L. Paivikki Buchwalter received her Diploma Engineer (M.Sc. equivalent) and Doctor of Technology degrees, both in chemical engineering, from Helsinki University of Technology, Finland in 1976 and 1997, respectively. She is a Senior Scientist in the System-on-Package Group at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. She joined IBM in 1980 at the IBM East Fishkill facility in the Polymer Science and Technology Group, moving to the Research Division in 1990. The bulk of her professional career has focused on adhesion and related fields as they pertain to microelectronics conductor/insulator interfaces, in particular the adhesion of polyimide to inorganic surfaces. Throughout her 25 years at IBM, she has worked on many interesting and diverse projects ranging from Cu/PI chip back-end-of-line processes to the application of MEMS to wireless communication. More recently she has been working to develop processes related to Si carrier build including Si through-vias, lamination, laser release, C4 joining, and under fill. Dr. Buchwalter has received an IBM Research Division Award, an IBM Outstanding Technical Achievement Award, and several IBM Patent Awards. She holds 11 patents and is a Master Inventor.

Edmund J. Sprogis received the B.S.E.E. degree from Worcester Polytechnic Institute, Worcester, MA, in 1978, and the M.S.E.E. degree from the University of Vermont, Burlington, in 1982. He joined IBM, Essex Junction, VT, in 1978, and is currently a Senior Engineer in the Systems and Technology Group, developing advanced 3-D semiconductor packaging technology and applications.


Hua Gan received the B.S., M.S., and Ph.D. degrees in materials science and engineering from Southeast University, China, Northeastern University, Boston, MA, and the University of California at Los Angeles, respectively. Following her study in electromigration and reliability in microelectronic interconnections, she joined IBM T. J Watson Center in 2004 as a post-doctorate, focusing on micro-joint development and reliability for silicon-on-package project. In 2005, she joined the IBM System And Technology Group, Hopewell Junction, NY, as an Advisory Engineer, working on C4 interconnects development. She is an author or coauthor of more than 15 technical papers. Dr. Gan is a member of the Material Research Society.

Raymond R. Horton is a Staff Engineer at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, where he is a member of the System-on-Package Group and is responsible for bonding, assembly, and testing of interconnections. His work experience includes at-panel display assembly and test and packaging. He is a coauthor of numerous technical publications and patents. Mr. Horton has received an IBM Outstanding Technical Achievement Award.

Robert J. Polastre received the Associate degree in electronic technology and the Bachelor’s degree from LaSalle University, Philadelphia, PA. He joined the IBM Research Division, Yorktown Heights, NY, in 1983. He is currently a Staff Engineer working in the System-on-Package Group. He is the author or coauthor of several papers on automated and thermal testing and is a coinventor of patents in these areas. Mr. Polastre received IBM Outstanding Technical Achievement Awards in 1990 and 1999 and an IBM Corporate Award in 1993 for his work on array testing of thin-film transistors.

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Steven L. Wright did graduate student work in electrical engineering at the University of Colorado and the University of California at Santa Barbara. He joined IBM in 1982 as a Research Staff Member. During his career at IBM, he has worked in four areas: materials science and device physics of III-V compound heterojunctions, liquid-crystal flat-panel display technology, development and marketing of high-resolution visualization technology and products, and silicon carrier packaging technology. He is currently a member of the System-on-Package Group in the Department of Electronic and Optical Packaging, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, focusing on test and reliability issues for silicon carrier technology. He has contributed to more than 150 publications. Dr. Wright has received six IBM Invention Achievement Awards and three IBM Research Division Awards.

John M. Cotte received the B.S. degree in chemical engineering from Bucknell University, Lewisburg, PA, in 1984, and the M.S. degree in materials science and engineering from the University of Pittsburgh, Pittsburgh, PA, in 1988. He is an Advisory Engineer at the IBM Thomas J. Watson Research CenterYorktown Heights, NY. He joined the IBM Research Division in 1988 and has worked in the Physical Sciences, Manufacturing Research, Silicon Technology and Electronic and Optical Packaging organizations. He has extensive experience in surface analysis and materials characterization, as well as unit process development in the areas of backend interconnects and chip packaging. Currently, he is working on novel processes to fabricate and integrate rf MEMS for communication applications, and through-via fabrication for 3-D integration and silicon packaging. He holds 39 U.S. patents Mr. Cotte has received 15 IBM Invention Achievement Awards.