3C-Silicon Carbide Nanowire FET: An Experimental and ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach Konstantinos Rogdakis, Seoung-Yong Lee, Marc Bescond, Sang-Kwon Lee, Edwige Bano, and Konstantinos Zekentes, Senior Member, IEEE

Abstract—Experimental and simulated I–V characteristics of silicon carbide (SiC) nanowire-based field-effect transistors (NWFETs) are presented. SiC NWs were fabricated by using the vapor–liquid–solid mechanism in a chemical vapor deposition system. The diameter of fabricated SiC NWs varied from 60 up to 100 nm while they were some micrometers long. Their I–V characteristics were simulated with SILVACO software, and special attention was paid to explore the role of NW doping level and NW/dielectric interface quality. The fabricated SiC-based NWFETs exhibit a mediocre gating effect and were not switchedoff by varying the gate voltage. Based on the simulations, this is a result of the high unintentional doping (estimated at 1 × 1019 cm−3 ) and the poor NW/dielectric interface quality. Moreover, a homemade algorithm was used to investigate the ideal properties of SiC-based NWFETs in ballistic transport regime, with NW lengths of 5–15 nm and a constant diameter of 4 nm for which the carrier transport is fully controlled by quantum effects. This algorithm self-consistently solves the Poisson equation with the quantum nonequilibrium Green function formalism. In the ballistic regime, devices with undoped SiC NWs exhibit superior theoretical performances (transconductance: ∼ 43.2 × 10−6 A/V and ION /IOFF = 1.6 × 105 for a device with 9-nm NW length) based on their simulated characteristics. Index Terms—Drift-diffusion (DD) model, field-effect transistor (FET), nonequilibrium Green function formalism (NEGF), β-silicon carbide (SiC) nanowires (NWs).

I. INTRODUCTION

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OW-DIMENSIONAL materials, particularly 1-D, have stimulated great interest due to their importance in basic scientific research and potential technological applications. One-dimensional materials like nanowires (NWs) and nanoManuscript received December 7, 2007; revised March 26, 2008. This work was supported in part by the Greek Ministry of Development (GSRT) under Grant 05NON-EU-265 and in part by the Korean Research Foundation funded by the Korean Government (MOEHRD) under Grant KRF-2005-005J07501.The review of this paper was arranged by Editor T. Kimoto. K. Rogdakis is with MRG, IESL, Foundation for Research and Technology—Hellas, University of Crete, 71110 Heraklion, Greece, and also with IMEP–LAHC/INP Grenoble, MINATEC, 38016 Grenoble, France (e-mail: [email protected]). S.-Y. Lee and S.-K. Lee are with the Department of Semiconductor Science and Technology, Chonbuk National University, Jeonju 561-756, Korea. M. Bescond is with the Laboratoire Matériaux et Microélectronique de Provence (L2MP), CNRS, Bât. Institut de Recherche sur les Phénomènes Hors Equilibre (IRPHE), 13384 Marseille, France (e-mail: [email protected]). E. Bano is with the Institute of Microelectronics, Electromagnetism and Photonics (IMEP)–LAHC/Institut National Polytechnique de Grenoble, MINATEC, 38016 Grenoble Cedex 01, France (e-mail: [email protected]). K. Zekentes is with the Microelectronics Research Group (MRG), Institute of Electronic Structure and Laser (IESL), Foundation for Research and Technology—Hellas, 71110 Heraklion, Greece (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.926667

tubes can function both as active devices and interconnects, and thus, they have the potential to provide two of the most critical functions in any integrated nanosystem. In addition, their low dimensionality—associated with new quantum size effects— has provided new ways to develop nanoscale electronics, optoelectronics, and, in general, nanostructures. Furthermore, theoretical calculations indicate that the chemical and physical properties of an NW could be much superior to those of bulk or thin film. On the other hand, silicon carbide (SiC) is widely investigated due to its physical properties like the wide bandgap, the high breakdown field strength, the high value of thermal conductivity, the high saturation carrier drift velocity, and the stability in high temperature as well as in corrosive environments. The combination of these properties with the advantages of NWs can result in devices with unique performance. Up to now, few experimental studies on SiC NW-based field-effect transistors (NWFETs) have been reported [1]–[4]. The first one by Seong et al. [1], [2] focuses on the electronic transport through 3C-SiC NWs. The analysis of I–V characteristics has shown that the NWs were highly n-typedoped with a resistivity of 2.2 × 10−2 Ω · cm for 0-V gate voltage and an estimated electron mobility of 15 cm2 /V · s. The second study on electrical transport through 3C-SiC NWs (NW diameter: ∼10 nm and length: 1.5 µm) was performed by Zhou et al. [3], [4]. Their SiC NWFET had slightly better performance (higher mobility and transconductance values as well as ION /IOFF ∼ 103 ) compared with the results reported in [1] and [2]. Moreover, a theoretical study, which was performed by Rogdakis et al. [5], on the 3C-SiC-based NWFET operation in ballistic and diffusive regimes by using nonequilibrium Green function formalism (NEGF) and drift-diffusion (DD) schemes, respectively, has been published. Based on this study, the SiC NWFETs have similar performance to the Si-based ones in both transport regimes, showing that the use of SiC as channel material in NWFETs will not degrade the electrical characteristics while it will offer all advantages from the SiC physical properties. In this paper, a detailed analysis of SiC-based NWFET operation is performed in both simulation and experimental levels. Many devices have been fabricated with different dimensions and device geometries, and their I–V characteristics have been compared with simulated ones. The simulation has been performed by using the SILVACO software [6] by considering a carrier transport dominated by DD. The effect of NW doping level and NW/dielectric interface quality on the performance of NWFETs was fully investigated. An optimum doping value has been determined for an NWFET with ideal interface and with

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ROGDAKIS et al.: 3C-SILICON CARBIDE NANOWIRE FET: AN EXPERIMENTAL AND THEORETICAL APPROACH

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III. SIMULATION TOOLS

Fig. 1.

Schematic view of SiC NWFET.

Fig. 2.

Scanning-electron-microscope photo of one of the SiC NWFETs.

geometry similar to that of the fabricated devices. The in-house developed algorithm [5] has not been used in this case since the dimensions of the fabricated NWFETs were large enough to make the quantum effects and the ballistic components in the resulting channel current negligible. Nevertheless, an optimum NWFET structure operating in ballistic mode is proposed, following a systematic study of the effects of NW length to the performance of the devices. II. NWFET FABRICATION SiC NWs were grown by using a hot-wall chemical vapor deposition (CVD) system with a methyltrichlorosilane (CH3 SiCl3 ) source precursor (see a more detailed information about the synthesis and material characteristics of cubic SiC NW in [1] and [2]). The SiC NWs had a diameter of < 100 nm and lengths of several micrometers. For electrical transport measurements of the SiC NWFET, as-synthesized grown SiC NWs were prepared on a highly doped silicon wafer, prepatterned by a photolithography process with a 300-nm-thick CVD-prepared silicon nitride (Si3 N4 ) layer. The highly doped (> 1020 cm−3 ) n+ Si wafer served as a back-gate electrode in three-probe FET structures (Fig. 1). Prior to the metal deposition (Ti/Au = 50/150 nm) by electron-beam evaporation, the native oxide on SiC NW was removed by dipping in buffered hydrofluoric (HF) acid for 30 s. Then, source and drain (S/D) electrodes (Ti/Au) were defined by conventional e-beam lithography and lift-off process. Fig. 2 shows the single SiC NWFET prepared on the Si3 N4 /n Si wafer in three-probe FET configuration.

A commercial simulation tool [6] is used, which solves the Boltzmann transport equation within the DD approximation self-consistently with the Poisson equation. Indeed, at the micrometer scale, the DD model used in SILVACO is a welladapted tool that is used to describe electronic transport in semiconductor devices operating within a diffusive transport regime. To obtain accurate results for MOSFET simulations, it is necessary to account for the mobility degradation that occurs inside inversion layers. The degradation normally occurs as a result of the substantially higher surface scattering near the semiconductor-to-insulator interface. It is well known that fixed charges near the gate side are responsible for the shift of the threshold voltage and that interface trap charges can change the subthreshold slope. The aforementioned charges are more critical in the case of an NWFET where the surfaceto-volume ratio is very high. In this paper, in order to have as much as more realistic simulation, a mobility model that includes transverse field, doping dependent, and temperaturedependent parts was used. The simulation of the experimental I–V curves was performed by varying the doping level of the NWs and by taking into account the fixed charge and interface trap charge effects. The simulation has been performed for devices that have the same geometry and material properties as the experimental ones presented in the previous section (Fig. 1). The only difference exists in the shape of the NW cross section, which is square for the simulated devices and circular for the experimental NWs. As shown in [7], the shape of the NW cross section has a minor impact on the electron energy even for extremely narrowed wires. In order to explore the upper performance limit of SiC NWs, i.e., in ballistic transport regime, a homemade algorithm is used which self-consistently couples the electrostatic potential Usc (given by the Poisson equation) and the charge distribution ρ (resulting from the Schrödinger equation) inside the device [5]. The first step is to identify a suitable basis set and Hamiltonian matrix (H) for the isolated channel of transistor. The trigated NW [along (100) orientation] transistors, with square cross section, are treated in a simplified tight-binding theory (one orbital per atom and only first-nearest-neighbor interactions) equivalent to the ellipsoidal energy band approximation. The second step is to compute the self-energy matrices, namely, ΣS , ΣD , and Σscat , which describe how the channel couples to the S/D contacts and to the scattering process (in this paper, Σscat is zero), respectively. Then, the retarded Green’s function is computed as follows: 1 G(E) = (E + i0+ )I − H − ΣS − ΣD (1) where E is the energy, and I is the unity matrix. Once the self-consistency is reached, the electrical current (at 300 K) was calculated by using the NEGF formalism 4e I= (2) T (E) [fs (E) − fD (E)] dE h where T (E) = Trace(ΓS GΓD G+ ) (G is the retarded Green’s function, and ΓS/D = i[ΣS/D −Σ+ S/D ]) is the S/D transmission coefficient (the extra factor of two comes from the valley

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degeneracy due to the spin), and fS/D (E) is the S/D Fermi function. A detailed description of the general theory is given in [8]. IV. SiC-BASED NWFET ELECTRICAL CHARACTERISTICS The drain current (ID ) versus the source–drain voltage (VDS ) and the gate voltage (VG ) was systematically measured. SiC NW channel current modulation has been achieved by applying a bias to the Si substrate which was used as a back gate in the FET structures. Fig. 3(a) and (b) shows the drain current versus the drain–source voltage (ID –VDS ) characteristic curves of a single SiC NWFET [a diameter of ∼90 nm and a channel length of ∼4.4 µm (see Figs. 1 and 2)] at different gate voltages (VG ) in the range of +40 to −40 V. It clearly shows that the single SiC NWFET operated at higher VG than the state-ofthe-art metal–oxide–semiconductor FETs (conventional planar MOSFETs operate at VG ∼ 1 V) due to the thick nitride layer (300 nm). Fig. 3(c) shows ID as a function of VG of the single SiC FET with a VDS of 3 V. The figure suggests that the single SiC NWFETs have the following characteristics: 1) are of n-type conductivity; 2) have ohmic contacts to SiC NWs; and 3) characterized by a small gate-effect in agreement with previous reports [1], [2]. The ON/OFF current ratio (ION /IOFF ) could not be extracted from gate characteristics, as shown in Fig. 3(c), because the SiC NWFET could not be completely depleted even at high gate bias voltages up to −40 V. The weak gating effect indicates high carrier concentration close to the metallic limit. This high n-type character of the NWs is attributed to the high density of donor states resulting quite probably from stacking faults [9]. Obviously, the NW doping level effect to the SiC NWFET operation should be studied for further device optimization. Moreover, the electron field effect mobility (µ) and the carrier concentration (n) are calculated by using the approximate relationship of cylinder-plate capacitance model [1], [10] µ=

gm · L2 C · VDS

(3)

where gm is the transconductance which can be obtained from the slope of the ID versus VG plot, L is the length of the NW, C is the capacitance of the SiC NW, and VDS is the drain–source voltage. To estimate the carrier concentration as noticed in (3), the capacitance is calculated by using the formula: C ≈ 2πε0 εL/ ln(2h/r), where h is the thickness of Si3 N4 (300 nm), and r is the radius of the NW (45 nm) with a quasi-circular cross-sectional approximation. We also estimated the carrier concentration with the relationship I = nqµEA, where n is the electron carrier concentration, E is the electric field, µ is the electron mobility, and A is the area. The estimated electron carrier density and the field-effect carrier mobility for the single SiC NWFETs were estimated to be ∼1.7 × 1020 cm−3 and ∼ 0.5 cm2/V·s, respectively. This estimated mobility is very low compared with that expected in bulk and/or thin-film 3C-SiC. Fig. 4 shows the simulated I–V characteristics of SiC NWFETs with NW dimensions of 90 nm diameter and 4.4 µm length. An excellent agreement between the experiment and the simulation is obtained for the following: 1) an n-type doping of NWs equal to 1 × 1019 cm−3 ; 2) maximum body mobility

Fig. 3. Experimental characteristics of the single SiC NWFET. (a) ID –VDS characteristics curves, showing n-type semiconductor behavior, for the VG values of +40, +20, 0, −20, and −40 V. (b) Enlarged plot of (a). (c) ID –VG curve at VDS of 3 V.


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TABLE 1 COMPARISON OF THE SIMULATED DEVICE PERFORMANCE WITH IDEAL INTERFACE

Fig. 4. Simulated characteristics of the single SiC NWFET. (a) ID –VDS characteristic curves for the VG values of +40, +20, 0, −20, and −40 V. (b) Enlarged plot of (a). (c) ID –VG curve at VDS of 3 V.

and surface mobility equal to 57.75 and 2.51 cm2 /V · s, respectively; 3) density of fixed charge Qf = 8.52 × 1013 cm−2 ; and 4) density of interface trap electron acceptor states Qit [11], [12] that is equal to ∼1.5 × 1012 eV−1 · cm−2 (Fig. 4).

In [12], a detailed analysis of 3C-SiC/SiO2 system in terms of Qf and Qit is presented (at the interface of n-type thinfilm 3C-SiC/SiO2 MOS capacitors, the density of traps close to the conduction band edge reached values in the range of 1011 cm−2 · eV−1 by using suitable processing [12]). Based on the aforementioned parameters, SILVACO calculates a total mobility value equal to ∼3.5 cm2 /V · s. The difference between the value of total mobility that SILVACO predicts (∼3.5 cm2 /V · s) and the estimated from the cylinder-plate capacitance model value (0.5 cm2 /V · s) could be justified by the lack of accuracy of the cylinder-plate capacitance model [interface traps and parasitic effects are neglected in (3), which leads to underestimated experimental mobility values (at least a factor of two)] [13], [14]. This remark may also explain the discrepancy between the estimated experimental value (∼1.7 × 1020 cm−3 ) of doping level and the one resulting from SILVACO calculations. Another difficulty with NWFETs is the experimental estimation of the interface trap density and fixed charges. The classical C–V measurement approach is not suitable for NWFET configuration due to the very small device capacitance. New elegant experimental techniques have to be developed. Nevertheless, by using the SILVACO software tool, and through the best fitting between the experiment and the simulation, the Qf and the density of interface trap states of our experimental devices were roughly estimated. Based on the simulations (Table I and Figs. 5 and 6), it is obvious that the control of the unintentional doping and the NW/dielectric interface quality is necessary to obtain high-performance NWFETs. Therefore, the effect of doping on the performance of the NWFET was studied by simulating the operation of devices with the same geometry as that of the experimental devices and with ideal (Table I and Figs. 5 and 6) NW/silicon nitride interface (zero defects). The simulation was performed from a maximum doping level of 1 × 1019 cm−3 , and it was gradually decreased down to a level of 1015 cm−3 . We assumed perfect SiC NW/nitride interface; thus, this time, we used the maximum value of bulk 3C-SiC electron mobility, which is ∼1000 cm2 /V · s, as the maximum body mobility [ohmic (pure-lattice) electron mobility]. Table I summarizes the results of the electrical devices’ performance with ideal NW/dielectic interface in terms of transconductance and FE electron mobility

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Fig. 7. ID –VG of ballistic SiC NW devices. Fig. 5. Simulated IDS –VDS characteristic for the n-type-doped SiC NWFETs with 5 × 1015 cm−3 and ideal interface (no defects).

TABLE II DEVICE CHARACTERISTICS IN BALLISTIC REGIME

V. SiC NWFET OPERATION IN BALLISTIC REGIME

Fig. 6. Simulated transfer IDS –VGS characteristic for the n-type-doped SiC NWFETs with 5 × 1015 cm−3 and ideal interface.

(using the approximate cylinder-capacitance model) for different NW doping levels. The calculations showed that, in the absence of interface fixed oxide and interface traps, and at a doping level of 1017 and below, it is possible to have a good gating effect (Fig. 5) even for small VD , and the FET switches-off with small negative gate voltage (Vth ∼ −0.5 V) (Fig. 6). Optimum operation has been obtained for an NW doping level of 5 × 1015 cm−3 (as shown in Table I). Figs. 5 and 6 show the corresponding SiC NWFET electrical characteristics. If very high values of fixed charge in dielectric and interface trap states are taken into account in the aforementioned simulation, it turns out that the device performance is poor independently of the doping level. In this case, the NWFET cannot be switched-off (for high Qf and Qit values) even for low doping concentrations. This shows that the effect of the interface quality is as critical for the device performance as the value of the doping level. A combination of a low doping level (lower than the 1019 cm−3 ) and as better as possible NW/dielectric interface (as smaller as possible Qf and Qit values) would lead to a much better device performance.

Fig. 7 shows the simulated, with the homemade algorithm [5], transfer characteristics of trigated SiC NWFETs operating in the ballistic transport regime. In all simulations, we considered NWs/channels with the following characteristics: 1) trigated; 2) square cross sections (4 × 4 nm); 3) 1-nm gate-oxide width; 4) channel length from 5 to 15 nm; and 5) 4-nmwide S/D electrodes. As it was expected, their performance is superior (and equivalent to their counterpart Si NWFETs [5]) compared with the experimental and the simulated devices operating in the diffusive transport regime (see Section IV). As the NW length decreases, the tunneling current in the subthreshold region becomes higher and has a negative impact to the device performance. The tunneling between S/D becomes more significant as long as the channel length reduces toward 5 nm, due to the potential barrier width decrease. At low gate voltage, the tunneling component predominates and degrades both the subthreshold slope and the IOFF . In the case of 5-nm NW length, we have the smallest ION /IOFF ratio (due to the high IOFF tunneling current). On the other hand, as the channel length increases, the transconductance decreases. From the aforementioned analysis, we see that a device of 9 nm could be an interesting opportunity to obtain a good compromise between a high ION /IOFF and, at the same time, a reasonably good transconductance value (Table II). VI. CONCLUSION The electronic transport in ballistic and diffusive 3C-SiC NWFETs has been theoretically investigated by using a


homemade 3-D quantum–mechanical simulation code and a commercial tool, respectively. The commercial tool was also used to simulate the experimental electrical characteristics of fabricated 3C-SiC NWFETs. Both the simulation and experimental results show that the NW doping level and the NW/dielectric interface are critical parameters for the device performance. We accurately simulated the experimental results when we considered, in our simulations, the interface trap states and the fixed charges near the interface as well as an appropriate model for the carrier mobility. The simulation results have showed that the ideal donor doping level for the SiC NWFETs would be around 5 × 1015 cm−3 when ideal NW/dielectric interface is considered. Based on the simulation, the NWFET could not be switched-off when high Qf and Qit values were used, even for low NW doping level. A combination of low doping level (lower than the 1019 cm−3 ) and as better as possible NW/dielectric interface would lead to better device performance. Future prospects for resolving these problems are the following: 1) use of NW dopant implantation for compensating excess carriers due to the unintentional doping; 2) use of NW and dielectric growth techniques as well as growth conditions appropriate to obtain better crystal quality and, thus, less unintentional doped NWs and interface with as lower as possible defects [12]; and 3) scaling down the NW dimensions (NW oxidation and HF etching to reduce the initial NW diameter, and fabrication of metal contacts with smaller distance between them to reduce the NW length) in order to enhance the device performance. ACKNOWLEDGMENT S. K. Lee would like to thank Prof. H.-J. Choi and H.-K. Seong for the discussions and sample preparations. R EFERENCES [1] H. K. Seong, H. J. Choi, S. K. Lee, J. I. Lee, and D. J. Choi, “Optical and electrical transport properties in silicon carbide nanowires,” Appl. Phys. Lett., vol. 85, no. 7, pp. 1256–1259, Aug. 2004. [2] H. K. Seong, H. J. Choi, S. K. Lee, J. I. Lee, and D. J. Choi, “Fabrication and electrical transport properties of CVD grown silicon carbide nanowires for field effect transistor,” Mater. Sci. Forum, vol. 527–529, pp. 771–774, 2006. [3] W. M. Zhou, F. Fang, Z. Y. Hou, L. J. Yan, and Y. F. Zhang, “Field-effect transistor based on β-SiC nanowire FET,” IEEE Electron Device Lett., vol. 27, no. 6, pp. 463–466, Jun. 2006. [4] W. Zhou, X. Liu, and Y. Zhang, “Simple approach to β-SiC nanowires: Synthesis, optical, and electrical properties,” Appl. Phys. Lett., vol. 89, no. 22, pp. 223 124-1–223 124-3, Nov. 2006. [5] K. Rogdakis, M. Bescond, E. Bano, and K. Zekentes, “Theoretical comparison of 3C-SiC and Si nanowire FETs in ballistic and diffusive regimes,” Nanotechnology, vol. 18, no. 47, pp. 475 715-1–475 715-5, Nov. 2007. [6] ATHENA and ATLAS Simulation Program, SILVACO Int., Santa Clara, CA, Oct. 2004. [7] Y. M. Niquet, C. Delerue, G. Allan, and M. Lannoo, “Method for tightbinding parametrization: Application to silicon nanostructures,” Phys. Rev. B, Condens. Matter, vol. 62, no. 8, pp. 5109–5116, Aug. 2000. [8] S. Datta, “Nanoscale device modeling: The Green’s function method,” Superlattices Microstruct., vol. 28, no. 4, pp. 253–278, Oct. 2000. [9] S. Y. Lee, T. H. Kim, D. I. Suh, N. K. Cho, H. K. Seong, S. W. Jung, H. J. Choi, and S. K. Lee, “A study of dielectrophoretically aligned gallium nitride nanowires in metal electrodes and their electrical properties,” Chem. Phys. Lett., vol. 427, no. 1–3, pp. 107–112, Aug. 2006. [10] T. Tachibana, H. S. Kong, Y. C. Wang, and R. F. Davis, “Hall measurements as a function of temperature on monocrystalline SiC thin films,” J. Appl. Phys., vol. 67, no. 10, pp. 6375–6377, May 1990.

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[11] S. Suzukia, S. Harada, R. Kosugi, J. Senzaki, W.-J. Cho, and K. Fukuda, “Correlation between channel mobility and shallow interface traps in SiC metal–oxide–semiconductor field-effect transistors,” J. Appl. Phys., vol. 92, no. 10, p. 6230, Nov. 2002. [12] A. Schöner, M. Krieger, G. Pensl, M. Abe, and H. Nagasawa, “Fabrication and characterization of 3C-SiC-based MOSFETs,” Chem. Vap. Depos., vol. 12, no. 8/9, pp. 523–530, Sep. 2006. [13] S. A. Dayeh, C. Soci, P. K. L. Yu, E. T. Yu, and D. Wang, “Influence of surface states on the extraction of transport parameters from InAs nanowire field effect transistors,” Appl. Phys. Lett., vol. 90, no. 16, p. 162 112, Apr. 2007. [14] D. R. Khanal and J. Wu, “Gate coupling and charge distribution in nanowire field effect transistors,” Nano Lett., vol. 7, no. 9, pp. 2778–2783, Sep. 2007.

Konstantinos Rogdakis received the B.S. degree in applied mathematics and physics and the M.S. degree in microsystems and nanodevices from the National Technical University of Athens, Athens, Greece, in 2005 and 2006, respectively. He is currently working toward the Ph.D. degree (“in cotutelle”) in nanoelectronics at the Institut National Polytechnique de Grenoble, Grenoble, France, and in the Physics Department, University of Crete, Heraklion, Greece.

Seung-Yong Lee received the B.S. degree in physics and the M.S. degree in semiconductor devices from Chonbuk National University, Jeonju, Korea, in 2005 and 2007, respectively, where he is currently working toward the Ph.D. degree in the Department of Semiconductor Science and Technology, focusing on the nanoscale semiconductor device design, fabrication, and characterization with wide bandgap semiconductor (SiC, GaN, ZnO, etc.). He has contributed to about 15 scientific papers.

Marc Bescond received the M.S. degree in material engineering from the National Institute of Applied Sciences, Lyon, France, in 2001, and the Ph.D. degree from the University of Provence, Marseille, France, in 2004. From 2005 to 2007, he was an Associate Professor of electrical engineering and physics with the Grenoble Institute of Technology, Grenoble, France. Before attending Grenoble, he was a Postdoctoral Fellow with the Device Modelling Group, University of Glasgow, Glasgow. Since October 2007, he has been a Researcher (Chargé de Recherche) with the Laboratoire Matériaux et Microélectronique de Provence, CNRS, Bât. Institut de Recherche sur les Phénomènes Hors Equilibre, Marseille, France. His research interests include the modeling of nanoelectronic devices, the 3-D simulations of quantum transport, and the band-structure calculations.

Sang-Kwon Lee received the B.S. degree in physics from Dongguk University, Seoul, Korea, in 1988, the M.S. degree in applied physics from the University of Texas, Arlington, in 1991, and the Ph.D. degree from the Royal Institute of Technology, Stockholm, Sweden, in 2002. Then, he studied his postdoctoral courses at the University of California, Berkeley, and at Lawrence Berkeley National Laboratory, Berkeley, from 2002 to 2003. From 1994 to 1998, he was a Research Engineer with Mando Central R&D Center, Korea, where he was involved in developing various sensor and actuators for automotive applications. He is currently an Assistant Professor with the Department of Semiconductor Science and Technology, Chonbuk National University, Jeonju, Korea. He is the author or coauthor of around 50 technical papers and has extensive experience in the fabrication and characterization of the nanoscale devices.

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Edwige Bano received the M.S. degree in optic, optoelectronic, and microwaves, with specialization in physics of semiconductors, and the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, in 1994 and 1997, respectively. She is currently an Associate Professor with INPG and is the Supervisor of the SiC activities with the Institute of Microelectronics, Electromagnetism and Photonics, LAHC, MINATEC, Grenoble. She is the author or coauthor of more than 40 journal and conference publications. Her research interests include the characterization and modeling of SiC devices.


Konstantinos Zekentes (M’03–SM’06) received the B.S. degree in physics from the University of Crete, Heraklion, Greece, in 1983, and the Ph.D. degree in physics of semiconductors from the University of Montpellier, Montpellier, France, in 1989. He is currently a Senior Researcher with the Microelectronics Research Group (MRG), Institute of Electronic Structure and Laser, Foundation for Research and Technology—Hellas, Heraklion. The objective of his work is to coordinate and supervise the MRG’s effort on SiC-related technology for elaborating high-power/high-frequency devices. He is also involved in the growth of SiC nanostructures. He has more than ninety journal and conference publications and is the holder of one U.S. patent.