60 GHz 28 nm CMOS transformer-coupled power amplifier for WiGig applications B. Leite, E. Kerhervé, A. Ghiotto, A. Larie, B. Martineau and D. Belot
that the performance would not be significantly degraded by parasitics (Fig. 2a). The parasitic elements extracted from the layout were then combined with the intrinsic model supplied by the foundry, as illustrated in Fig. 2b. D
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A 60 GHz power amplifier (PA) based on a 28 nm CMOS technology is presented for WiGig applications. It consists of a two-stage pseudodifferential common-source structure using low-power and low-Vt transistors, capacitive neutralisation for isolation enhancement and integrated transformers for impedance matching, power splitting, power combining and balanced-to-unbalanced transformation purposes. The output-stage transistors have a measured 1 dB output compression point (OCP1 dB) of 10.2 dBm, a 10.2 dB gain and a peak power added efficiency (PAE) as high as 35%. The fabricated PA achieves a 12 dBm OCP1 dB, a 15.3 dB gain and a peak PAE better than 20% while occupying a silicon active area of only 0.037 mm2.
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It is important to note that the transistors’ accesses, the transformers, RF pads (which are part of the input and output matching networks) and interconnections, especially the cross-connections of the neutralisation capacitors, were all designed and modelled through the use of EM simulators. Power transistor experimental results: The power transistor was fabricated and large-signal measurements were carried out on-wafer at room temperature using a focus load–pull system. The optimal load impedance in terms of output power is found to be ZLoad = 14 + j10 Ω. Applying this impedance to the output of the transistor, the large-signal tests presented in Fig. 3 were carried out at 60 GHz impedance when the transistor is biased at VGS = 0.75 V and VDS = 1.1 V. A peak power added efficiency (PAE) as high as 35% is observed with a 1 dB output compression point (OCP1 dB) of 10.2 dBm, a 12.6 dBm maximum output power and a 10.2 dB gain. 18
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Design considerations: The proposed PA was designed using a bulk 28 nm CMOS technology from STMicroelectronics. The adopted topology is shown in Fig. 1. It consists of a two-stage pseudo-differential common-source amplifier, making extensive use of integrated transformers. These transformers are responsible for power splitting and combining, as well as the conversion between single-ended and differential modes, and ESD protection at the input and output of the circuit. The three transformers also supply through their centre-taps a path for the DC bias feeds, both for VBias at the transistors’ gates and VDD at their drains. Furthermore, they constitute a crucial part of the input, interstage and output matching networks.
a Layout of power transistor b Extracted transistor model including layout parasitics
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Introduction: Recent advances in silicon-based technologies along with a demand for high-speed wireless connections have driven the development of wireless local area networks (WLANs) standards operating at 60 GHz such as WiGig [1]. Such applications require a low-cost and low-power implementation, which favours the adoption of system-on-chip implementations for the transceivers. Therefore, owing to the large amount of digital circuitry integrated in such systems, the use of advanced CMOS nodes becomes the most suitable technology choice. Nevertheless, the use of downscaled processes poses a number of challenges in the design of analogue and RF blocks. Namely, for the design of power amplifiers (PAs), the low breakdown voltage makes it increasingly difficult to obtain high-output power levels. Moreover, as the back-end-of-line of the technologies is scaled, passive devices tend to become increasingly lossy. This Letter presents the design of a 28 nm CMOS PA targeting WiGig applications in the 60 GHz band.
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Fig. 1 Schematic of 60 GHz 28 nm CMOS PA
The designed baluns adopted the structure proposed in [2], where a capacitor is added to the single-ended side in order to optimise its common-mode rejection ratio at the working band. The transformer’s dimensions were therefore tuned in order to achieve a good trade-off among impedance matching, conversion balance and insertion loss. To ensure stability and enhance the reverse isolation of the PA, crosscoupled capacitive neutralisation allowing an adequate compensation for the feedback effect of the transistors’ gate–drain capacitances was adopted [3]. All of the capacitors in the circuit present a MOM constitution. The dimensioning of the transistors was done as a compromise between intrinsic gain and power capability and the influence of parasitics, which rise as the transistors’ width increases. Therefore, 1 µm fingers were used for both transistors, with the power transistor totalling 90 fingers and the driver transistor including 45 fingers. Special care was taken in laying out the transistors, and a stair-shaped layout was used so
Fig. 4 Micrograph of fabricated PA
PA experimental results: The designed PA was fabricated and its performance was measured on-wafer with an Agilent E83612 vector network analyser for S-parameters and using the same setup as for the single power transistors large-signal characterisation. The circuit core occupies 0.037 mm2, whereas the total area of the PA including pads amounts to 0.255 mm2, as illustrated by the chip micrograph in Fig. 4. The PA was biased with VBias = 0.75 V and VDD = 1.1 V.
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The measured and simulated S-parameters are reported in Fig. 5. The PA presents a power gain superior to 15 dB from 64 to 69 GHz. The observed frequency shift from the 60 GHz band is due to an inaccuracy in the adopted model, which was at an early stage at the time of the design. The presented simulations fit well with the measurements due to the use of an updated model. Moreover, thanks to the capacitive neutralisation, isolation is better than 40 dB up to 80 GHz and the amplifier is unconditionally stable in the whole considered band. 20 10
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Conclusion: A 60 GHz PA designed in a 28 nm CMOS technology was presented in this Letter. The PA presents a two-stage pseudo-differential common-source topology using capacitive neutralisation and extensively employing integrated transformers. The fabricated PA achieves a 12 dBm OCP1 dB, a 15.3 dB gain and a peak PAE superior to 20% while occupying a silicon area of only 0.037 mm2. To the authors’ knowledge, this is the highest reported PAE and OCP1 dB in a 28 nm CMOS PA. Acknowledgment: This work was supported by the ENIAC European project Mirandela. © The Institution of Engineering and Technology 2014 28 May 2014 doi: 10.1049/el.2014.1979 One or more of the Figures in this Letter are available in colour online.
E. Kerhervé, A. Ghiotto and A. Larie (IMS Laboratory, CNRS UMR 5218, IPB, University of Bordeaux, Talence 33405, France) B. Martineau and D. Belot (STMicroelectronics, Crolles 38926, France)
1 Hansen, C.J.: ‘WiGiG: multi-gigabit wireless communications in the 60 GHz band’, IEEE Wirel. Commun., 2011, 18, (6), pp. 6–7, doi: 10.1109/MWC.2011.6108325 2 Aloui, S., Leite, B., Demirel, N., Plana, R., Belot, D., and Kerherve, E.: ‘High-gain and linear 60-GHz power amplifier with a thin digital 65 nm CMOS technology’, IEEE Trans. Microw. Theory, 2013, 61, (6), pp. 2425–2437, doi: 10.1109/TMTT.2013.2258169 3 Chan, W.L., and Long, J.R.: ‘A 58–65 GHz neutralized CMOS power amplifier with PAE Above 10% at 1 V supply’, IEEE J. Solid-State Circuits, 2010, 45, (3), pp. 554–564, doi: 10.1109/JSSC.2009.2039274 4 Zhao, D., and Reynaert, P.: ‘A 60 GHz dual-mode class AB power amplifier in 40 nm CMOS’, IEEE J. Solid-State Circuits, 2013, 48, (10), pp. 2323–2337, doi: 10.1109/JSSC.2013.2275662 5 Shirinfar, F., et al.: ‘A fully integrated 22.6 dBm mm-wave PA in 40 nm CMOS’. IEEE RF Integrated Circuits Symp., Seattle, WA, USA, June 2013, pp. 279–282, doi: 10.1109/RFIC.2013.6569582 6 Thyagarajan, S.V., Niknejad, A.M., and Hull, C.D.: ‘A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS’. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, September 2013, pp. 1–4, doi: 10.1109/CICC.2013.6658408 7 Ogunnika, O.T., and Valdes-Garcia, A.: ‘A 60 GHz class-E tuned power amplifier with PAE > 25% in 32 nm SOI CMOS’. IEEE RF Integrated Circuits Symp., Montreal, Canada, June 2012, pp. 65–68, doi: 10.1109/RFIC.2012.6242233 8 Vidojkovic, V., et al.: ‘A low-power 57-to-66 GHz transceiver in 40 nm LP CMOS with -17 dB EVM at 7 Gb/s’. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, February 2012, pp. 268–270, doi: 10.1109/ISSCC.2012.6177011 9 Cohen, E., Ravid, S., and Ritter, D.: ‘60 GHz 45 nm PA for linear OFDM signal with predistortion correction achieving 6.1% PAE and −28 dB EVM’. IEEE RF Integrated Circuits Symp., Boston, MA, USA, June 2009, pp. 35–38, doi: 10.1109/RFIC.2009.5135484 10 Essing, J., Mahmoudi, R., Pei, Y., and v. Roermund, A.: ‘A fully integrated 60 GHz distributed transformer power amplifier in bulky CMOS 45 nm’. IEEE RF Integrated Circuits Symp., Baltimore, MD, USA, June 2011, pp. 1–4, doi: 10.1109/RFIC.2011.5940684
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Fig. 6 Measured and simulated gain, output power and PAE at 64 GHz
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Table 1: Comparison of 60 GHz sub-65 nm CMOS PAs
B. Leite (GICS-UFPR, Department of Electrical Engineering, Federal University of Paraná (UFPR), Curitiba 81.531-980, Brazil)
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The large-signal measurements and simulations at 64 GHz are shown in Fig. 6. An OCP1 dB of 12 dBm is obtained, with a 13.7% PAE at OCP1 dB and a peak PAE of 20.2%. Moreover, it can be observed that the output saturation power, as well as the OCP1 dB, are relatively flat in the band between 60 and 70 GHz, as shown in Fig. 7. An overall good match is observed between measured and simulated results. The most pronounced divergence appears for higher power levels (Pin > 10 dBm) for which the transistor simulation model does not remain valid.
to achieve a substantially higher PAE and a slightly superior OCP1 dB while occupying quite a reduced area.
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Fig. 7 Measured saturation power, OCP1 dB, gain and peak PAE
Table 1 compares the obtained results to other published 60 GHz PAs in sub-65 nm CMOS technologies. The PA proposed in [4], designed using 40 nm CMOS, obtains overall superior performances as it uses twice the number of power cells compared with our design, which explains its larger area occupancy. Such an approach is even more pronounced in the case of [5] where 32 parallel PAs are used, resulting in the highest gain and output power, which come at the cost of a low PAE and an area superior to 2 mm2. To the authors’ knowledge, the PA in [6] is, to this date, the sole other realisation using the 28 nm technologic node. As it includes an additional gain stage in its topology, the gain in [6] is considerably higher. Our work, on the other hand, manages
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