A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications F. Pellizzer1, A. Benvenuti1, B. Gleixner2, Y. Kim2, B. Johnson2, M. Magistretti1, T. Marangon1, A. Pirovano1, R. Bez1, G. Atwood2 1. STMicroelectronics, Via C. Olivetti 2, 20041 Agrate Brianza (Milan), Italy 2. Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA Tel.: +39-039-6036813, E-mail:
[email protected]
Abstract A 90nm technology node Phase Change Memory (PCM) process, based on a chalcogenide material storage element with a vertical pnp Bipolar Junction Transistor (BJT) selector device, is presented. The small cell area of 12F2, the good electrical results, and the intrinsic reliability demonstrate the viability of the PCM cell concept. Programming currents as low as 400uA, very good distributional data achieved on multi-megabit arrays for programming (set and reset), endurance, and retention, demonstrate the suitability of PCM for fabrication of a high density array at 90nm.
Introduction Flash memories have been able to scale for more than 15 years, boosting the recent impressive growth of the portable equipment market and becoming the mainstream Non-Volatile Memory (NVM) technology. Projecting into the next decade, though, there are several fundamental limitations that must be solved to push the floating-gate concept beyond the 32nm technology node. The increasing complexity of floating gate scaling leaves room for the investigation of alternative NVM concepts that promise better scalability, improved performances, and competitive cost with Flash. Among them, chalcogenide-based PCM devices are the most promising, allowing a fast write and read, good read signal window, byte alterability, extended endurance, and intrinsic scalability in the deca-nanometer range [1]. PCM learning has improved rapidly over the past three years, and the results so far obtained forecast the ability to fabricate high density memory with some commercial potential [2]. In this work we demonstrate the capability of the PCM technology to be integrated at 90nm with a 12F2 1T/1R cell based on a vertical BJT selector, suitable for high density stand-alone memory applications.
Process Architecture The 90nm PCM process architecture (Tab.1 and 2) has been developed considering the small cell size requirements, the process cost, and the high performance characteristics, in particular in terms of fast random access-time typical of NOR Flash applications. PCM cell structure. The PCM cell is a 1T/1R structure, where the select transistor is a vertical pnp-BJT, and the resistor, the so-called storage element, is a heater with the chalcogenide material on top. The base of the pnp-BJT constitutes the word-line, while the emitter is connected to the bottom electrode of the storage element (Fig.1) through a tungsten pre-contact. The collector is formed by the common ground. The STI depth is 270nm to optimize the BJT active and passive characteristics. The cell layout is fully self-aligned, using a cross-point architecture between the active area and the emitter and base implant stripes (Fig.2). The cell area is 0.0968um2 (12F2), obtained with a x-pitch of 220nm and a y-pitch of 440nm. Emitter and base contact resistance has been optimized keeping both active areas salicided with CoSi2 (Fig.1). The heater, landed on a tungsten plug, can be either a µTrench [3] (Fig.3) or a sub-litho contact [4] (Fig.4), usually called Lance, as a function of the reset current minimization or of the process simplification, still retaining the same cell size. The chalcogenide material is a thin layer of Ge2Sb2Te5 (GST), capped with a Ti/TiN barrier. Front-end. Considering the STI depth requirement of the PCM cell, single STI approach has been used. The transistor architecture is defined considering the memory specification: 8nm gate oxide CMOS with dual-flavor CoSi2 transistor, in order to maximize the current and to sustain the 3V operation needed to program the cell. Back-end. The metallization has been chosen considering the cell layout and the compatibility with the state-of-the-art NOR Flash technology. 3 Cu lines have been integrated with line1 used in cell 1-4244-0005-8/06/$20.00 (c) 2006 IEEE
array for Word-Line (WL), line2 used in cell array as main Bit-Line, and line3 used only in periphery (or as global WL). The contact between line2 and GST line is formed using an ad-hoc strap.
Electrical Characterization The electrical demonstration of the 90nm PCM process architecture is mainly focused on the memory cell characteristics, since the MOS transistors are not impacted by the cell integration. One of the key aspects is the reduction of the reset current. The small contact area of the µTrench heater (~400nm2) is very effective in reducing the programming current down to 400uA (Fig.5). Despite its much larger contact area (~3000nm2), the Lance heater gives only double programming current, i.e. 700uA (Fig.6). This is justified by the structural differences between the two heaters, as can be appreciated from the I-V curves (Fig.7), which demonstrate the lower resistance of Lance with respect to µTrench. On the other side it is important to show the driving capabilities and the low reverse-bias leakage of the salicided vertical pnp-BJT. Fig.8 shows that the BJT delivers the reset current for µTrench at 1.4V, and only 0.15V more are required to reset a cell with Lance. Moreover the driving current is obtained together with a very low base-emitter leakage current in reverse bias (less than 10 pA at 3V), necessary to build a very high density array. Retention and endurance, the two most important aspects of reliability, have been characterized. The activation energy shows that at 90nm the retention meets the traditional requirement of 85°C for 10 years (Fig.9). The endurance of these scaled PCM storage elements is demonstrated to be in the range of 108 reset/set cycles (Fig.10), comparable with previous reports [3]. Finally the good programmed distributions obtained on multi Mb arrays for both PCM structures (Fig.11) demonstrate their potential manufacturability.
Conclusions The process architecture and the electrical results for a 90nm PCM technology with two alternative heater architectures and with a salicided pnp-BJT selector have been presented. The vertical and selfaligned cell structure results in a cell area of 0.0968um2, with programming current as low as 400uA, confirming the good scaling perspective of PCM. Reliability (retention and endurance) are demonstrated to be comparable to, or better than Flash. The tight programmed distributions of both µTrench and Lance storage elements make them suitable for fabrication of high density PCM array.
Acknowledgments The authors would like to acknowledge the support and many contributions from ST, Intel, and Ovonyx personnel.
References [1] S. Lai, “Current Status of the Phase Change Memory and its Future”, IEDM Tech. Dig., 2003. [2] G. Atwood and R. Bez, “Current Status of Chalcogenide Phase Change Memory”, DRC, 2005. [3] F. Pellizzer et al., “Novel µTrench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications”, Symp. On VLSI Tech., 2004. [4] S. Lai and T.Lowrey, “OUM – A 180nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications”, IEDM Tech. Dig., 2001.
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Table.1. CMOS technology parameters.
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