A Bridgeless Resonant Pseudoboost PFC Rectifier - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 11, NOVEMBER 2014

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A Bridgeless Resonant Pseudoboost PFC Rectifier Abbas A. Fardoun, Senior Member, IEEE, Esam H. Ismail, Senior Member, IEEE, Mustafa A. Al-Saffar, Member, IEEE, and Ahmad J. Sabzali, Member, IEEE

Abstract—In this paper, a new bridgeless single-phase ac–dc converter with a natural power factor correction (PFC) is proposed. Compared with existing single-phase bridgeless topologies, the proposed topology has the merits of less component counts. The absence of an input diode bridge and the presence of only one diode in the current path during each stage of the switching cycle result in higher power density and less conduction losses; hence, improved thermal management compared to existing PFC rectifiers is obtained. The proposed topology is designed to work in resonant mode to achieve an automatic PFC close to unity in a simple and effective manner. The resonant mode operation gives additional advantages such as zero-current turn-on in the active power switches, zero-current turn-off in the output diode and reduces the complexity of the control circuitry. Principle of operation and the feasibility of the proposed converter are provided. Detailed experimental and simulation results are presented. Index Terms—Bridgeless rectifier, high efficiency rectifier, low conduction losses, power factor correction (PFC), single-phase rectifier, total harmonic distortion (THD).

I. INTRODUCTION OWER supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment especially in the telecommunication and computer industries to meet harmonic regulations and standards, such as the EN61000-3-2. Also, higher power density and lower system cost are always very desirable features, especially for low power supplies. In addition, new energy saving initiatives (e.g., 80 PLUS) are forcing the designers to search for new topologies to further reduce losses while keeping low input-current harmonics and PFC capability. Most of the PFC rectifiers utilize a boost/buck–boost topology converter at their front end due to its high power factor (PF) capability [1]–[4]. However, a conventional PFC scheme has lower efficiency due to significant losses in the diode bridge. During each switching cycle interval, the current flows through three power semiconductor devices. The forward voltage-drop

P

Manuscript received June 11, 2013; revised September 21, 2013 and November 1, 2013; accepted December 3, 2013. Date of publication January 23, 2014; date of current version July 8, 2014. This work was supported in part by the United Arab Emirates University, Research Affairs office. This paper was presented at the 27th annual IEEE Applied Power Electronics Conference, Orlando, FL, USA, Feb. 2012 Recommended for publication by Associate Editor C. A. Canesin. A. A. Fardoun is with the Department of Electrical Engineering, University of United Arab Emirates, Al-Ain, UAE (e-mail: [email protected]). E. H. Ismail, M. A. Al-Saffar, and A. J. Sabzali are with the Department of Electrical Engineering, College of Technological Studies, Al-Shaab 36051, Kuwait (e-mail: [email protected]; [email protected], [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2013.2295317

Fig. 1. Proposed bridgeless ac–dc PFC converter with: (a) Positive output polarity. (b) Negative output polarity.

across the bridge diodes degrades the converter efficiency, especially at low-line input voltage. In response to these concerns, considerable research efforts have been directed toward the development of efficient bridgeless PFC circuit topologies [5]–[24]. A bridgeless PFC circuit allows the current to flow through a minimum number of switching devices compared to the conventional PFC circuit. Accordingly, the converter’s conduction losses can be significantly reduced, and higher efficiency and lower cost can be obtained. However, most of the previous proposed bridgeless PFC converters have at least one of the following drawbacks: 1) high components count, 2) components are not fully utilized over whole ac-line cycle, 3) complex control, 4) dc output voltage is always higher than the peak input voltage, 5) lack of galvanic isolation, and 6) due to the floating ground, some topologies require additional diodes and/or capacitors to minimize EMI. In order to overcome most of these problems, an interesting reduced component count topology has been introduced in [25]. However, the proposed topology in [25] still suffers from having at least two semiconductors in the current conduction path during each switching cycle. In [26], a zero current switch topology is presented. This topology has reduced-component count; however, the load is floating with respect to the input. A novel low-count topology has been introduced in [27]. The proposed topology has low-component count with an input stage similar to a boost converter. In this paper, a new bridgeless PFC circuit based on the modified boost converter is introduced and presented in Fig. 1(a) and (b). Compared with existing single-phase bridgeless topologies,

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the proposed topology has low component count, a single control signal, and nonfloating output. Since the topology operates in discontinuous conduction mode, the proposed converter is intended for low-power applications. The converter components are fully utilized during the positive and negative ac-line cycle. It should be mentioned here that the conventional and the Totem-pole bridgeless PFC boost rectifiers [19] have one less component than the proposed converter. However, these converters have significantly larger common-mode noise than the proposed converter because of the output ground which is connected to the ac source only during a positive half-line cycle. Also, unlike the proposed converter, the conduction loss in the semiconductors for the conventional and the Totem-pole bridgeless PFC boost rectifiers is high due to the presence of two semiconductor switches in the current flowing path during each switching cycle. A converter similar to the proposed converter of Fig. 1(a) was recently reported in [28] and [29]. However, the converter in [28] and [29] utilizes an extra resonant inductor in series with capacitor C1 ; hence, its circuit operation is completely different than the proposed converter. Moreover, unlike the proposed topology, the topology presented in [28] cannot be considered as an “ideal” automatic current shaper since the input current is not directly proportional to the input voltage for a constant duty ratio. In [28], variable switching frequency control must be employed to achieve high power which makes it challenging to optimize the design of the filter components and control loop. Principle of operation of the proposed converter and its analysis is described in Section II. Design procedure and simulation results are presented in Section III. Experimental results for a 115-W/240-Vdc and 115-W/400-Vdc are provided in Section IV followed by a conclusion in Section V.

Fig. 2. Topological stages for the converter of Fig. 1(a) during one switching period T s .

II. PRINCIPLE OF OPERATION AND ANALYSIS A. Principle of Operation The proposed converters of Fig. 1 are designed to operate in discontinuous-conduction mode (DCM) during the switch turn-on interval and in resonant mode during the switch turnoff intervals. As a result, the switch current stress is similar to the conventional DCM PFC converter, while the switch voltage stress is higher. Moreover, the two power switches Q1 and Q2 can be driven by the same control signal, which significantly simplifies the control circuitry. However, an isolated gate drive is required for the power switch Q1 . Referring to Fig. 1(a), the switching conduction sequences are as follows: 1) during positive ac-line cycle, Q1 −DQ 2 , D2 , D1 , X (all switches are off); and 2) during negative ac-line cycle, Q2 −DQ 1 , D1 , D2 , X. On the other hand, the switching conduction sequences for the converter of Fig. 1(b) are as follows: 1) during positive ac-line cycle, Q1 −DQ 2 , D1 , D2 , X; and 2) during negative ac-line cycle, Q2 −DQ 1 , D2 , D1 , X. Thus, during each switching period Ts , the current path goes through only two or one semiconductor devices instead of three. As a result, the total conduction losses of the semiconductor devices will be considerably lower compared to the conventional bridgeless PFC converters. Furthermore, to

Fig. 3. Topological theoretical waveforms for the converter of Fig. 1(a) during the positive half-line cycle.

avoid repetition, only the converter in Fig. 1(a) will be analyzed; however, a similar approach can be developed for the proposed converter in Fig. 1(b). Also, due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-period of the ac-input voltage. To simplify the analysis, it is assumed that the converter of Fig. 1(a) is operating under steady-state condition. In addition, the following assumptions are made: input voltage is pure sinusoidal, ideal lossless components, the switching frequency (fs ) is much higher than the ac line frequency (fL ), and the output capacitor Co is large enough such that the output voltage can be considered constant over the whole line period. Based on these assumptions, the circuit operations in one switching period Ts in a positive ac-line cycle can be divided into four distinct topological stages. The four equivalent circuits of each topological stage and the key waveforms during one switching period are shown in Figs. 2 and 3, respectively. Fig. 4 shows key waveforms of the proposed topology during the negative halfcycle over one switching cycle. It shall be noted that during the

FARDOUN et al.: BRIDGELESS RESONANT PSEUDOBOOST PFC RECTIFIER

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with the input voltage, while the voltage across capacitor C1 remains constant at voltage vx . The normalized circuit equations are given by iL 1,n (t) = mac ωr (t − t0 )

(6)

mC 1 (t) = − mx

(7)

iQ −pk ,n = mac α

(8)

where mx = vx /Vo and α is the normalized length of this stage and it is given by α = ωr (t1 − t0 ) = ωr d1 Ts

Fig. 4. Topological theoretical waveforms for the converter of Fig. 1(a) during the negative half-line cycle.

negative half-cycle the load is charged during the positive half of the resonant cycle. In addition, the capacitor voltage during the negative half-cycle is not symmetric to the positive half one. This is attributed to the fact that the capacitor voltage amplitude is the sum of the output and input line voltages during the negative half-cycle while it subtracts during the positive one. In order to perform the analysis and derive equations independent of any particular parameter, all equations derived in this paper are normalized using the following base quantities: Base voltage = Output voltage, Vo L1 Base impedance = Zo = C1 Vo Zo 1 ωr √ = Base frequency, fr = 2π 2π L1 C1 Base current =

(1) (2) (3) (4)

The normalized values of the input and output quantities are described as vac vC 1 , mC 1 = mac = Vo Vo iL 1,n =

iL 1 Zo , Vo

iQ −pk ,n =

iQ −pk Zo , Vo

RN =

RL (5) Zo

where vac is the input ac voltage, vC 1 is the voltage across the capacitor element C1 , iL 1 is the current through the inductor element L1 , iQ −pk is the peak switch Q1 , and RL is the load resistance. For a loss free converter, the output and the input power are equal. Based on the above definitions, a brief analysis of each topological stage, along with the important circuit equations is presented next. Stage 1[t0 , t1 ], [Fig. 2(a)]: This stage starts when the switch Q1 is turned-on. The body Diode of Q2 is forward biased by the inductor current iL 1 . Diode D1 is reverse biased by the voltage across C1 , while D2 is reverse biased by the voltages vC 1 + Vo . In this stage, the current through inductor L1 increases linearly

(9)

where d1 is the switch Q1 duty cycle. Stage 2[t1 , t2 ] [Fig. 2(b)]: This stage starts when switch Q1 is turned OFF and diode D2 is turned ON simultaneously providing a path for the inductor currents iL 1 . As a result, diode D1 remains reverse biased during this interval. The series tank consisting of L1 and C1 are excited by the input voltage vac through diode D2 as shown in Fig. 2(b). The stage ends when the resonant current iL 1 reaches zero and diode D2 turns OFF with zero current. During this stage, capacitor C1 is charged until it reaches a peak value as shown in Fig. 3. The normalized resonant iL 1 (t) and vC 1 (t) can be, respectively, described as iL 1,n (t) = A sin ωr (t − t1 ) + iQ −pk ,n cos ωr (t − t1 ) (10) mC 1 (t) = (mac − 1) + iQ −pk ,n sin ωr (t − t1 ) − A cos ωr (t − t1 )

(11)

where A = mac + mx −1. The normalized length of this stage can be calculated as following: 4 iQ −pk ,n −1 β = ωr (t2 − t1 ) = sin . (12) 4 + i2Q −pk ,n Stage 3[t2 , t3 ] [Fig. 2(c)]: during this stage diode D1 is forward biased to provide a path during the negative cycle of the resonating inductor current iL 1 . This stage ends when the inductor current reaches zero. Thus, during this stage diode D1 is switched ON and OFF under zero current conditions. Assuming the constant input voltage over a switching period, the capacitor is discharged until it reaches a voltage vx (see Fig. 3). The normalized resonant iL 1 (t) and vC 1 (t) can be, respectively, described as iL 1,n (t) = − (mac + mx ) sin ωr (t − t2 )

(13)

mC 1 (t) = mac + (mac + mx ) cos ωr (t − t2 ).

(14)

The normalized length of this stage can be calculated as following: γ = ωr (t3 − t2 ) = π.

(15)

Stage 4[t3 , t4 ] [Fig. 2(d)]: during this stage all switches are in their off-state. The inductor current is zero, while the capacitor voltage remains constant (vC 1 = vx ). It shall be noted that for this converter to operate as specified, the length of this stage must be greater than or equal to zero. Based on the analysis above, the complete normalized stateplane trajectory of the proposed converter could be constructed

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Fig. 6.

Fig. 5.

Normalized state-plane trajectories for the converter of Fig. 1(a).

in the (mC 1 , iL 1,n ) state plane. Fig. 5 shows the state-plane diagram in a switching period with (mC 1 , iL 1,n ) as state variables. Referring to Fig. 5, the direction of the arrows shows the variations of the normalized current and voltage during the switching period. The circled numbers reflect the stage number. The value of the normalized capacitor voltage mx can be found from Fig. 5 as mx =

i2Q −pk ,n − mac ≥ 0. 4

(16)

Large signal model of the proposed converter of Fig. 1(a).

line, which is the perfect condition for a unity power factor operation. In other words, similar to conventional DCM buck– boost (flyback converter), Cuk and Sepic PFC rectifiers (18) shows that the input port of the proposed rectifier obeys Ohm’s law. Thus, the input current is sinusoidal and in phase with the input voltage. Hence, the power stage circuit of the converter of Fig. 1(a) can be represented by its large signal averaged model shown in Fig. 6. This model can be implemented in a simulation program to predict the steady state and large signal dynamic characteristics of the real circuit. Furthermore, the averaged model can greatly reduce the long computation time when it is implemented in simulation software. C. Boundaries Between CCM and DCM

B. Voltage Conversion Ratio M The voltage conversion ratio M = Vo /Vm in terms of circuit parameters can be obtained by applying the input–output power balance principle to the circuit of Fig. 1(a). The average input power during one half-cycle (TL /2) of the ac-line voltage is T L /2 2 vac ¯i L 1 dt (17) Pin (t)T L /2 = TL 0 where ¯iL 1 is the average input current over one switching period Ts and it is given by ¯iL 1 = vac . (18) Re The variable Re represents the emulated input resistance of the converter and it is derived as 2L1 Re = 2 . (19) d1 T s Evaluating (17) and applying the power balance between the input–output ports, the desired voltage conversion ratio M can be derived as RL d1 Vo = =√ (20) M= Vm 2Re 2K where Vm is the peak of the input ac-line voltage, and the dimensionless conduction parameter K is defined by K=

2L1 . R L Ts

(21)

Note that (20) shows that the gain is directly proportional to the duty cycle. Thus, a controller design is relatively an easy task since only the output voltage must be regulated, while the internal current loop is completely eliminated. Moreover, for a given operating point (M, RL ), the emulated input resistance Re in (19) is constant when both d1 and Ts are kept constant. Thus, the converter presents a linear resistive load to the ac power

To ensure DCM operation, the length of the fourth stage must be greater than zero. Therefore, the following condition must be satisfied: 2π (22) α+β+γ ≤ F where F = fs /fr is the normalized switching frequency. The condition in (22) can be fulfilled if diodes D1 and D2 remains reverse biased during the fourth stage. Hence, the following condition must be also satisfied: 0 ≤ mD 1 ≤ 1

(23)

where mD 1 is the normalized voltage across diode D1 . Since the inductor voltage is zero during the fourth stage and the normalized capacitor voltage (mC 1 ) is equal to −mx , the normalized voltage across D1 can be expressed by the following bounds 0 ≤ mac + mx ≤ 1.

(24)

Substituting (16) into (24) gives 0 ≤ iQ −pk ,n ≤ 2.

(25)

From (8), the maximum value of the peak switch current occurs when vac = Vm , and it is given by α . (26) IQ −pk ,n = M Substituting (9), (20), and (26) into (25), the following condition for DCM is obtained: 2 1 F K≤ = Kcrit . (27) 2 π D. Components Stresses Table I shows the semiconductors normalized peak voltage and current stresses for the proposed converter of Fig. 1(a). Table I also shows the rms current stresses through each of the cir-


TABLE I NORMALIZED COMPONENT STRESSES FOR THE PROPOSED CONVERTER

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1) The voltage conversion ratio M is 240 Vo = 2. (28) =√ Vm 2 × 85 2) To ensure DCM operation, the value of the normalized switching frequency (F ) must be less than one. For this design, the value of F is chosen to be 0.8 3) From (21) and (27), determine the value of the critical inductance required to maintain DCM operation 2 R L Ts F = Lcrit = 163 μH. (29) L1 ≤ 4 π M=

In this design, the value of L1 is selected to be 100 μH. 4) Calculate the value of the resonant capacitance C1 form (4) 1 = 65 nF. (30) C1 = L1 (2πfr )2 5) From (20), calculate switch duty-cycle d1 √ d1 = M 2K = 0.4. TABLE II COMPARISON OF SEMICONDUCTORS VOLTAGE STRESSES

(31)

6) From (26), evaluate the maximum value of the peak switch current IQ −pk ,n ω r d1 T s α = = 1.57. (32) M M 7) Evaluate (9) and (12) and (15) and check if (22) is satisfied: 4jQ −pk 2π −1 = 7.84. ωr d1 Ts + sin + π = 7.61 ≤ 4 + jQ2 −pk F (33) If (22) is not satisfied, reiterate by changing the value of F and redo steps (1) to (7). IQ −pk ,n =

cuit elements. Voltages and currents are normalized with respect to the output voltage Vo and base current (Vo /Zo ), respectively. These equations are provided for design purposes. Table II compares the semiconductors voltage stress for the proposed converter as well as for the conventional boost and sepic converters. Table II shows that the switch in the proposed converter is subjected to higher voltage stress. However, the switch voltage stress becomes comparable to the SEPIC topology if the converter is designed for high value of (RN F). III. DESIGN PROCEDURE AND SIMULATION RESULTS A. Design Procedure In this section, a procedure for the converter design is presented for a given operating point. The highest values for α and β occur at the peak input voltage. Worst case values must be taken into account to ensure that (22) through (25) and (27) are satisfied. It shall be noted that due to the resonant nonlinear nature of the converter, an iterative design procedure is involved. The design procedure is presented for the following power stage specifications: vac = 85 Vrm s , Vo = 240 V, Pout = 115 W, and fs = 50 kHz. From the aforementioned data, and assuming that the efficiency is 100%, the values of the circuit components are calculated as follows:

B. Control Issues and Small-Signal Modeling Note that according to (20), load regulation can be achieved by either a simple variable duty-cycle fixed-frequency control or a fixed duty-cycle variable-frequency control. In the case of variable-frequency control, the variation in the switching frequency depends on the voltage gain M and output load RL . The range of the switching frequency variation can be found from (16), (22), and (27) and is given by ωr ≤ fs ≤ min · {f1 , f2 } (34) RN where M ωr fr 64 × b1 − b21 − f1 = , f2 = (35) RN 2 9 and b1 =

8 × 3

4M 2 +1 . 3πRN

(36)

For controller design purpose, a small-signal model of the converter is required. From (18), the peak value of the average input current ¯i L 1 is given by im =

vm d21 Ts . 2L1

(37)

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TABLE IV COMPONENTS USED IN SIMULATION PROTOTYPE

Fig. 7.

Small-signal equivalent circuit for the converter of Fig. 1(a). TABLE III SMALL-SIGNAL MODEL PARAMETERS

Considering 100% of efficiency, then from the large signal model of Fig. 6, the average of the output current over a one half-line period can be derived as T L /2 2 vac 2 v 2 d2 T s dt = m 1 . (38) io = TL 0 R e vo 4L1 vo To derive the small-signal model let the system operate in a steady state and consider a small-signal perturbations around the operating point: vm = Vm + vˆm , vo = Vo + vô , im = Im + îm , io = Io + îo , and d1 = D1 + dˆ1 , with Vm vˆm , Vo vô , Im îm , Io îo , and D1 dˆ1 . Substituting the perturbed variables into both (37) and (38) and neglecting the products of small-signal perturbations, a simple small-signal equivalent circuit is derived as shown in Fig. 7. The small-signal parameters are listed in Table III. The open-loop small-signal transfer functions of interest, i.e., duty ratio-to-output and lineto-output directly follow from Fig. 7 as j2 /Co vô (s) = (39) s + R L2C o dˆ1 (s) vˆ m =0

vô (s) g2 /Co = . vˆm (s) d=0 s + R L2C o ˆ

(40)

C. Simulation Results and Topology Comparison The converter of Fig. 1(a) has been simulated using PSPICE for the following input and output data specifications: vac = 85 Vrm s , Vo = 240 V, Pout = 115 W, and fs = 50 kHz. The design procedure of Section III-A has been followed to come up with the design components values. The values of the resonant tank have been rounded to the closet discrete off the shelf components. Moreover, an equivalent series resistor (ESR) of 30 mΩ is placed in series with all the inductors and capacitors. Furthermore, PSPICE actual semiconductor models have been used to simulate the switches. Table IV shows the details of the components used in the simulation for the above operating point. According to (20), the switch duty-cycle (d1 ) is set to 40%.

A small high-frequency input filter (LF = 1 mH, and CF = 1 μF) is inserted to filter the pulsating high frequency inductor L1 ripple current. Fig. 8 shows the simulated voltage and current waveforms under full load condition. It can be observed from Fig. 8(a) that the input line current (iac ) is in phase with the input voltage. Fig. 8(b) shows the unfiltered input current through tank inductor (iL 1 ) and tank capacitor voltage (vC 1 ) over the whole line period. It can be noted that the capacitor voltage during the negative half-line cycle is different from that during the positive half-cycle. The asymmetry of vC 1 is expected since the switching sequence during the positive ac-line cycle is different from the switching sequences during the negative ac-line cycle. Fig. 8(c) shows the tank inductor current and capacitor voltage waveforms over several switching cycles. Fig. 8(d) shows the switch Q1 voltage and current waveforms. It is clear from Fig. 8(d) that the switch Q1 turns ON under zero current condition. The diodes (D1 and D2 ) voltage and current waveforms are shown in Fig. 8(e) and (f), respectively. It is clear from Fig. 8(e) and (f) that both diodes D1 and D2 are turned OFF under zero current conditions. The performance of the converter is further investigated under the conditions of load current variations based on the average small-signal model in Fig. 7. Fig. 9 shows the Bode plot of the ) transfer open-loop control voltage-to-output voltage ( vˆvˆc tor(s) l (s) function of the system. This transfer function is given by dˆ1 (s) vô (s) vô (s) j2 /Co = × = Kp × ˆ vˆctrl (s) vˆctrl (s) d1 (s) s + R L2C o ˆ

(41)

= 1/Vpk = 1/15, where Vpk represents where Kp = vˆdc t1r(s) l (s) the peak value of the modulating signal used in PWM. Based on the open-loop transfer function of the system, a classical type-II compensation network is designed as shown in Fig. 10 with a bandwidth of 94 rad/s (15 Hz). The simulated transient responses of the output voltage and load current to a step load change from 100% to 0% and vice versa are shown in Fig. 11 for an input voltage of 85 Vrm s . It is clear from Fig. 11 that transient response to load step changes is slow because of the low bandwidth although dc regulation is good. As with any power factor corrector circuit (pre-regulator), the bandwidth of the voltage feedback loop compensator must be less than the


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Fig. 9.

Fig. 10.

Control-to-output frequency responses.

Type II compensator network.

Fig. 11. Simulated closed-loop transient response of the output voltage (top trace) and load current (bottom trace) when subjected to an output load change from 100W to 0W to 100W.

Fig. 8.

Simulated waveforms for the converter of Fig. 1(a).

input line frequency, typically in the range of 5 to 20 Hz [30]. If the voltage loop bandwidth were large, it would modulate the input current to keep the output voltage constant and this would distort the input current and result in a very poor power factor. There are numerous methods to improve the voltage-loop dynamic response of a PFC preregulator [31]–[38], but that is beyond the scope of this paper.

Fig. 12. voltage.

Converter efficiency, power factor, and THD as function of the input

Simulated efficiency, power factor, and percent of the total harmonic distortion (%THD) variations under different input voltages are shown in Fig. 12 for an output voltage of 400 V. The harmonic components in Fig. 12 are calculated up to 1.25 kHz (up to 25th order) via PSPICE simulation. The input power

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TABLE V COMPARISON OF EFFICIENCY AND POWER FACTOR AT LOW LINE (110 V R M S ) AND HIGH LINE (220 V R M S ) FOR A PFC RECTIFIER WITH DC OUTPUT VOLTAGE V o = 400 V AND OUTPUT POWER P o = 200 W IN DCM MODE

Fig. 13. Harmonics content of the input current as compared with EN610003-2 Class D limits at full load for two different line input voltages.

factor is calculated according to the following relation: PF =

Pin (t)T L . Vac,rm s Iac,rm s

(42)

Note that for pure sinusoidal input voltage excitation, the average input power Pin (t)T L only consists of the fundamental component multiplied by its displacement factor (Cos(θ1 )), where θ1 is the angle by which the fundamental component of iac (t) lags vac (t). In this case, (42) can be expressed as PF =

Iac,rm s(1) cos (θ1 ) Iac,rm s

(43)

where Iac,rm s (1) is the rms value of the fundamental component of the input current iac (t). The line current distortion is quantified by the THDi parameter, which is defined as

∞ 2 2 2 Iac,rm s − Iac,rm s(1) n =2 Iac,rm s(n ) THDi = = (44) Iac,rm s(1) Iac,rm s(1) where Iac,rm s(n) is the rms value of the nth harmonic component of the line current iac (t). Using (43) and (44), the relationship between PF and THDi can be determined as follows: 2 cos (θ1 ) − 1. (45) THDi = PF Referring to Fig. 12, the efficiency peaks (96.9%) at about 120 Vrm s input voltage and tapers down in both low and high voltages. Unlike the boost PFC converter, the proposed converter suffers from high voltage stress on some components (the power switches and the capacitor C1 ) at high line; this high voltage stress increases the switching losses which offset the lower conduction losses due to current reduction. At low line, the current drawn from the main is high; however, the voltage stress on the power switches and capacitor C1 is reduced. In other words, the overall components losses (switching and conducting) at high-line and low-line voltage balance out. Therefore, the slight increase in efficiency at low line is mainly due to improved power factor. Nevertheless, it is evident from Fig. 12 that high PF and high efficiency (>95.5%) can be maintained under universal input voltage operation. Fig. 13 presents the simulated harmonic content of the input line current at nominal high (220 Vrm s ) and nominal low line (110 Vrm s ) inputs together with the limits of EN61000-3-2 Class

D standard. Note that, for better visibility of the higher order harmonics, class D limits are scaled down by a factor of 8 (class D limits/8). It is evident from Fig. 13 that the calculated results are well below the allowable limits of Class D standard. An efficiency comparison between the conventional PFC boost and the conventional PFC SEPIC converters is performed via simulation. In this comparison, all the three converters are assumed to operate in DCM with the same operating conditions and parameters. Therefore, to ensure a fair comparison, the inductance values in all topologies are selected such that Ke = 0.8 Kcrit at an operating point of an output voltage and power of 400 V and 200 W, respectively. The simulated efficiency presented in Table V includes conduction and switching losses of the semiconductor devices, inductors’ copper losses, capacitors’ ESR losses, as well as gate drive losses. PSPICE actual semiconductor models have been used to simulate the diodes in the circuit: STTH5L06 for the conventional boost and the proposed converter and diode model UF3007 for the conventional SEPIC converter. For the power switches, an ideal switch with Ron = 160 mΩ has been utilized in the simulation for all the topologies. Moreover, an equivalent series resistor (ESR) of 20 mΩ is placed in series with all the inductors and capacitors. Referring to Table V, it is clear from the simulated results that the proposed topology provides lower THD and higher PF than the conventional boost and it provides similar conversion efficiency at nominal low line. Compared to the conventional SEPIC converter, the proposed topology provides better conversion efficiency at both nominal low line and nominal high line with comparable values of THD and PF. IV. EXPERIMENTAL RESULTS The performance of the proposed converter of Fig. 1(a) has been verified by a laboratory prototype for the same operating point as the simulation at an input voltage of 85 Vrm s and using the same components of Table IV. In this prototype circuit, a DC4-100 toroidal core (100 μH, RDC = 25 mΩ, and core volume Ve = 36.2 cm3 ) from Wilco company is used for the inductor L1 . The prototype was constructed and tested under an open-loop condition at constant switching frequency and duty


Fig. 14.

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Complete circuit diagram of the developed prototype.

cycle. The circuit diagram of the complete prototype including the gate driver circuit is depicted in Fig. 14. The experimental waveforms of the converter at full load are depicted in Fig. 15. The output voltage, the input voltage, and the filtered line current (iac ) waveforms are shown in Fig. 15(a). Fig. 15(b) depicts the unfiltered line current (iL 1 ) and the voltage across the capacitor C1 . The waveforms of iL 1 and vC 1 during a few switching periods at peak input voltage are depicted in Fig. 15(c), which correctly demonstrates the operating mode and matches the simulated results. Fig. 15(d) shows the switch Q1 voltage and current waveforms. It is evident from Fig. 15(b) that the switch Q1 turns-on under zero current condition. The diodes (D1 and D2 ) voltage and current waveforms are shown in Fig. 15(e) and (f), respectively. It is evident from Fig. 15(e) and (f) that both diodes D1 and D2 are turned OFF under zero current conditions. Note that the high frequency ringing in the Q1 current at turn-off and in the diode D2 current at turn-on appears as a consequence of resonances between converter inductances and device parasitic capacitances. Nevertheless, the experimental waveforms are in good agreement with the simulation waveforms shown in Fig. 8. Fig. 16 shows the measured and calculated PF and harmonic content of the line current together with the limits of EN610003-2 Class D standard. It is evident from Fig. 16 that that the proposed converter is capable of complying with the stringent Class D limits of EN61000-3-2 standard. It is also clear from Fig. 16 that the harmonic currents are well below the limits specified in class D standard. The measured%THD in filtered input current is about 5.8% with a power factor of 0.9983 and conversion efficiency of 94.3%. The proposed converter of Fig. 1(a) has been also tested under universal input line conditions. For the test, the output voltage is set to 400 V, and all circuit parameters have been kept the same as described in Table IV except for the active switches (switch type IXFN36N100 is used) and the tank capacitor C1 which is replaced by a 15 nF. Figs. 17 and 18 show the measured input voltage and the input current at nominal low line (110 Vrm s ) and nominal high line (220 Vrm s ), respectively. The measured efficiencies at the nominal low line (110 Vrm s ) and nominal

Fig. 15. Measured waveforms for the converter of Fig. 1(a). (v a c = 85 V rm s , V o = 240 V, P o = 115W).

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Fig. 16. Measured harmonic content of the input line current together with the calculated results and the limits of EN61000-3-2 Class D standard. Fig. 20. Measured harmonic content of the input line current for the converter of Fig. 1(a). (v a c = 220 V rm s , V o = 400 V, P o = 115 W).



nominal low line (110 Vrm s ) and nominal high line (220 Vrm s ), respectively. Note that (18) predicts that the average input current is proportional to the input voltage vac . Therefore, the PF and the THD should be same at the low line and high line, i.e., independent of the voltage gain M . On the other hand, Figs. 19 and 20 show that the PF and THD are lower at low line than that at high line. The reason for this difference can be attributed to the input low-pass filter. In the experimental prototype, an L − C low-pass filter was utilized to absorb the high-frequency component of inductor current iL 1 . This study did not focus on the performance of the input filter since the proposed converter is capable of producing a low harmonic distortion in line current that is well below the limits specified in EN61000-3-2 Class D requirements over the entire full range of line voltage and load. It should also been mentioned that the experimental curves are obtained in the absence of any snubber circuits and without any special circuit layout. Also, it is important to mention here that the experimental prototype has been conceived on a proofof-concept basis; therefore, the components have been chosen based on their off-the-shelf availability rather than optimizing the performance of the converter. For this reason, it is expected that higher efficiency can be achieved for the proposed scheme. V. CONCLUSION

Fig. 19. Measured harmonic content of the input line current for the converter of Fig. 1(a). (v a c = 110 V rm s , V o = 400 V, P o = 115 W).

high line (220 Vrm s ) operating points at a load of 115 W are 95.6% and 95.2%, respectively. As predicted, the efficiency difference between the nominal low line and nominal high line is less than 1%. Figs. 19 and 20 show the measured and calculated power factor and harmonic content of the input line current at

A new ac–dc converter with low component count and its topology derivation have been presented. The components of the proposed topology are fully utilized over the whole line cycle. The two power switches in the proposed topology can be driven by the same control signal, which significantly simplifies the control circuitry. Analysis, component stresses, design constraints, and simulation results of the converter have been presented. State-plane diagram has been constructed which has been successfully used to analyze the proposed converter. Both large-signal and small-signal averaged circuit models of the proposed converter are derived and presented. Experimental results obtained on a 115-W, 400 V output, and universal input prototype are provided. The input current harmonics meet the EN61000-3-2 Class D requirements with a large margin and maintaining efficiency at full load higher than 95% during the entire line voltage range. Although the discontinuous input current for the proposed converter may


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Abbas A. Fardoun (M’90–SM’05) was born in Lebanon. He received the B.S. degree from the University of Houston, Houston, TX, USA, in 1988, and the M.S. and Ph.D. degrees from the University of Colorado, Boulder, CO, USA, in 1990 and 1994, respectively. He was with Advanced Energy Inc. from 1994– 1996, where he was involved with high-frequency power supply design. From 1996 until 1998, he was with Delphi where he worked on Electrical Power Steering. From 1998 until 2006, he has been with TRW Automotive working on electrical power steering development for column and rack drives. Since 2006, he has been with the Department of Electrical Engineering at the United Arab Emirates University (UAEU) where he is an Associate Professor. He holds seven awarded patents related to ac drives and automotive applications. His main research interests include ac drives, ac—dc, and dc–dc power supplies for renewable energy applications. Dr. Fardoun received the Hariri Foundation distinguished graduate award in 1994.

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Esam H. Ismail (M’93–SM’08) was born in Kuwait. He received the B.S. (with magna cum laude honors) and M.S. degrees from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively, and the Ph.D. degree from the University of Colorado, Boulder, CO, USA, in 1993, all in electrical engineering. During the period 1985–1988, he joined the College of Technological Studies in Kuwait as a Lecturer, where he is currently a Full Professor in the Department of Electrical Engineering. His research interests include single-phase and three-phase low harmonic rectification, high-frequency power conversion, soft switching techniques, and the development of new converter topologies. His recent research interest has been directed on developing new power converter circuits for renewable energy systems (Wind, Solar, and Fuel Cells) and their integration to the ac utility grid. Dr. He served as an Assistant Deputy Director General for Applied Education and Research at the Public Authority for Applied Education and Training (PAAET), Kuwait, from 2000 to 2005. In 2011, he was appointed as a Director of the Quality Assurance and Academic Accreditation Office at PAAET. Dr. Ismail is a Member of Tau Beta Pi (The Engineering Honor Society).

Mustafa A. Al-Saffar (M’08) received the B.S. and M.S. degrees in electrical engineering from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively,and the Ph.D. degree from the University of Wisconsin-Madison, Wisconsin, USA., in 1997. He joined the Department of Electrical Engineering, College of Technological Studies in Kuwait, in 1985, where he is currently an Associate Professor. His research interests include the fields of advanced control techniques, high-power-factor rectifiers, and electric drive systems. Ahmad J. Sabzali (M’85) received the M.Sc. degree in electrical engineering from North Carolina A&T State University, NC, USA, in 1986, and the Ph.D. degree in electrical engineering from Bristol University, Bristol, U.K., in 1996. In 1983, he joined the Department of Electrical Engineering, the College of Technological Studies, Kuwait, where he is currently an Associate Professor of electrical engineering. His research interests include resonant converters, dc–dc converters, electric machine drives, and control.