A Buck-Boost Converter Modified to Utilize 600V GaN ...

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Advances in Electrical and Computer Engineering

Volume 15, Number 3, 2015

A Buck-Boost Converter Modified to Utilize 600V GaN Power Devices in a PV Application Requiring 1200V Devices Srdjan SRDIC1, Zeljko DESPOTOVIC2 University of Belgrade - School of Electrical Engineering, 11120, Serbia 2 University of Belgrade - Institute "Mihailo Pupin", 11060, Serbia [email protected], [email protected]

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[4-9]. The all-GaN converters developed specifically for the PV applications have also been successfully demonstrated in [10-12]. In all the presented applications, a superior performance of the GaN-based devices over Si-based devices is demonstrated. II. A MODIFIED BUCK-BOOST CONVERTER TOPOLOGY

Many transformerless PV inverter topologies can be found in the literature [13-23], and all the proposed inverters have to meet several demands defined by the grid, by the PV module, and by the operator (owner). These demands include: low cost, high operating efficiency, low level of dc current injected into supply grid, ability of islanding detection, minimization of the capacitive leakage current, decoupling of PV panels from the grid, etc. Due to its good properties, a 3-level neutral-point-clamped (NPC) singlephase inverter seemed to fulfill the most demands, and is chosen for the particular application. The 3-level NPC inverter requires bipolar input voltage, which can be realized with a boost and a buck-boost converter, as shown in Fig. 1. The boost converter provides a positive voltage to the NPC inverter, while the buck-boost converter provides a negative voltage to the NPC inverter. Both converters exhibit low power losses and both transfer power only during the one half-cycle of the grid voltage (the boost converter transfers power during the positive half-cycle, and the buck-boost converter transfers power during the negative half-cycle of the grid voltage) A similar converter can be derived in the case when the positive terminal of the PV string is grounded. However, the topology from Fig. 1 has one significant disadvantage if new GaN components are to be used. Namely, during the conduction of the diode D 2 , the transistor T 2 needs to block the sum of the PV string voltage V pv (which is normally in the range from 150 to 350 V) and the dc bus voltage V dc (which is in the order of 400 V). Additionally, when the transistor T 2 conducts, the diode D 2 needs to block the sum of the PV string voltage and the dc bus voltage. Therefore, the devices rated over 600 V are required for the buck-boost converter. In order to overcome this disadvantage, a modification of the buck-boost converter is introduced. An additional transistor T 3 and a clamping diode D 2 are introduced into the circuit, as shown in Fig. 2. A series connection of diodes D 3 and D 4 provide required blocking voltage of Vpv + Vdc. Note that no modifications of the boost converter with 600 V devices are

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Abstract—This paper presents a buck-boost converter which is modified to utilize new 600 V gallium nitride (GaN) power semiconductor devices in an application requiring 1200 V devices. The presented buck-boost converter is used as a part of a dc/dc stage in an all-GaN photovoltaic (PV) inverter and it provides a negative voltage for the 3-level neutral-pointclamped (NPC) PWM inverter which is connected to the utility grid. Since in this application the transistor and the diode of the buck-boost converter need to block the sum of the PV string voltage (which is normally in the range from 150 to 350 V) and the dc bus voltage (which is in the order of 400 V), the 1200 V devices or series connection of 600 V devices need to be employed. Currently, 1200 V GaN power semiconductor devices are not commercially available. Therefore, the standard buck-boost converter is modified to enable the use of 600 V GaN devices in this particular application. Based on the proposed converter topology, a PSpice simulation model and a 600 W converter prototype were developed. Both simulation and experimental results show successful operation of the converter. Index Terms—buck-boost converter, converter topology, dcdc power converters, GaN semiconductor devices, PV inverter.

I. INTRODUCTION

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Over the past 30 years, developments in power electronics are mainly driven by continuous needs to reduce device size (i.e. to increase power density) and to increase device efficiency. However, a trade-off between the power density and the efficiency exist and the efficiency has often been sacrificed for the sake of power density. In order to improve this trade-off, the components with lower power losses at higher switching frequencies are needed. Due to their high current/voltage capabilities and fast switching speeds, the power devices based on the SiliconCarbide (SiC) and the Gallium-Nitride (GaN) are the most promising semiconductor devices for achieving higher efficiency in high-power-density devices [1-2]. Since the breakdown voltage of GaN devices is currently limited to about 1000 V (by existing epitaxial growth technology), these devices are most suitable for applications with operating voltages below 1000 V [3]. On the other hand, SiC devices are expected to cover the higher voltage applications, due to the availability of good quality bulk substrates and better thermal properties of the SiC [2]. Currently, 1700 V SiC devices and 600 V GaN devices are commercially available from several manufacturers. The all-GaN high efficiency dc/dc converters and dc/ac inverters have already been successfully demonstrated in

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Advances in Electrical and Computer Engineering necessary for its proper operation in this particular application.

Volume 15, Number 3, 2015 is important to note that diode D 2 in the modified topology exhibits virtually no power losses, as will be shown by simulation. III. SIMULATION OF THE MODIFIED BUCK-BOOST TOPOLOGY

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The proposed modified buck-boost converter with GaN transistors and diodes has been modeled and its operation has been simulated in OrCAD PSpice. The schematic of the simulated converter is shown in Fig. 3. The converter input voltage was set to V pv = 350 V and the duty cycle was set to D = 0.533. Therefore, the dc bus voltage was around 400 V. The other values for V pv and D could have been chosen as well. The operating frequency was set to f sw = 60 kHz. The large electrolytic capacitor C 2 serves as a dc bus capacitor and the resistor R 6 simulates a load. Power inductor L 5 of 680 H enables continuous conduction mode at low loads. Inductors L 1 –L 4 simulate parasitic inductances of the PCB traces, which contribute to the voltage spikes across the transistors during the transistor turn-off transient. These voltage spikes may significantly increase the transistors' drain-source voltage thus increasing the blocking voltage requirements of the transistors. Low resistances of the resistors R 1 – R 4 simulate the low equivalent resistance of the output stage of the integrated driver circuit. The 100 ms of the converter operation was simulated in order to ensure that the steady state was reached. Since a maximum simulation step was set to 50 ns, only the last 2 ms of the operation were saved in order to avoid large amount of recorded data. The simulated drain-source voltages across T 2 and T 3 (V DS2 and V DS3 , respectively) are shown in Fig. 4. As shown in Fig. 4, the transistors share the blocking voltage as expected (T 3 blocks the input PV voltage, while T 2 blocks the dc bus voltage). The inverse voltage across diode D 2 (V D2inv ), the power dissipation in the diode D 2 (P D2 ), and the inverse voltage across the series connection of the diodes D 3 and D 4 (V D3D4inv ), are shown in Fig. 5. As shown in Fig. 5, the power dissipation in the diode D 2 is essentially zero. The voltage spikes visible in the waveform of the diode D 2 inverse voltage are a result of the introduced parasitic inductances and can be significant if the parasitic inductances are not kept low by the proper PCB layout. In order to increase the readability of Figs. 4 and 5, the waveforms were plotted in MATLAB, by using data which are transferred from the PSpice as comma-separated values.

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Figure 1. The initial topology of the PV inverter.

Figure 2. The topology with the modified buck-boost converter.

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In the modified buck-boost converter, the transistors T 2 and T 3 are turned on at the same time. When off, transistors block the voltage equal to the sum of the PV string voltage and the dc bus voltage (transistor T 2 blocks the voltage of the negative dc bus, while the T 3 blocks the input PV voltage). Therefore, the topology from Fig. 2 enables the use of the 600 V GaN devices which are available on the market. In order to achieve the expected voltage sharing, the T 3 needs to be turned off slightly before the T 2 (in our case, the T 3 was turned off approximately 66 ns before the T 2 ). It

Figure 3. The schematic of the simulated converter.

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V DS2 [V]

400 300 200 100 0 99.04 99.045 99.05 99.055 99.06 99.065 99.07 99.075 99.08 99.085 99.09 Time [ms]

VDS3 [V]

400 300 200 100 0 99.04 99.045 99.05 99.055 99.06 99.065 99.07 99.075 99.08 99.085 99.09 Time [ms]

Volume 15, Number 3, 2015 testing of the converter, a capacitor of 4700 F (not shown in Fig. 6) was connected in parallel to the load and to the 22 F polypropylene capacitor shown in Fig. 6 (soldered to blue wires connected to the smaller multimeter). This large capacitor represents the dc bus capacitor. The transistors were driven by the signals from the TMS320F28027 experimenter kit DSP control card, which are passed by the fast optocouplers to the driver circuits on the dc/dc converter board. The driver circuits for both transistors are identical and were supplied by the isolated power supplies in order to enable floating operation of the transistors. The simple code for the DSP was generated in Simulink, by using blocks from the fixed-point library "C28x IQmath".

550 VD2inv [V]

450 350 250 150 50 -50 99.04 99.045 99.05 99.055 99.06 99.065 99.07 99.075 99.08 99.085 99.09 Time [ms]

Figure 6. A part of the laboratory setup. The bulky three-phase transformers are not shown.

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P D2 [W]

0.03

0.01

0 99.04 99.045 99.05 99.055 99.06 99.065 99.07 99.075 99.08 99.085 99.09 Time [ms]

500 300 100

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VD3D4inv [V]

900 700

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Figure 4. Simulated drain-source voltages across T 2 and T 3 (V DS2 and V DS3 , respectively).

99.04 99.045 99.05 99.055 99.06 99.065 99.07 99.075 99.08 99.085 99.09 Time [ms]

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Figure 5. Simulated diode D 2 inverse voltage (V D2inv ), power dissipation in the diode D 2 (P D2 ) and the inverse voltage across the series connection of the diodes D 3 and D 4 (V D3D4inv ).

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IV. EXPERIMENTAL EVALUATION OF THE MODIFIED BUCKBOOST TOPOLOGY The operation of the modified topology was experimentally evaluated on a laboratory prototype of a dc/dc stage of a PV inverter with GaN transistors and diodes. For the initial testing purposes, the dc/dc stage of a PV inverter was developed as a separate converter which consists of a buck converter and a modified buck-boost converter presented in this paper. A part of the laboratory setup is shown in Fig. 6. The converter was supplied from the simple rectifier consisting of a three phase diode bridge and a large electrolytic capacitor. The rectifier was supplied from the secondary of the 4-kVA three-phase transformer connected to the output of a three-phase variable autotransformer. The primary of the variable autotransformer was connected to a 380-V, 50-Hz threephase network. Four 200-W light bulbs, connected as 2 parallel branches of 2 bulbs in series, make a 660-W load at dc bus voltage of 400 V. It should be noted that during the

The operation of the converter was verified at several input voltages and duty cycles, while the output voltage was kept at 400 V. The switching frequency was set to 60 kHz. Both transistors were turned on at the same time, and the T 3 was turned off by the DSP approximately 66 ns before the T 2 (more precisely, the turn-off command from the DSP was given 66 ns earlier). Although the diodes D 3 and D 4 were not matched, there was no need for voltage sharing capacitors across the diodes since the diode voltage rating (600 V) is significantly higher than the required diode blocking voltage (around 400 V). The voltage sharing between the transistors is illustrated in Figs. 7–10. In the case of Figs. 7 and 8, the input voltage was set to 171 V and the duty cycle was set to 0.7. In the case of Figs. 9 and 10, the input voltage was set to 350 V and the duty cycle was set to 0.533. In both cases, the average output voltage was around 400 V. As seen in Figs. 7 and 9, the voltage sharing between the transistors is acceptable, although transistor T 2 takes more voltage than anticipated by the simulations. The large voltage spikes across the T 3 are a result of the non-optimal PCB layout design (i.e. significant parasitic inductances of the long T 3 drain trace). As seen in Figs. 8 and 10, the T 3 turns off about 100 ns before the T 2 . The diode D 2 inverse voltage and the transistor T 3 V DS voltage are shown in Figs. 11 and 12. The ringing visible in the voltage waveforms is a result of the introduced parasitic inductances of the long PCB traces. During the testing procedure we have learned that the extra care should be taken when designing the converter PCB layout in order to fully utilize the potential of the high-speed components. Namely, the traces between the transistors and diodes should be as short as possible and the gate-source circuit loop should be minimized as much as possible. The similar conclusions are reported in [6] and [24].

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Figure 10. The waveforms from Fig. 9 zoomed-in around the transistors' turn-off transient: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T3.

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Figure 7. The experimental results for V in = 171 V and D = 0.7: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T 3 .


Figure 11. The experimental results for V in = 171 V and D = 0.7: (cyan) diode D 2 inverse voltage, and (orange) V DS voltage of T 3 .

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Figure 8. The waveforms from Fig. 7 zoomed-in around the transistors' turn-off transient: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T3.

Figure 9. The experimental results for V in = 350 V and D = 0.533: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T 3 .

Figure 12. The experimental results for V in = 350 V and D = 0.533: (cyan) diode D 2 inverse voltage, and (orange) V DS voltage of T 3 .

The influence of the long traces between the power components (i.e. large "power loop") to the generated voltage spikes across a transistor during the transistor turnoff transient is illustrated in Figs. 13 and 14. Figure 13 shows the T 3 V DS voltage before the long T 3 drain trace has been shortened. Figure 14 shows the same voltage after the T 3 drain-source trace has been shortened. As seen in Fig. 14, by shortening the T 3 drain trace, the voltage spikes in T 3

V DS voltage is reduced by around 50 V. The response could be even further improved by additionally reducing the power loop in the transistor T 3 circuit. It should be noted that in this case a two-layer PCB was used. For better performance, a four layer PCB with the inner layer close to the power loop should be considered, as suggested in [24]. The inner-layer-as-a-return-path approach could be used to reduce the gate-source loop inductance, as suggested in [6].

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Figure 16. The experimental results for V in = 100 V and D = 0.7, after the long T 3 drain trace has been shortened: (cyan) inverse voltage of D 2 , and (orange) V DS voltage of T 3 .

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Figure 13. The experimental results for V in = 150 V and D = 0.7, before the long T 3 drain trace has been shortened: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T 3 .


As can be seen in Figs. 15 and 16, after shortening the T 3 drain trace, both the duration and the amplitude of the ringing in the D 2 inverse voltage were reduced. V. CONCLUSION

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The modified buck-boost converter topology, which is used as a part of a dc/dc stage in an all-GaN grid-connected photovoltaic inverter, has been presented in this paper. Currently commercially available GaN power devices have maximum breakdown voltage of 600 V, although the breakdown voltage of GaN power devices is limited to about 1000 V by existing epitaxial growth technology. The proposed modified buck-boost converter enables the use of 600-V GaN devices in an application in which the standard buck-boost converter would require 1200-V devices. The successful operation of the proposed converter was demonstrated by simulations and verified by experiments. However, the experimental results have shown that the voltage sharing between the transistors is not as ideal as in the simulations and that one of the transistors takes more voltage than anticipated by the simulations. The tests have also shown that the extra care should be taken when designing the converter's PCB layout, in order to avoid the unwanted voltage spikes and excessive ringing in the transistors' and diodes' voltage waveforms. Namely, power traces should be kept short and the gate-source loop should be minimized as much as possible.

Figure 14. The experimental results for V in = 150 V and D = 0.7, after the long T 3 drain trace has been shortened: (cyan) V DS voltage of T 2 , and (orange) V DS voltage of T 3 .

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The influence of the power loop parasitic inductances on the diode D 2 inverse voltage is illustrated in Figs. 15 and 16. Figure 15 shows the D 2 inverse voltage before the T 3 drain trace has been shortened and Fig. 16 shows the D 2 inverse voltage after the T 3 drain trace has been shortened.

REFERENCES [1]

[2]

[3]

Figure 15. The experimental results for V in = 100 V and D = 0.7, before the long T 3 drain trace has been shortened: (cyan) inverse voltage of D 2 , and (orange) V DS voltage of T 3 .

[4]

M. Ishida, Y. Uemoto, T. Ueda, T. Tanaka, D. Ueda, "GaN power switching devices," 2010 International Power Electronics Conference (IPEC), pp. 1014–1017, 21–24 June 2010. [Online]. Available: http://dx.doi.org/10.1109/IPEC.2010.5542030. J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas, J. Rebollo, "A Survey of Wide Bandgap Power Semiconductor Devices," IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2155–2163, May 2014. [Online]. Available: http://dx.doi.org/10.1109/TPEL.2013. 2268900. T. Ueda, "Recent advances and future prospects on GaN-based power devices," 2014 International Power Electronics Conference (IPECHiroshima 2014 - ECCE-ASIA), pp. 2075–2078, 18–21 May 2014. [Online]. Available: http://dx.doi.org/10.1109/IPEC.2014.6869874. T. Morita, S. Tamura, Y. Anda, M. Ishida, Y. Uemoto, T. Ueda, T. Tanaka, D. Ueda, "99.3% Efficiency of three-phase inverter for motor drive using GaN-based Gate Injection Transistors," 2011 TwentySixth Annual IEEE Applied Power Electronics Conference and

63



[9]

[10]

[11]

[12]

[13]

Pr

[14]

64

[16]

[17]

[18]

[19]

rs io n

[8]

[15]

Transactions on Power Electronics, vol. 22, no. 5, pp. 1928–1940, Sep. 2007. [Online]. Available: http://dx.doi.org/10.1109/TPEL. 2007.904202. R. Gonzalez, J. Lopez, P. Sanchis, L. Marroyo, "Transformerless inverter for single-phase photovoltaic systems," IEEE Transactions on Power Electronics, vol. 22, no. 2, pp. 693–697, Mar. 2007. [Online]. Available: http://dx.doi.org/10.1109/TPEL.2007.892120. T. Kerekes, R. Teodorescu, U. Borup, "Transformerless Photovoltaic Inverters Connected to the Grid," Twenty Second Annual IEEE Applied Power Electronics Conference (APEC 2007), pp. 1733–1737, Feb. 25–Mar. 1, 2007. [Online]. Available: http://dx.doi.org/10.1109/ APEX.2007.357753. F. Schimpf, L. E. Norum, “Grid connected converters for photovoltaic, state of the art, ideas for improvement of transformerless inverters”, Nordic Workshop on Power and Industrial Electronics (NORPIE/2008), June 9-11, 2008. T. Kerekes, M. Liserre, R. Teodorescu, C. Klumpner, M. Sumner, "Evaluation of three-phase transformerless photovoltaic inverter topologies," IEEE Transactions on Power Electronics, vol. 24, no. 9, pp. 2202–2211, Sep. 2009. [Online]. Available: http://dx.doi.org/ 10.1109/TPEL.2009.2020800. S. V. Araujo, P. Zacharias, R. Mallwitz, "Highly efficient singlephase transformerless inverters for grid-connected photovoltaic systems," IEEE Transactions on Industrial Electronics, vol. 57, no. 9, pp. 3118–3128, Sep. 2010. [Online]. Available: http://dx.doi.org/ 10.1109/TIE.2009.2037654. Wensong Yu, Jih-Sheng Lai, Hao Qian, C. Hutchens, "Highefficiency MOSFET inverter with H6-type configuration for photovoltaic nonisolated AC-module applications," IEEE Transactions on Power Electronics, vol. 26, no. 4, pp. 1253–1260, Apr. 2011. [Online]. Available: http://dx.doi.org/10.1109/TPEL. 2010.2071402. T. Kerekes, R. Teodorescu, P. Rodriguez, G. Vazquez, E. Aldabas, "A new high-efficiency single-phase transformerless PV inverter topology," IEEE Transactions on Industrial Electronics, vol. 58, no. 1, pp. 184–191, Jan. 2011. [Online]. Available: http://dx.doi.org/ 10.1109/TIE.2009.2024092. Li Zhang, Kai Sun, Lanlan Feng, Hongfei Wu, Yan Xing, "A family of neutral point clamped full-bridge topologies for transformerless photovoltaic grid-tied inverters," IEEE Transactions on Power Electronics, vol. 28, no. 2, pp. 730–739, Feb. 2013. [Online]. Available: http://dx.doi.org/10.1109/TPEL.2012.2205406. T. K. S. Freddy, N. A. Rahim, Wooi-Ping Hew, Hang Seng Che, "Comparison and analysis of single-phase transformerless gridconnected PV inverters," IEEE Transactions on Power Electronics, vol. 29, no. 10, pp. 5358–5369, Oct. 2014. [Online]. Available: http://dx.doi.org/10.1109/TPEL.2013.2294953. D. Reusch, J. Strydom, "Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter," Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 649–655, 17–21 Mar. 2013. [Online]. Available: http://dx.doi.org/10.1109/TPEL. 2013.2266103.

[20]

[21]

ve

[7]

ie w

[6]

ev

[5]

Exposition (APEC) , pp. 481–484, 6–11 Mar. 2011. [Online]. Available: http://dx.doi.org/10.1109/APEC.2011.5744640. Weimin Zhang, Zhuxian Xu, Zheyu Zhang, F. Wang, L. M. Tolbert, B. J. Blalock, "Evaluation of 600 V cascode GaN HEMT in device characterization and all-GaN-based LLC resonant converter," 2013 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 3571–3578, 15–19 Sep. 2013. [Online]. Available: http://dx.doi. org/10.1109/ECCE.2013.6647171. A. Tuysuz, R. Bosshard, J. W. Kolar, "Performance comparison of a GaN GIT and a Si IGBT for high-speed drive applications," 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 ECCE-ASIA), pp.1904–1911, 18–21 May 2014. [Online]. Available: http://dx.doi.org/10.1109/IPEC.2014.6869845. B. Hughes, J. Lazar, S. Hulsey, M. Musni, D. Zehnder, A. Garrido, R. Khanna, R. Chu, S. Khalil, K. Boutros, "Normally-off GaN-on-Si multi-chip module boost converter with 96% efficiency and low gate and drain overshoot," 2014 Twenty-Ninth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 484–487, 16–20 Mar. 2014. [Online]. Available: http://dx.doi.org/10.1109/ APEC.2014.6803352. K. Shirabe, M. M. Swamy, Jun-Koo Kang, M. Hisatsune, Wu Yifeng, D. Kebort, J. Honea, "Efficiency Comparison Between Si-IGBTBased Drive and GaN-Based Drive," IEEE Transactions on Industry Applications, vol. 50, no. 1, pp. 566–572, Jan. –Feb. 2014. [Online]. Available: http://dx.doi.org/10.1109/TIA.2013.2290812. M. D. Seeman, S. R. Bahl, D. I. Anderson, G. A. Shah, "Advantages of GaN in a high-voltage resonant LLC converter," Twenty-Ninth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 476–483, 16–20 Mar. 2014. [Online]. Available: http://dx.doi.org/10.1109/APEC.2014.6803351. M. Acanski, J. Popovic-Gerber, J. A. Ferreira, "Comparison of Si and GaN power devices used in PV module integrated converters," 2011 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1217–1223, 17–22 Sep. 2011. [Online]. Available: http://dx.doi.org/10.1109/ECCE.2011.6063915. A. Hensel, C. Wilhelm, D. Kranzer, "Application of a new 600 V GaN transistor in power electronics for PV systems," 2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC), pp. DS3d.4-1–DS3d.4-5, 4–6 Sep. 2012. [Online]. Available: http://dx.doi.org/10.1109/EPEPEMC.2012.6397350. L. Garcia-Rodriguez, V. Jones, J. C. Balda, E. Lindstrom, A. Oliva, J. Gonzalez-Llorente, "Design of a GaN-based microinverter for photovoltaic systems," 2014 IEEE 5th International Symposium on Power Electronics for Distributed Generation Systems (PEDG), pp.1– 6, 24–27 June 2014. [Online]. Available: http://dx.doi.org/10.1109/ PEDG.2014.6878639. S. B. Kjaer, J. K. Pedersen, F. Blaabjerg, "A review of single-phase grid-connected inverters for photovoltaic modules," IEEE Transactions on Industry Applications, vol. 41, no. 5, pp. 1292–1306, Sep.–Oct. 2005. [Online]. Available: http://dx.doi.org/10.1109/TIA. 2005.853371. S. Jain, V. Agarwal, "A single-stage grid connected inverter topology for solar PV systems with maximum power point tracking," IEEE


[22]

[23]

[24]