A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions Ahmed Elkammar Department of EE The Graduate Center and The City College of CUNY New York, NY 10031
[email protected]
Srinivasa Vemuru Department of ECCS Ohio Northern University Ada, OH 45810
[email protected]
Abstract - As the technology scales down, the reduced spacing between the individual wires within a bus results in increased crosstalk. This increases power dissipation particularly in wide data buses. We propose an efficient encoding scheme that significantly reduces the number of correlated switching (coupling transitions) as well as self-transitions among the wires in the data busses. The proposed scheme reduces the number of correlated switching by 67% compared to the Bus-Invert approach and by 50% compared to the EXODUS method in four-bit bus lines. This scheme also reduces the number of self transitions by 12% compared to EXODUS scheme and equals to those produced by Bus-Invert approach.
Keywords: Bus encoding, crosstalk, correlated switching, self transition 1. Introduction Low-power design has become a major concern due to the widespread use of the portable applications. As CMOS technology processes scale down to deep submicrometer dimensions (DSM), the wire aspect ratio (metal height/width) is increasing. For example, the aspect ratio increases from 1.8 for 0.18 µm process to 2.7 for 0.07 µm process [1]. In addition, the absolute spacing between the wires is reducing due to process scaling. As a result, the coupling capacitances (Cc) between the adjacent bus lines is increasing and has become dominant compared to the self-line capacitance (Cs). For instance, Cc/Cs can take values as high as 6 and 8 in 0.18 µm and 0.13 µm
Norman Scheinberg Department of EE The City College of CUNY New York, NY 10031
[email protected]
processes, respectively. In general, technology downscaling results in an increased wire aspect ratio and thus increase the value of Cc/Cs. Data Bus Lines CC
CC CS
CC CS
CC CS
CC CS
Figure 1. Bus model with self and coupling capacitances. Power dissipation in buses is related to the intrinsic capacitances of the bus lines (i.e., self and coupling capacitances see Figure 1) and the nature of the switching activities that take place within the individual wires. In this paper, we study techniques to reduce these switching activities. Correlated switching occurs when two or more neighboring lines make opposite transitions at the same time. For example, one line switching from 1 to 0 while its adjacent wire is switching from 0 to 1. A selftransition occurs in a line when it switches from 1 to 0 or 0 to 1 regardless of the activities in the neighboring lines. Therefore every correlated transition also involves self transitions. Silent transition is transition when the line remains constant during two consecutive data transfers, for example 0 to 0 or 1 to 1. In Figure 2 we present
three types of possible data transitions [1]. In type A transitions there is no correlated switching. In type B transitions, there is one correlated switching. This is an undesirable case, because the effective coupling capacitance between lines 1 and 2 increases twice due to Miller effect. In type C transitions, there are two correlated switchings between the wire 2 and its two adjacent neighbors. This is the worst possible scenario since the coupling capacitance to both adjacent neighboring wires increases by a factor of 2 [2]. The number of self-transitions for A, B, and C types are 1, 2 and 3, respectively. To achieve power reduction we need to minimize type B and C transitions. Thus an encoding scheme to reduce the correlated switching results in reduced coupling capacitances effects. Another goal is to maximize the number of silent lines, which results in reduction in the number of self transitions (charging and discharging the bus lines self capacitances). An important component of the power dissipation in digital processors occurs during the transmission of data through high capacitance buses [3]. Several techniques have been proposed to reduce the power dissipation in these buses through the use of coding techniques, low-swing signaling and charge recycling [4-6]. The reduced swing communication suffers from reduced signal to noise ratio, especially as the supply voltages are scaled down [7-10]. The coding of data has been used for reducing power dissipation through the reduction of correlated and self-transitions. Bus-Invert technique conditionally inverts the transmitted data in the bus to reduce signal transitions [11]. If more than half
of the bits change, the whole bus is inverted. Therefore, in addition to the data, an extra bit must be transmitted to indicate if the bus is inverted. This approach only considers self-transitions and can yield larger number of correlated transitions. EXODUS scheme uses a combination XOR and XNOR conversion of data based on previous value and the next data to be transmitted; the primary focus of the scheme is to reduce the number of correlated transitions. However, it yields a larger number of self-transitions compared to Bus-Invert technique [1]. In this paper, we propose an encoding scheme that considers both correlated and self-transitions on general-purpose buses. Section 2 presents the details of the proposed scheme. Preliminary results are presented in Section 3 which is followed by conclusions. 2. The Proposed Scheme Our goal is to reduce the power dissipation that is related to transmitting information via a bus. Average power dissipation by the bus lines per bus cycle [7]: (1) Pave α (γc Cc + γ s Cs) Vdd2 where γc is the number of average coupling transitions per bus cycle and γs is the number of average self-transitions per bus cycle. Thus making signal transitions smoother, i.e., having less correlated and self-switching will result in reduced power dissipation.
line 1 C12 silent line
line 1
C12
C12 line 2
line 2
C23
C23
Correlated switching C23
self transition
C34 line 4
(a) ( )
Correlated switching
line 3
line 3 C34
Correlated switching
C34 (b)
line 4
Figure 2. Categorization of Signal Transitions in a Data Bus.
The proposed scheme encodes the data in a simple and straightforward scheme by applying either XOR or XNOR operation on the data to be transmitted and the previously transmitted data. Let D(t) denote the data on a bus at time t, and L[D(t)] is the encoded data of D(t). The m-bit bus is divided into subsets with each subset consisting of 4-bits. Computing the number of 0’s in the subset of D(t) that needs to be encoded will determine the encoding function as described below: L[D(t+l)] = L[D(t)] ⊕ D(t+l)
(2)
L[D(t+l)] = L[D(t)] ⊙ D(t+1) (3) If the number of 0’s is greater than the number of 1’s then the encoded data will be the XOR of the last transmitted data and the unencoded data using eqn (2). If the number of 0’s is less than the number of 1’s, then the encoded data will be the XNOR of the previously transmitted data and the unencoded data using eqn (3). When the number of 0’s and the numbers of 1’s are equal the appropriate equation from (2) and (3) is used as follows: (a) if the outputs have no correlated switching, the output will be generated with the control bit similar to that of last data transmission; (b) if one operation generates a correlated switching output is encoded using other operation, (c) if both outputs produced correlated switching, the output is transmitted with the same control bit as previous data. Table I summarizes the encoding operations. For example, assume L(t) = 1010 and the data to be encoded D(t+1) = 1000. The proposed scheme scheme encodes the data into L[D(t+1)] = 0010 by using XOR operation. Choice of encoding for some other values of D(t+1) are also given. A control line is transmitted along with the data with a value of ‘1’ or ‘0’ when eqn (2) or (3) is used in the encoding scheme respectively. At the receiving end of the bus, restoration of the original data is accomplished by simple decoding logic that uses the control line. The control line carries the information about whether XOR or XNOR encoding operation was used on the original data. Because of the XOR property that L[D(t+1)] ⊕ L[D(t)] = (L[D(t)] ⊕ D(t+l)) ⊕ L[D(t)] = D(t+1), which is also true for the XNOR operation, the original data can be restored by applying the same encoding operation on L[D(t+1)] and L[D(t)] at the receiver side. To implement the proposed
encoding scheme extra circuitry is needed on the data-path; which means additional area. The proposed scheme for reducing power dissipation like other methods represents a trade-off between area and power. 3. Results Since there are 22N possible transitions and Nbit changes per transition, there is a total of Nx22N possible bit changes for N-bit bus-lines [1]. We applied our encoding scheme, the Bus-Invert and EXODUS schemes to the 4-bit data lines for all these combinations. Table II summarizes the number of combination bits and the number of correlated switchings for our scheme, EXODUS scheme, Bus-Invert method and the unencoded data. The third row represents normalized correlated switching with the BusInvert scheme as the normalizing reference. Table III summarizes the number of combination bits, the number of self-transitions and the silent lines in our scheme, EXODUS scheme, Bus-Invert method, and the unencoded data. Third and fifth rows represent normalized self-transitions and silent lines to BusInvert method. The control lines are excluded in this comparison since they are present in all three schemes. Note that the proposed scheme reduced the number of correlated switching by 67% compared with the conventional Bus-Invert method and by 50% compared to the EXODUS method. It also reduces the number of self-transitions by 12% compared to EXODUS scheme and equal to that of the Bus-Invert. It increases the number of silent lines (desirable transitions) by 7% compared to EXODUS scheme and same as that of the BusInvert. It also removes all of type C transitions. The 4-bit bus was used as a building block to form wider buses, for example 8, 16, 32, and 64. An example using an 8-bit bus is given in Figure 3. Additional reduction in correlated switching is expected for larger bus structures because the proposed scheme also reduces the probability of the adjacent wires of the building blocks (each 4-bit wires) to switch from 1 to 0 and from 0 to 1. This is in addition to reduced self and correlated switching in four-bit bus structures. Example 1 shown in Figure 3 represents the data of
D1: D2: D3: D4: D5: D6: D7: D8:
01010011001010000101 10100000100101110111 11101011100110100001 00100001100111000110 10001010011000010111 00110011011100111000 10011001100010001110 10101110000101010111
(a) 20 randomly generated patterns to be transmitted on an 8-bit bus.
D1: D2: D3: D4: D5: D6: D7: D8:
00001010000010100010 10101000110111111110 10001111100000110000 00000011100001110101 10101010000110101010 01111011111110011111 11100010000000010001 11000111000101111111
(b) The encoded data after applying the EXODUS scheme.
D1: D2: D3: D4: D5: D6: D7: D8:
01110011010011111100 10000000111100001110 11001011111111011000 00000001111110111111 11111011111011100000 01000010111111001111 11101000000001111001 11011111100110100000
(c) The encoded data after applying the Bus-Invert scheme.
D1: D2: D3: D4: D5: D6: D7: D8:
01011100110110000011 11111110000011011111 10001100000001000100 00000000000000000001 11000000000111110001 00010001111111000100 11011101010100011111 11111000010001110001
d) The encoded data after applying the proposed scheme
Figure 3. Comparison of encoded data using different schemes for an 8-bit bus an 8-bit bus (D8-D1) transmitting 20 randomly generated patterns. The correlated switchings are highlighted. The unencoded data in Figure 3(a) consists of 80 self-transitions, 22 correlated switchings and 72 silent transitions. The data is encoded using EXODUS scheme in Figure 3(b). This data has 63 self-transition, 7 correlated switchings and 89 silent transitions. The data is encoded using the Bus-Invert approach in Figure 3(c). This data has 48 self-transitions, 6 correlated switchings and 104 silent transitions. In Figure 3(d), the proposed encoding scheme is applied and results in no correlated switching, 47 selftransitions and 105 silent transitions. In the second example of Figure 4, the data of a 16bit bus (D16-D1) transmitting 20 randomly generated patterns is presented. The unencoded data in Figure 4(a) consists of 154 self-transitions, 33 correlated switchings and 150 silent transitions. The data is encoded using EXODUS scheme in Figure 4(b). This data has 108 self-transitions, 12 correlated switchings and 195 silent transitions. The data is encoded using the Bus-Invert approach in Figure 4(c). This data has 92 self-transitions, 6 correlated switchings and 212 silent transitions. In Figure 4(d), the proposed encoding scheme is
applied and results in 91 self-transitions, 2 correlated switchings and 213 silent transitions. Table IV summarizes the results of applying EXODUS, Bus-Invert and the proposed scheme on the unencoded data of Figure 4(a). The proposed scheme results in reduced number of correlated switching compared to both EXODUS and BusInvert schemes. Similar results were obtained in other test cases.
4. Conclusions An encoding scheme for low power deep submicron designs has been presented that reduces both correlated and self-transitions types and can effectively reduce the power consumption in bus structures. The presented scheme efficiently reduces the correlated switching by 67% compared to the Bus-Invert method and by 50% compared to EXODUS method for a four-bit data bus. It also yields less number of self transitions compared to EXODUS method and matches those of the BusInvert method. For wider buses it yields more savings in power dissipation as a result of reducing the probability of switching from 1 to 0 and 0 to 1 in the interface between the 4-bit blocks.
D1: 11110001011010110110 D2: 10111010100000000111 D3: 00100100111000110111 D4: 01110010010000000011 D5: 11100110100000110000 D6: 00011100011101101001 D7: 00010100110001101011 D8: 01010111110011100110 D9: 11010100100110111101 D10: 10110101100100001010 D11: 00101100101010110010 D12: 00101111001110000100 D13: 01001010010111111000 D14: 10111101111010111110 D15: 01110010001111111110 D16: 01011100000101000010 (a) 20 randomly generated patterns to be transmitted on a 16-bit bus.
D1: D2: D3: D4: D5: D6: D7: D8: D9: D10: D11: D12: D13: D14: D15: D16:
11110011010110010011 10000001111010110010 00111111000000111000 00100100001111100000 10001011010100110001 00100111111101011111 01111101100000001001 00011111100011111111 11000110011101111011 10000111100001011110 00111100111111011011 00111110000111111111 01111010111001000110 11011111110000111101 00000000000011101111 00110100001111000000
(b) The encoded data after applying the EXODUS scheme.
D1: D2: D3: D4: D5: D6: D7: D8: D9: D10: D11: D12: D13: D14: D15: D16:
11110011111010110001 10111000000000000000 00100110011000110000 01110000110000000100 11111110100000100110 00000100011101111111 00001100110001111101 01001111110011110000 11100111111111000000 10000110111101110111 00011111110011001111 00011100010111111001 00001000010000000110 11111111111101000000 00110000001000000000 00011110000010111100
(c) The encoded data after applying the Bus-Invert scheme.
D1: 10000010110011011110 D2: 11110000011111111111 D3: 00011011110000100000 D4: 01111111000000000111 D5: 11011100011110011110 D6: 01110000110111110000 D7: 01111111111111110011 D8: 00000010000011111010 D9: 10101110001111010001 D10: 11101111110011110100 D11: 00000001111000100100 D12: 00000011000000000000 D13: 00011011100000000011 D14: 10111110101001111000 D15: 00110100001111111000 D16: 00000000000011010000 (d) The encoded data after applying the proposed scheme.
Figure 4. Comparison of encoded data using EXODUS, BI approach and the proposed scheme for a 16-bit bus
5. References [1] K.-H. Baek, K.-W. Kim and S.-M. Kang “ EXODUS: Inter-module bus-encoding scheme for system-on-a-chip,” Electronics Letters, Vol. 36, pp. 615-617, March 2000.
[2] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company Inc., 1990 [3] P. P. Sotiriadis and A. Chandrakasan, “Low Power Bus Coding Techniques Considering Inter-wire Capacitances,” in the Proceedings of IEEE Custom Integrated Circuits Conference, pp. 507-510, 2000.
[4] A. Chandrakasan, R. Brodersen, Low Power CMOS Design, IEEE Press, 1998. [5] K. Y. Khoo, A. Willson, Jr., “Charge recovery on a databus,” in the Proceedings of IEEE/ACM ISPLED, pp. 185-189, 1995. [6] B. Bishop, M. J. Irwin, “Databus charge recovery: Practical consideration,” in the Proceedings of IEEE/ACM ISPLED, pp. 85-87, August 1999. [7] Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, M. Aoki, “Sub-1-V swing internal bus architecture for future low-power ULSI’s,” IEEE Journal of SolidState Circuits, pp. 414-419, April 1993. [8] M. Hiraki, H. Kojima, H. Misawa, T. Akazawa, Y. Hatano, “Data-dependent logic swing internal bus architecture for ultra low-power LSI’s,” IEEE Journal of Solid-State Circuits, pp. 397-401, April. 1995. [9] H. Yamauchi, H. Akamatsu, T. Fujita, “An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI’s,” IEEE Journal of Solid-State Circuits, pp. 423-431, April. 1995. [10] H. Zhang, J. Rabaey, “Low swing interconnect interface circuits,” in the Proceedings of ISPLED, pp. 161-166, August 1998. [11] M. R. Stan, W. P. Burleson, “Bus-Invert Coding for Low-Power I/O,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 1, pp. 49-58, March 1995.
TABLE I. A sample of encoding operations L[D(t)] = 1010 D(t + 1)
Encoding operation
1000 1110 1010 0110 1100
XOR XNOR XOR XNOR XOR
Encoded data L[D(t+1)] 0010 1011 0000 0011 0110
0011 1001 0101
XNOR XOR XNOR
0110 0011 0000
TABLE II. Correlated switching Comparison in 4 bit data lines Unencoded Number of combination bits Number of correlated switchings Normalized correlated switchings
BusOurEXODUS Invert scheme
1024
1024
1024
1024
96
24
16
8
4
1
0.67
0.33
TABLE III. Self transition and Silent Line
Comparison in Example 1 Unencoded Total combinations Number of Self transitions Normalized self transitions Number of silent lines Normalized correlated switchings
BusOurEXODUS Invert scheme
1024
1024
1024
1024
512
320
364
320
1.6
1
1.14
1
512
704
660
704
0.73
1
0.94
1
TABLE IV. Summary of Results for Example 2
Number of selftransitions Number of correlated switchings Number of silent transitions
Unencoded
BusInvert
EXODUS
Our scheme
154
92
108
91
33
6
12
2
150
212
195
213
