A comparative study of resonant inverter topologies ... - IEEE Xplore

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between four inverter topologies commonly used in induction cookers. ... and they are compared in aspects such as power device stresses, efficiency, frequency ...
A Comparative Study of Resonant Inverter Topologies Used in Induction Cookers. S. Llorente1,2, F. Monterde2, J.M. Burdío 1, and J. Acero1 1

2

Dept. Ingeniería Electrónica y Comunicaciones Universidad de Zaragoza María de Luna 3 50015 Zaragoza, SPAIN e-mail: [email protected]

BSH Balay Bosch-Siemens Home Appliances Group Avda. de la Industria 49 50089 Zaragoza, SPAIN e-mail: [email protected]

ZCS one [8,9]. Every topology has one optimum point, which is presented and used for the design. The design is complete if several aspects are known such as values of components and maximum rates of current and voltage in devices.

Abstract- In this paper a comparison is performed between four inverter topologies commonly used in induction cookers. The considered topologies are the full-bridge inverter, the half-bridge inverter, and two single-switch inverters. All of them are designed for the same specifications and they are compared in aspects such as power device stresses, efficiency, frequency control, and electromagnetic emissions.

Leq

Req

I. INTRODUCTION Domestic induction cookers are made up of a copper coil placed below a ferromagnetic pan as shown in Fig. 1(a). The induction coil is connected to a mediumfrequency (20-100 kHz) power source producing an alternating magnetic field, which causes eddy currents and magnetic histeresis, heating up the pan. The coupling between the coil and the pan is modeled as the series connection of an inductor and a resistor, based on the transformer analogy and it is defined by the values of Leq and Req [1] (Fig. 1(b)). The load power factor is usually around 0.5.

(a)

Fig. 1. (a) Pan-Inductor, (b) L-R equivalent circuit.

In this paper it has been performed an optimum design of each of these topologies for induction cookers with the same specifications. The results of those designs are presented comparing several aspects. This has been carried out by means of simulation programs in Matlab using a unified discrete-time state-space model [10] for every topology. The results have been verified experimentally.

A typical arrangement of induction cookers is shown in Fig. 2. Induction cookers take the energy from the mains voltage, which is rectified by a full bridge of diodes. A bus filter is designed to allow a big voltage ripple getting a resultant input power factor close to one. Then the inverter topology supplies the high-frequency current to the induction coil. Due to this ripple all components must be designed for the voltage and current peak values (Fig. 2).

The paper is organized as follows. First, the common specifications are presented, then they are assigned to each inverter topology, and finally, comparison and some experimental conclusions are shown. I

Design specifications for the inverter are the input voltage, maximum and minimum output powers, switching frequency and performance features of each inverter topology. Some main aspects for the performance are: maximum rates of current and voltage that devices must withstand, efficiency, frequency control of output power, and electromagnetic emissions.

Rectification

V

V

II

IO

Inverter

VI

VO

VI

VO

II

I

Inverter topologies commonly used for induction heating are the full-bridge [2-4], half-bridge [5,6] and two single-switch inverter topologies, a ZVS one [7,8] and a

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(b)

Pan-inductor

IO

Fig. 2. Typical arrangement of induction cookers.

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II. DESIGN CONSIDERATIONS

 Req 1 1 − fn = · 2·π Leq ·C  2·Leq 

The same design specifications are needed to compare the four inverter topologies and they are discussed as follows:

2

(3)

where VI is the input dc bus voltage (Fig. 3).

• Input voltage (Vrms): Two input voltages of 100 V and 230 V were chosen for the comparison. • Maximum output power (Pmax): Maximum output powers of 3000 W and 1000 W were assumed. • Minimum output power (Pmin): As minimum power demanded it was considered a 25% of the maximum power. • Switching frequency (fsw): A switching frequency of 50 kHz was assumed for the design for maximum powers, varying it to obtain lower powers. Also, IGBT devices were assumed for all devices.

The main waveforms of the series-resonant fullbridge are shown in Fig. 4. VO Leq

VI

Req

C

IO VLOAD

It is also assumed in the design a typical value of 0.5 for the power factor for the pan-inductor coupling (1).

FP =

   

Fig. 3. Full – bridge with a series-resonant load.

VLOAD

Req 2

Req + ( Leq ·2·π · f sw )

2

≅ 0.5

IO

(1)

t (a)

Vo IO

III. ANALYSIS OF THE INVERTER TOPOLOGIES

t

Each considered topology has been analyzed and simulated with optimization programs in Matlab using a unified discrete-time state-space model [10]. The design has been carried out to ensure specifications by means of an iterative method. The final results include the values of components and voltages and currents through the devices for the optimum operation.

(b) Fig. 4. Typical waveforms of Full – bridge with a series-resonant load, (a) Load current and voltage. (b) Output current and voltage.

The results are the design values of components and voltages and the currents withstood by the devices, as follows in Table I.

A. Full-bridge inverter The full-bridge topology is the most complete allowing many control possibilities. In this case the fullbridge topology with a series resonant load LRC is analyzed (Fig. 3). The following characteristics were assumed for the design at maximum output power: • Square wave: since it provides the highest rms voltage in the load (VLOAD). Equation (2) shows the decomposition in harmonics. • Switching frequency equal to natural oscillation frequency of the load (fn) (3): since it provides that the power factor for the load at the switching frequency is one.

V LOAD rms h =

4·V I

π ⋅h⋅ 2

, h odd

TABLE I. DESIGN VALUES OF COMPONENTS AND SEMICONDUCTOR STRESSES FOR FULL-BRIDGE TOPOLOGY.

Values of components

Vrms (V) 100 V

230 V

Pmax (W) 1000 3000 1000 3000

Leq



44.0 14.6 232.9 77.7

Req ( ) 8.0 2.7 42.2 14.1

C (nF) 212 637 40 120

Semiconductor stresses VSWmax ISWmax (A) (V) 141 22.8 141 68.7 325 9.8 325 29.7

B. Half-bridge inverter topology The half-bridge topology (Fig. 5) is the most used in induction cookers, due to its robustness and simplicity. The characteristics assumed for the design at maximum output power are:

(2)

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• Square wave: since it provides the highest rms voltage in the load (VLOAD). Equation (4) shows the decomposition in harmonics. • Switching frequency equal to natural oscillation frequency of the load (fn) (3): since it provides that the power factor for the load at the switching frequency is one.

V LOAD rms h =

designs can be established with a direct relation between them, as are shown in Table III. TABLE III. RELATION BETWEEN HALF -BRIDGE TOPOLOGY AND FULL BRIDGE TOPOLOGY DESINGS.

Half Bridge/Full Bridge

2·V I

π ⋅h⋅ 2

, h odd

(4)

VI

The ZVS single-switch inverter (1SW-ZVS) considered is shown in Fig. 7. The conditions for optimum switching [7] are used for the design, as defined by (5) and (6).

C/2

VO Req

V (t = T) = U

(5)

O

IO

dV

VLOAD

C 4

Req 1/4

Leq 1/4

C. ZVS single-switch inverter

The main waveforms of the series-resonant fullbridge are shown in Fig. 6.

Leq

Semiconductor Stress VSWmax ISWmax 1 2

Values of components

= 0 or I (t = T) = 0

O

C/2

dt Fig. 5. Half – bridge inverter topology.

(6)

O

t =T

Therefore, the characteristics assumed for the design are: • The optimum switching conditions are used when the power is minimum, so that the ZVS operation will be always guaranteed.

VLOAD IO t a)

VO

The waveforms of the 1SW-ZVS topology for optimum switching are shown in Fig. 8.

IO t

C

VO b)

Leq

VI

Req

I IO

Fig. 6. Typical waveforms of Half – bridge, a) Load current and voltage, b) Output current and voltage.

The values obtained of the components and semiconductor stresses for the chosen designs are shown in Table II.

Fig. 7. 1SW-ZVS inverter topology.

TABLE II. DESIGN VALUES OF COMPONENTS AND SEMICONDUCTOR STRESSES FOR HALF -BRIDGE TOPOLOGY.

Values of components

Vrms (V) 100 V

230 V

Pmax (W) 1000 3000 1000 3000

Leq ( H) 11.0 3.6 58.2 19.4

Req ( ) 2.0 0.7 10.5 3.5 

C (nF) 848 2548 160 480

IO

Semiconductor stresses VSWmax ISWmax (A) (V) 141 45.6 141 137.4 325 19.6 325 59.4

t VO

t=T

Fig. 8. Typical waveforms of 1SW-ZVS: output current and voltage.

Comparing the half-bridge topology to the full-bridge one both have a very similar performance. In fact, their

The results obtained are shown in Table IV.

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TABLE IV. DESIGN VALUES OF COMPONENTS AND SEMICONDUCTOR STRESSES FOR 1SW-ZVS TOPOLOGY.

Leq ( H) 23.1 7.7 122.3 40.7

Pmax (W) 1000 3000 1000 3000

230 V

Req ( ) 4.1 1.4 22.2 7.4 

ILs

Semiconductor stresses VSWmax ISWmax (A) (V) 885 31.2 885 93.7 2035 13.6 2035 40.8

Values of components

Vrms (V) 100 V

∆ILs

Vrms (V) 23.1 69.4 4.4 13.1

IO

VO

IO

D. ZCS single-switch inverter

I (t = D·T) = I (t = D·T) dI

Ls

dt

dI

=

L

Ls

dt

t = D·T

(7)

The values of components, the voltages and the currents in the devices (Table V) are obtained as a result of the design.

(8)

TABLE V. DESIGN VALUES OF COMPONENTS AND SEMICONDUCTOR STRESSES FOR 1SW-ZCS TOPOLOGY.

t = D·T

Values of components

∆ILs = I Ls avg / 2

Vrms (V) 100 V

230 V

(9)

VI

I LS

Req

Leq

IO

Pmax (W) 1000 3000 1000 3000

Ls ( H) 136 45.4 715 239.6

Leq ( H) 27.0 9.1 144.9 48.1

Req ( ) 4.9 1.7 26.3 8.7 

C (nF) 208 619 39 117

Semiconductor stresses VSWmax ISWmax (A) (V) 526 48.3 526 143.7 1207 20.8 1207 62.6

IV. COMPARISON BETWEEN INVERTER TOPOLOGIES

The usual waveforms of the 1SW-ZCS input and output current and voltage and current in the load are shown in Fig. 10.

ILs

t

Fig. 10. Typical waveforms of 1SW-ZCS: a) Input and output currents. b) Output current and voltage.

The characteristics assumed for the design are: • Optimum switching: which is assumed for the maximum power to ensure ZCS switching for all possible powers. • Ripple of input current (∆ILs): The value of one half of the average current is assumed as input ripple:

Ls

t = T·D b)

The schematic of the ZVS single-switch inverter (1SW-ZCS) studied in this paper is shown in Fig. 9. The design is carried out by means of the optimum switching [9]. In this case (7) and (8) define the used conditions.

L

t

a)

The comparison between inverter topologies is performed independently of the specifications. This is carried out defining the specification parameters for each magnitude. Those are used to obtain the independent adimensional parameters which are compared. Table VI shows the main magnitudes and the specification parameters used to perform the comparison.

I

o

VO

TABLE VI. SPECIFICATION PARAMETERS FOR EACH MAGNITUDE

C

Fig. 9. 1SW-ZCS inverter topology.

Magnitude Voltage

Specification parameter

Power

Pmax

Frequency

f sw

Time

Vrms

1 f sw

Current

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Pmax Vrms

Inductance

2

I SWmax = k Iswmax ·

Vrms Pmax ⋅ f sw

Capacity

Pmax

(11)

TABLE VIII. VALUES OF ADIMENSIONAL CONSTANTS OF SEMICONDUCTOR

2

Vrms ⋅ f sw

Resistance

Pmax Vrms STRESSES

2

Vrms Pmax

The values of the specification parameters depend on the design specifications. These values are shown for each magnitude in Table VII. MAGNITUDE AND EACH DESIGN SPECIFICATIONS

Vrms (V) Pmax (W)

Voltage (V) Power (W) Frequency (kHz) Time ( s) Current (A) Inductance (µH) Capacity (nF) Resístanse (Ω)

100 3000 1000 100 100 1000 3000 50 50 20 20 10,0 30,0 200,0 66,7 2000,0 6000,0 10,0 3,3

230 3000 1000 230 230 1000 3000 50 50 20 20 4,3 13,0 1058,0 352,7 378,1 1134,2 52,9 17,6

B) Efficiency The efficiency is an important parameter as it informs of the heat losses that must be removed by the heat sink. The conduction losses, which are the most important in all cases, depend on the rms and average current (Iswrms and Iswavg) that goes through them. These can be calculated as shown in (12) and (13), where kIswrms and kIswavg are adimensional constants that depend on the topologies (Table IX).

Some interesting consequences can be reached from Tables VI and VII: • Every voltage just depends on the input voltage. • Currents are proportional to the required output power and inversely proportional to the input voltage. • Capacitor and inductor values are inversely proportional to the switching frequency. • Inductor values are increased with the squared input voltage and are inversely proportional to the required power. However, capacitor values increase with the power while they are inversely proportional to the squared voltage.

I SWrms = k Isw rms ·

Pmax Vrms

(12)

I SWavg = k Isw avg ·

Pmax Vrms

(13)

TABLE IX. VALUES OF CONSTANTS OF RMS AND AVERAGE DEVICE CURRENTS

kIswrms 1.12 2.25 1.99 2.28

Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

The considered comparison aspects are semiconductor stresses, efficiency, power control, and electromagnetic emissions.

kIswavg 0.71 1.42 1.58 1.42

The conduction losses in each device (Psw) can be calculated by means of the rms and the average currents and the device parameters of conduction (Vsw and Rsw):

A) Semiconductor stresses

Psw = I SWavg ·V sw + I SWrms ·R sw 2

The semiconductor stresses are the maximum voltages and currents (VSWmax, ISWmax) that devices must withstand. Those can be calculated by (10) and (11) where kVswmax y kIswmax are adimensional constants that only depend on the topologies. The values of those constants for each topology can be found in Table VIII. VSWmax = kVswmax ·Vrms

kIswmax 2.28 4.56 3.12 4.83

As a result, the devices of the single-switch inverter topologies must withstand higher voltages than those of the half-bridge and the full-bridge inverters. The devices of the full-bridge topology withstand the lowest currents.

TABLE VII. VALUES OF THE SPECIFICATION PARAMETERS FOR EACH

Magnitude

kVswmax 1.41 1.41 8.85 5.25

Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

(14)

The devices must be chosen in order to withstand the maximum voltage and have the appropriate performance in conduction. The devices used for the implementation of the topologies for the cases of 3000 W and 230 V and their conduction parameters are shown in Table XIII. The losses per device (Psw), the overall losses (Ptot) and the efficiency ( ) can be observed in Table X.

(10)



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the voltage supplied to the load (VO) and the big coil area, which causes a high parasitic capacity. The values of the main adimensional harmonics of each one of the inverter topologies are shown in Table XI and XII.

TABLE X. DEVICE LOSSES AND EFICIENCY.

Ptot (W) 38.162 49.676 71.081 57.421

Psw (W) 9.540 24.838 71.081 57.421

Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

(%) 98.74 98.37 97.68 98.12

TABLE XI. MAIN ADIMENSIONAL HARMONICS OF INPUT CURRENT (II) (DIFFERENTIAL MODE ). I h / (Pmax/Vrms)

As consequence the full-bridge inverter is the most efficient topology, even though the different results are quite similar.

Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

C) Power control

fsw

2·fsw

3·fsw

0.0079 0.0236 1.2846 0.3721

0.6929 0.6929 0.5692 0.0853

0.0024 0.0047 0.2462 0.2791

THD (%) 70.73 70.76 142.78 51.11

TABLE XII. MAIN ADIMENSIONAL HARMONICS OF OUTPUT POWER (VO) (COMMON MODE ).

The inverter must be able to let the power control in order to be adjusted to the user’s requirements. This control is normally carried out by varying the switching frequency. This variation is defined by the modulation factor (m) related to the frequency at maximum power (fsw Pmax) (15). f sw = m· f sw P max

Mains freq. 1 1 1 1

VO h / Vrms Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

fsw 2.465 1.226 1.130 1.835

2·fsw 0.024 0.028 1.087 1.196

3·fsw 0.470 0.235 1.004 0.435

4·fsw 0.020 0.023 0.900 0.370

5·fsw 0.260 0.129 0.774 0.230

6·fsw 0.019 0.022 0.639 0.222

7·fsw 0.181 0.088 0.504 0.165

According to Table XI the 1SW-ZCS inverter topology has the best performance in differential mode due to its input inductance. The best topology in common mode is the half-bridge one, because the resultant harmonics of the decomposition of the inductor voltage have the lowest amplitude.

(15)

The frequency variation necessary to let the power control with each inverter topology is shown in Fig. 11. 1

0.9

V. EXPERIMENTAL CONVERTERS

0.8

Topology designs have been verified with experimental converters. These have been built using IGBT transistors (Table XIII). The control circuits have been implemented using Programmable Logic Devices (Altera EPM9320ALC) with the VHDL hardware description language. Next the experimental converters are shown and some aspects are pointed out.

P o/P m ax

0.7

0.6

1SW- ZVS

0.5

0.4

1SW- ZCS Full-bridge and Half-bridge

0.3

0.2 0.6

0.8

1

1.2

1.4

1.6 m

1.8

2

2.2

2.4

2.6

TABLE XIII. IGBT TRANSISTORS USED FOR EACH INVERTER TOPOLOGY AND THEIR CONDUCTION CHARACTERISTICS .

Fig. 11. Frequency control of output power.

Full-bridge Half-bridge 1SW-ZVS 1SW-ZCS

The 1SW-ZCS inverter topology allows the lowest frequency variation for the minimum output power. D) Electromagnetic emissions

IGBT STW20NB60H STW20NB60H GT50J101 SGL40NB150TU

Vsw (V) 1.3 1.3 1.7 1.6

Rsw (mΩ) 26 26 96 75

The PCB of the full-bridge inverter topology (Fig. 12) is the most complex due to its number of devices. However, its sink is the smallest one, because of the best efficiency of this topology.

The most important electromagnetic emissions in induction cookers are the conducted ones through the mains voltage (Fig. 2). The conducted electromagnetic emission depends on the differential mode and the common mode. The former is due to the absorbed input current (II). The latter is due to

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V. CONCLUSIONS The common resonant inverter topologies applied to induction cookers have been designed and implemented. The different aspects have been compared systematically. The full-bridge topology is the most efficient one due to the low current through its devices, however, its implementation is complex. The half-bridge topology offers an appropriate balance between complexity and performances. The single-switch topologies are simple because of their low number of components but their devices must withstand high voltages, therefore their efficiency is low. Also, their controls are complex.

Fig. 12. Full-bridge inverter topology.

The implementation of the half-bridge inverter topology (Fig. 13) is very interesting because the PCB and the control requirements are not very complex. As a result, its implementation is expected to be robust.

REFERENCES [1] F.P. Dawson and Praveen Jain, “System for Induction Heating and Melting Applications, a comparison of Load Commuted Inverter” in IEEE Power Electronics Specialist Conf. Rec 1990, pp. 281-290. [2] H. Ogiwara and M. Nakaoka, “Induction heating high frequency inverters using static induction transistors”, International Journal Electronics, 1990, vol. 68, pp. 629645. [3] E.J. Dede et al. “High frequency generators for induction heating”, PCIM Europe, vol. 3, 1991. [4] F. Monterde et al. “A new ZVS two-output series-resonant inverter for induction cookers obtained by a synthesis method” IEEE Power Electronics Specialist Conf., Rec.2000, pp. 1375-1380. [5] L. Hobson, D.W. Tebb and Turnbull, “Dual element induction cooking unit using power MOSFETs”, International Journal Electronics, vol. 59, nº 6, pp. 747757, 1985. [6] H.W.Koertzen, J.D. Van Wyk and J.A. Ferreira, “Desing of the half-bridge series resonant converters for induction cooking”, IEEE Power Electronics Specialist Conference Rec., 1995, pp 729-735 [7] H. Omori, H Yamasita, M. Nakaoka and T. Maruhashi, “A novel type induction-heating single ended resonant inverter using new bipolar Darlington-transistors”, IEEE Power Electronics Specialist Conference Rec., 1985, pp 590-599 [8] I Cohen H. “Evaluation and Comparison of Power Conversion Topologies”, European Power Electronics Conference Rec., 1993, pp 9-16 [9] J.M. Leisten and L. Hobson, “A parallel resonant power supply for induction cooking using a GTO”, PEVD Conference Rec., 1990 pp 224-230. [10] J.M. Burdio and A. Martínez, “A Unified Discrete-Time State-Space Model for Switching Converters” IEEE Transactions on Power Electronics, vol. 10, pp. 694-707, Nov. 1995.

Fig. 13. Half-bridge inverter topology.

The implementations of the single-switch topologies (Fig. 14 and 15) are simple due to their low number of components. Nevertheless, its control is complex because of the feedback needed.

Fig. 14. 1SW-ZVS inverter topology.

Apart from the difficulties of the one-switch topologies, the ZCS one has an input inductor (Inductor Ls in Fig. 9) whose implementation is very complex due to the great current through it.

Fig. 15. 1SW-ZCS inverter topology.

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