Article
A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs Min-Kyu Kim, Seong-Kwan Hong and Oh-Kyong Kwon * Received: 17 November 2015; Accepted: 22 December 2015; Published: 26 December 2015 Academic Editor: Gonzalo Pajares Martinsanz Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea;
[email protected] (M.-K.K.);
[email protected] (S.-K.H.) * Correspondence:
[email protected]; Tel.: +82-2-2220-0359; Fax: +82-2-2297-2231
Abstract: This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 ˆ 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 µm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 µs to 0.45 µs and random noise from 848.3 µV to 270.4 µV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. Keywords: successive approximation register ADC; column parallel readout; CMOS image sensor
1. Introduction Recently, noise performance of CMOS image sensors (CISs) has become an important factor for images captured under low light conditions. The CIS typically uses a programmable gain amplifier (PGA) and a multiple sampling method to suppress noise caused by the pixel and readout circuit [1–8]. The PGA amplifies the pixel output and reduces noise with respect to the gain of the PGA. The readout circuit using the multiple sampling method repeatedly samples the pixel output and then averages the sampled pixel outputs to reduce noise by one over the square root of the number of samplings [7,8]. Several multiple sampling methods, such as the correlated multiple sampling (CMS), digital correlated multiple sampling (DCMS), and pseudo-multiple sampling (PMS) methods, have been studied for CISs with single-slope analog-to-digital converters (SS ADCs) [4–6]. The CMS method repeatedly integrates and averages the pixel output in the analog domain, but requires a power-consuming amplifier [4]. The DCMS method repeatedly converts the pixel output to a digital signal and averages the A/D conversion results in the digital domain. However, the total A/D conversion time increases in proportion to the number of samplings [5]. An alternative solution to DCMS, the PMS method which uses multiple ramp signals with different offsets is reported [6]. However, it requires an accurate ramp generator to control the offset of multiple ramp signals. Several ADCs using the multiple sampling method have been researched to achieve low noise and overcome the drawbacks of SS ADC, which makes achieving short conversion time and high resolution difficult. A ∆Σ ADC easily achieves low noise by repeating sampling and integrating Sensors 2016, 16, 27; doi:10.3390/s16010027
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Several ADCs using the multiple sampling method have been researched to achieve low noise and overcome the drawbacks of SS ADC, which makes achieving short conversion time and high resolution difficult. A ΔΣ ADC easily achieves low noise by repeating sampling and integrating Sensors 2016, 16, 27 2 of 14 operations, but requires many clocks and a complex decimation filter [9]. An extended counting ADC (EC ADC) achieves short conversion time by sequentially converting the pixel output to the upper bit by ΔΣ ADC theand lower bit by using cyclic filter ADC.[9]. However, an operational operations, butusing requires many and clocks a complex decimation An extended counting amplifier in EC achieves ADC increases power consumption [10,11]. A converting successive approximation ADC (EC ADC) short conversion time by sequentially the pixel outputregister to the ADC (SAR consumes lessthe power to using its simple [3,12–15] reduces amplifier noise by upper bit byADC) using ∆Σ ADC and lowerdue bit by cyclicstructure ADC. However, anand operational using the PMS method [14].consumption However, since the SAR ADC repeats the operation of the 1st(SAR A/D in EC ADC increases power [10,11]. A successive approximation register ADC conversion, longless A/Dpower conversion is required. ADC) consumes due totime its simple structure [3,12–15] and reduces noise by using the PMS This paper proposes a fast (FMS) method for CIS withconversion, SAR ADC to achieve method [14]. However, since the multiple SAR ADCsampling repeats the operation of the 1st A/D long A/D short conversion times and low noise. A 12-bit SAR ADC using the proposed FMS method conversion time is required. repeatedly converts the pixel tosampling the lower 4-bitmethod among for theCIS 12-bit Therefore, the This paper proposes a fast output multiple (FMS) withoutput. SAR ADC to achieve required numbertimes of bitand conversion steps is reduced to one-third. 12-bit SAR in the readout short conversion low noise. A 12-bit SAR ADC using theThe proposed FMSADC method repeatedly channel employs 10-bittocapacitor DAC fourthe scaled voltages tothe reduce the number area. In converts the pixel aoutput the lower 4-bitwith among 12-bitreference output. Therefore, required addition, a simplesteps digital processing logic consisting of a 3-input MUX andreadout toggle flip-flop is of bit conversion is reduced to one-third. The 12-bit SAR ADC in the channel (T-F/F) employs to perform complex calculations forvoltages multipletosampling andarea. digital correlateda simple double aproposed 10-bit capacitor DACthe with four scaled reference reduce the In addition, sampling (DCDS).logic In Section 2, the thetoggle developed CIS(T-F/F) is described, along the digital processing consisting of aarchitecture 3-input MUXofand flip-flop is proposed to with perform operating principle of thefor proposed method. Section presents the circuit implementations of the complex calculations multipleFMS sampling and digital3 correlated double sampling (DCDS). In the SAR2,ADC and the digital processing logic the readoutalong channel. Section 4, the experimental Section the architecture of the developed CIS in is described, withIn the operating principle of the results of FMS the developed CIS are analyzedthe and compared with prior of works. Finally, are proposed method. Section 3 presents circuit implementations the SAR ADCconclusions and the digital given in Section 5. the readout channel. In Section 4, the experimental results of the developed CIS are processing logic in analyzed and compared with prior works. Finally, conclusions are given in Section 5. 2. CIS Architecture 2. CIS Architecture 2.1. Block Diagram 2.1. Block Diagram Figure 1 shows the block diagram of the developed CIS employing the proposed FMS method. Figure 1 shows the blockof diagram of the developed CIS employing the proposed The pixel array is composed 256 × 128 pixels with a pixel size of 4.4 μm × 4.4 μm. FMS Each method. readout The pixel array is composed of 256 ˆ 128 pixels with a pixel size of 4.4 µm ˆ 4.4 µm. Each readout channel, consisting of a PGA, a 12-bit SAR ADC, a digital processing logic, and a column decoder, channel, consisting of aand PGA, a 12-bitthe SAR ADC, a digital processing logic,array and atocolumn has a pitch of 17.6 μm converts four column outputs of the pixel digitaldecoder, signals. has a pitch of 17.6 µm and converts the four column outputs of the pixel array to digital signals.
Figure 1. Block diagram of the developed CIS with a schematic schematic of of pixel pixel circuit. circuit.
The PGA amplifies the pixel output, VPIX , and then the 12-bit SAR ADC using the proposed FMS method repeatedly converts the PGA output, VPGA , to a digital signal. The digital processing logic simultaneously performs the calculations for multiple sampling and DCDS. The output of the digital
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The PGA amplifies the pixel output, VPIX, and then the 12-bit SAR ADC using the proposed FMS 3 of 14 method repeatedly converts the PGA output, VPGA, to a digital signal. The digital processing logic Sensors 2016, 16, 27 simultaneously performs the calculations for multiple sampling and DCDS. The output of the digital processing logic selected by the column decoder isistransferred totothe sense amplifier. To reduce processing column decoder transferred the sense reducethe the The logic PGA selected amplifiesby thethe pixel output, VPIX, and then the 12-bit SAR ADCamplifier. using theTo proposed area and power consumption, four images obtained from each column output are externally area and power consumption, four images obtained from each column output are externally combined FMS method repeatedly converts the PGA output, VPGA, to a digital signal. The digital processing combined toentire formimage. an entire timing circuit generates control for output the rowofdriver, to form Theimage. timing circuit generates control signals for thesignals row driver, readout circuit, logic an simultaneously performs the The calculations for multiple sampling and DCDS. The the readout circuit, and logic sense amplifier, while the bias andisreference circuits provide the bias anddigital sense amplifier, whileselected the bias reference circuits provide the bias reference voltages, processing byand the column decoder transferred to theand sense amplifier. Toand reference for the PGA and SAR ADC. from each column output are reducevoltages, thefor area and consumption, four12-bit images obtained respectively, therespectively, PGApower and 12-bit SAR ADC. Figure 2 shows the operating sequence of the developed CIS time. pixels externally combined to form an entire image. The timing circuit generates signals for The the Figure 2 shows the operating sequence of the developed CIS in in acontrol a row row line line time. Therow pixels driver, readout circuit, and sense amplifier, while the voltage, bias and reference the bias and selected by SX generates aa pixel pixel reset voltage, VPIX_RST PIX_RST, circuits photo-induced signal selected by SX sequentially sequentially generates reset V ,and andaaprovide photo-induced signal reference respectively, the PGA and 12-bit SAR ADC. voltage, VVPIX _voltages, SIG, according to the for control signals, RX and TX, respectively. The PGA with a gain of voltage, PIX_SIG , according to the control signals, RX and TX, respectively. The PGA with a gain of Figure 2 shows the operating sequence of the developed CIS a rowvoltage, line time. The pixels GG generates a PGA reset voltage, V PGA _ RST , and an amplified signal voltage, PGA_RST ++ G generates a PGA reset voltage, VPGA_RST , and an amplified pixel pixelinsignal VVPGA_RST G ׈ selected by SX sequentially generates a pixel reset voltage, V PIX_RST, and a photo-induced signal (V _RST – VPIX_SIG), according to the pixel output. The SAR ADC using the proposed FMS method (VPIX PIX_RST – V PIX_SIG ), according to the pixel output. The SAR ADC using the proposed FMS method voltage, VPIX_SIG, accordingoftosamplings the control signals, RX and TX, respectively. The PGA12-bit with a gain of has the has the maximum maximum number number of samplings of of 17. 17. At At the the first first A/D A/Dconversion, conversion,the the 12-bitSAR SARADC ADC G generates a PGA reset voltage, VPGA_RST, and an amplified pixel signal voltage, VPGA_RST + G × converts to 12-bit, and then repeatedly converted V PGA toto the lower 4-bit. The digital processing convertsVVPGA to 12-bit, and then repeatedly converted V the lower 4-bit. The digital processing PGAADC using the proposed FMS method (VPIX_RSTPGA – VPIX_SIG), according to the pixel output. The SAR logic combines the sequentialoutputs outputsofofthe thecomparator comparator to obtain the A/D conversion result, logic combines the sequential to obtain A/D conversion and and then has the maximum number of samplings of 17. At the first A/D the conversion, the 12-bitresult, SAR ADC then subtracts the A/D conversion result of V PGA _ RST from that of V PGA _ RST + G × (V PIX _ RST – V PIX _ SIG).). subtracts the A/D conversion result of VPGA_RST fromVthat of V lower 4-bit. + G The ˆ (Vdigital – VPIX_SIG PIX_RST to 12-bit, and then repeatedly converted PGA to thePGA_RST processing converts VPGA Finally, the digital processing logic output becomes the A/D A/D conversion conversion result of of GGresult, (VPIX_RST PIX_RST –– Finally, digitalthe processing output becomes the ˆ× (V logic the combines sequentiallogic outputs of the comparator to obtain the A/D result conversion and VVPIX _ SIG) [16,17]. ) [16,17].the A/D conversion result of VPGA_RST from that of VPGA_RST + G × (VPIX_RST – VPIX_SIG). then subtracts PIX_SIG Sensors 2016, 16, 27
Finally, the digital processing logic output becomes the A/D conversion result of G × (VPIX_RST – VPIX_SIG) [16,17].
Figure Figure2.2.Operating Operatingsequence sequenceininaarow rowline linetime. time. Figure 2. Operating sequence in a row line time.
2.2. Operating Principle of the Proposed FMS Method 2.2. Operating Principle of the Proposed FMS Method 2.2. Operating Principle of the Proposed FMS Method Figure 3 shows the signal flow diagram of the proposed FMS method. The proposed FMS Figure 3 shows the signal flow diagram of the proposed FMS method. The proposed FMS method method Figure operates in fourthe steps: (1) flow An N-bit ADC the input VIN, to an N-bitFMS digital 3 shows signal diagram of converts the FMS voltage, method. proposed operates in four steps: (1) An N-bit ADC converts theproposed input voltage, V I N , to The an N-bit digital signal, signal, D1st_N-bit , for the VIN is a constant CIS applications; (2) digital An N-bit method operates in first four A/D steps:conversion, (1) An N-bitwhere ADC converts the inputfor voltage, VIN, to an N-bit D1st_N ´bit , for the first A/D conversion, where V I N is a constant for CIS applications; (2) An N-bit signal, D1st_N-bit , for thetofirst conversion, VIN isthen a constant for CIS applications; (2)obtained An N-bit by DAC converts D1st_N-bit an A/D analog voltage,where V1st, and the error voltage, VERR, is DAC converts D1st_N ´bit to an analog voltage, V1st , and then the error voltage, VERR , is obtained by DAC converts D1st_N-bit to anno analog voltage, V 1st, and then the V error is obtained by subtracting V1st from VIN. With quantization errors and noise, 1st is voltage, equal toVVERR IN,, and VERR becomes subtracting V1st from V I N . With no quantization errors and noise, V1st is equal to V I N , and VERR subtracting V1st from IN. With no quantization errors and noise, V1st is equal to VIN, and VERR GND. (3) An M-bit ADC Vconverts VERR to the lower M-bit among the N-bit output, where the range becomes GND. (3)(3)An thelower lower M-bit among N-bit output, where ERRtotothe GND. AnM-bit M-bitADC ADCconverts converts V VERR M-bit among thethe N-bit output, where of Vbecomes ERR is determined by the quantization error and noise. The proposed FMS method repeats the thethe range of V is determined by the quantization error and noise. The proposed FMS method of ERR Vsteps ERR is determined by the quantization error and noise. The proposed FMS method second range and third (L − 1) times, where L is the number of samplings. Therefore, the lower M-bit repeats thethe second and 1) times, times,where whereLLisisthe thenumber number samplings. Therefore, repeats second andthird thirdsteps steps(L (L´ − 1) of of samplings. Therefore, the the conversion results, DKth_M-bit’s, are repeatedly obtained from the second to Lth A/D conversion, lower M-bit conversion ’s, are repeatedly obtained from the second to Lth A/D lower M-bit conversionresults, results,DD Kth_M-bit ’s, are repeatedly obtained from the second to Lth A/D Kth_M´bit where DKth_M-bit corresponds to the Kth A/D conversion result. (4) To obtain the final A/D conversion conversion, where DKth_M corresponds to the Kth A/D conversion result. (4) To obtain the final conversion, where DKth_M-bit corresponds to the Kth A/D conversion result. (4) To obtain the final ´bit result, D FIN_N-bit, the digital processing logic adds D1st_N-bit to the average value of DKth_M-bit’s. A/D conversion result, DN_N FIN_N-bit, the 1st_N-bit to the value of of A/D conversion result, DFI digitalprocessing processinglogic logicadds addsDD the average value ´bit , thedigital 1st_N ´bit to average DKth_M-bit ’s. DKth_M ’s. ´bit
Figure 3. Signal flow diagram of the proposed FMS method. Figure 3. Signal flow diagram of the proposed FMS method.
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Figure 4 shows the block diagram of the N-bit SAR ADC employing the proposed FMS method, Figure 4 shows the block diagram of the N-bit SAR ADC employing the proposed FMS method, without the use of an additional analog circuit for the N-bit D/A conversion in the second step and without the use of an additional analog circuit for the N-bit D/A conversion in the second step and lower M-bit conversion in the third step. The N-bit SAR ADC consists of an N-bit capacitor DAC, a lower M-bit conversion in the third step. The N-bit SAR ADC consists of an N-bit capacitor DAC, SAR logic, and a comparator. The reference voltages, +VREF, −VREF, and GND are used for the a SAR logic, and a comparator. The reference voltages, +VREF , ´VREF , and GND are used for the SAR ADC. SAR ADC.
Figure 4. Block diagram of the N-bit SAR ADC. Figure 4. Block diagram of the N-bit SAR ADC.
In the first step of the proposed FMS method, the N-bit capacitor DAC samples VIN by In thethe firsttop stepand of the proposed FMS method, the N-bit DACrespectively, samples V I N and by connecting connecting bottom plates of all capacitors to Vcapacitor IN and GND, then its the topVand of all capacitorscompares to V I N and GND, respectively, and then its output, VDAC , output, DAC, bottom became plates VIN. The comparator VDAC with GND to obtain the most significant N−1·CU, the comparator compares GND to2obtain most significant bit operation (MSB), and bitbecame (MSB),Vand the SAR logic connects theVlargest capacitor, to +V REF or −VREF. This I N . The DAC with SAR logic connects the significant largest capacitor, 2 N ´1is¨ Cobtained. or ´V . This operation is repeated isthe repeated until the least bit (LSB) Then, the capacitor, CU, is U , to +V REF REFsmallest until the least (LSB)the is obtained. Then, the smallest capacitor, to +VREF connected to +Vsignificant REF or −VREFbit . After first A/D conversion by the N-bit SARCADC, VDAC is expressed U , is connected as:or ´VREF . After the first A/D conversion by the N-bit SAR ADC, VDAC is expressed as: N V N ˆ ÿ VDAC VIN V1st _ NOISE D st _ N bit [i ] REF i VDAC “ VI N ` V1st_NOISE ´i 1 1D ris 1st_N ´bit 2ˆ
i“1
˙ V GND REF « GND 2i
(1)(1)
where D1st_N-bit[i] corresponding to the ith bit of the first A/D conversion result has a value of ”1” or where D bit [i] corresponding to the ith bit of the first A/D conversion result has a value of ”1” or “−1”, and 1st_N V1st_´ NOISE is an input-referred noise which includes the sampling and circuit noises at the “´1”, and V1st_NOISE is an input-referred noise which includes the sampling and circuit noises at the first A/D conversion. first A/D conversion. Figure 5a shows an example of the 4-bit capacitor DAC when D1st_N-bit is ”1001”. The capacitors, Figure 5a shows an example of the 4-bit capacitor DAC when D The capacitors, ´bit is ”1001”. 8·CU, 4·CU, 2·CU, and CU, are connected to −VREF, +VREF, +VREF, and −VREF1st_N , respectively, and VDAC, which 8¨ CU , 4¨ CU , 2¨ CU , and CU , are connected to ´VREF , +VREF , +VREF , and ´VREF , respectively, and is equal to VIN + V1st_NOISE − 3/16·VREF, converges to GND. In the second step, VIN is sampled again in V , which is equal to V I N + V1st_NOISE ´ 3/16¨ VREF , converges to GND. In the second step, V I N theDAC 4-bit capacitor DAC, and the capacitors, 8·CU, 4·CU, 2·CU, and CU, are connected to +VREF, −VREF, is sampled again in the 4-bit capacitor DAC, and the capacitors, 8¨ CU , 4¨ CU , 2¨ CU , and CU , are −VREF, and +VREF, respectively, as shown in Figure 5b, which are inversely connected as compared connected to +VREF , ´VREF , ´VREF , and +VREF , respectively, as shown in Figure 5b, which are with Figure 5a. Afterwards, all capacitors are connected to GND as shown in Figure 5c, and VDAC inversely connected as compared with Figure 5a. Afterwards, all capacitors are connected to GND becomes VIN + V2nd_NOISE − 3/16·VREF which is equal to VERR, where V2nd_NOISE is an input-referred noise as shown in Figure 5c, and V becomes V I N + V2nd_NOISE ´ 3/16¨ VREF which is equal to VERR , at the second A/D conversion. DAC From the second to Lth A/D conversions, the N-bit capacitor DAC where V2nd_NOISE is an input-referred noise at the second A/D conversion. From the second to Lth repeats the second step, and VDAC after the second step is expressed as: A/D conversions, the N-bit capacitor DAC repeats the second step, and VDAC after the second step is N V expressed as: VDAC VIN VKth _ NOISE D1st _ N bit [i ] REF VKth _ ERR (2) 2i i 1 ˆ ˙ N ÿ VREF D1st_N ˆ error VDACVKth “_VERR VKth_NOISE ´ “ VKth_ERR IN ` ´bit ris where VKth_NOISE and are the input-referred noise and voltage at the Kth A/D(2) 2i i “1 conversion, respectively. Using Equations (1) and (2), VKth_ERR can be simplified as:
where VKth_NOISE and VKth_ERR the input-referred noise and error voltage at the Kth A/D VKth _are (3) ERR GND V1st _ NOISE VKth _ NOISE conversion, respectively. Using Equations (1) and (2), VKth_ERR can be simplified as: VKth_ERR has a Gaussian distribution around GND − V1st_NOISE and its minimum and maximum VKth_ERR (3) voltages are determined by VKth_NOISE . « GND ´ V1st_NOISE ` VKth_NOISE VKth_ERR has a Gaussian distribution around GND ´ V1st_NOISE and its minimum and maximum voltages are determined by VKth_NOISE .
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(a)
(b)
(c) Figure 5. 5. Schematics the first first A/D A/D conversion Figure Schematics of of the the 4-bit 4-bit capacitor capacitor DAC DAC when when the conversion result result is is “1001”: “1001”: (a) when when converting converting the the 4-bit; 4-bit; (b) (b) when when sampling sampling V VIN, ,and (a) and(c) (c)when whenobtaining obtainingVVERR. . IN
ERR
In the third step, since the range of VKth_ERR is relatively small compared with that of VIN, In the third step, since the range of VKth_ERR is relatively small compared with that of V I N , VKth_ERR can be converted to a digital signal using only lower capacitors in the N-bit capacitor DAC. VKth_ERR can be converted to a digital signal using only lower capacitors in the N-bit capacitor DAC. After the N-bit SAR ADC converts VKth_ERR to the lower M-bit among the N-bit output, VDAC is After the N-bit SAR ADC converts VKth_ERR to the lower M-bit among the N-bit output, VDAC is expressed as: expressed as: ˙ MMˆ ÿ VREF VREF V D [ i ] GND (4) VDACV“ V ´ D ris ˆ « GND (4) DAC Kth_ERR Kth _ ERR Kth _ M ´ bit Kth_M bit 2 N2NM´iM`i i“1i 1
where DKth_M [i] corresponding to the of the A/D conversion result a value of ”1” Kth_M-bit´ [i] to the ith ith bit bit of the KthKth A/D conversion result hashas a value of ”1” or bitcorresponding or “´1”. From second Lth A/D conversions, SAR ADCrepeats repeatsthe thesecond secondand andthird third steps. steps. “−1”. From thethe second to to Lth A/D conversions, thethe SAR ADC After completing the total A/D conversion, the the analog analog voltage voltage corresponding corresponding to to an average value of A/D conversion, the lower M-bits, AVR[V(DKth_M )],expressed is expressed Kth_M-bit as: as: ´)], bitis ˙ L L 1L M Lˆ M 11 ř VV REF REF V DKthqs_ M“bit 1 ˆ ř ř D DKth _ M ris [ i ] VKth pV_Kth_ERR AVR rVAVR pDKth_M ˆ « ˆ ´ GNDq bit ERR GND N M i ´ bit Kth_M ´ bit L ´ 1 L k“12 i“k1 2 i 1 2 N2´ M`i LL ´11 k k2“2 L L ř L 1 1 L ř « ˆ 1 p´V V ` VKth_NOISE q « ´V1st_NOISE ` 1 ˆ V VKth_NOISE L ´ 1 k“2 1st_NOISE L ´ 1 k“Kth 1st _ NOISE VKth _ NOISE V1st _ NOISE 2 _ NOISE
L 1
k 2
L 1
(5) (5)
k 2
where 1) is is the the repeated repeated number number of of the the second second and and third third steps steps at at the the number number of of samplings samplings of of L. L. where (L (L ´ − 1) The final A/D conversion result, D , is obtained by adding D and the average value FI N_N,´is bitobtained by adding D1st_N-bit 1st_N ´bit The final A/D conversion result, DFIN_N-bit and the average value of the lower M-bits, while the analog voltage corresponding to DFIN_N-bit, V(DFIN_N-bit), can be expressed as:
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of the lower M-bits, while the analog voltage corresponding to DFI N_N ´bit , V(DFI N_N ´bit ), can be expressed as: N V ˙ V DFIN _ N bitN ˆ DFIN _ N bit [i ] REF i ř i 1 V2REF V pDFI N_N ´bit q “ DFI N_N ´bit ris ˆ N L2i M VREF VREF i “1 ˆ ˆ ˙ 1 L M ˙ D [ i ] (6) N 1st _ N bit VREF2i L1 1 ř ř DKth _ M bit [i] 2 N M i VREF ř i 1 k 2 i 1 “ D1st_N ´bit ris ˆ ` ˆ D ris ˆ (6) Kth_M ´ bit i L ´ 1 k “2 i “1 2 N ´ M `i L i “1 12 L VKth _ NOISE VIN GND1 ř Lˆ 1 kV « VI N ´ GND ` 2 L ´ 1 k“2 Kth_NOISE where DFIN_N-bit[i] corresponding to the ith bit of the final A/D conversion result has a value of ”1” or whereSince DFI N_N [i] corresponding ithFIN_N-bit bit of final A/D has a value of ´biteffect “−1”. the of VKth_NOISE to onthe V(D ) the decreases by conversion averaging Vresult Kth_NOISE, V(DFIN_N-bit) ”1” or “´1”. Since the effect of V on V(D ) decreases by averaging VKth_NOISE , Kth_NOISE FI N_N ´bit converges to VIN − GND as L increases. V(DFI N_N ´bit ) converges to V I N ´ GND as L increases. 3. Circuit Implementation 3. Circuit Implementation 3.1. Design of 12-bit SAR ADC Using the Proposed FMS Method 3.1. Design of 12-bit SAR ADC Using the Proposed FMS Method Figure 6 shows a schematic of the 12-bit SAR ADC which converts the PGA output, VPGA, to a Figure 6 shows a schematic of the 12-bit SAR ADC which converts the PGA output, VPGA , to a digital signal. The PGA in [2,3], which has gains of ×1, ×2, and ×4, is used for the developed CIS. To digital signal. The PGA in [2,3], which has gains of ˆ1, ˆ2, and ˆ4, is used for the developed CIS. To reduce the area, the SAR ADC uses a 10-bit capacitor DAC, which has a split capacitor structure with reduce the area, the SAR ADC uses a 10-bit capacitor DAC, which has a split capacitor structure with an attenuation capacitor, CATT, instead of a 12-bit capacitor DAC. To obtain the additional lower 2-bit, an attenuation capacitor, C ATT , instead of a 12-bit capacitor DAC. To obtain the additional lower 2-bit, four scaled reference voltages, +1/2·VREF, +1/4·VREF, −1/4·VREF, and −1/2·VREF, are used in the 10-bit four scaled reference voltages, +1/2¨ VREF , +1/4¨ VREF , ´1/4¨ VREF , and ´1/2¨ VREF , are used in the capacitor DAC. The reference voltages, +VREF, −VREF, and GND, are generated via an off-chip DAC, 10-bit capacitor DAC. The reference voltages, +VREF , ´VREF , and GND, are generated via an off-chip whereas the scaled reference voltages are generated by using an internal R-string. All reference DAC, whereas the scaled reference voltages are generated by using an internal R-string. All reference voltages are provided to the 12-bit SAR ADC via on-chip reference buffers. At the rising edge of the voltages are provided to the 12-bit SAR ADC via on-chip reference buffers. At the rising edge of the control signal, EN_CMP, the clocked comparator compares two outputs of the preamplifier which control signal, EN_CMP, the clocked comparator compares two outputs of the preamplifier which amplifies the difference between VDAC and GND. The SAR ADC converts VPGA to 12-bit at the first amplifies the difference between VDAC and GND. The SAR ADC converts VPGA to 12-bit at the first conversion, and then repeatedly converts VPGA to the lower 4-bit. 12 latches and four latches operate conversion, and then repeatedly converts VPGA to the lower 4-bit. 12 latches and four latches operate as SAR logic at the 12-bit and lower 4-bit conversions, respectively. The SAR logic sequentially stores as SAR logic at the 12-bit and lower 4-bit conversions, respectively. The SAR logic sequentially stores the output of the clocked comparator and selects the reference voltages connected to the capacitors the output of the clocked comparator and selects the reference voltages connected to the capacitors in in the 10-bit capacitor DAC. the 10-bit capacitor DAC.
Figure6. 6. Schematic Schematicof ofthe the12-bit 12-bitSAR SARADC. ADC. Figure
Figure Figure 77 shows shows the the maximum maximum switching switching energies energies of of the the capacitor capacitor DAC DAC according according to to the the bit bit conversion conversionstep stepof of the the 12-bit 12-bit conversion. conversion.Since Sincecharges chargesin inthe thecapacitor capacitorDAC DACare are provided providedfrom from the the reference the switching switchingenergy energydetermines determinesthe the settling time each bit conversion reference voltages, voltages, the settling time forfor each bit conversion stepstep [12], [12], and it is calculated using equations in [15]. When the capacitor DAC is reset and samples VPGA and it is calculated using equations in [15]. When the capacitor DAC is reset and samples VPGA , all the, all the capacitors are simultaneously charged toand VPGAthe and the largest switching is required in capacitors are simultaneously charged to VPGA largest switching energyenergy is required in the bit the bit conversion steps. The maximum switching energy decreases with an increase of the bit conversion steps. The maximum switching energy decreases with an increase of the bit conversion step conversion step with an exception of the second bit, sixth bit, and seventh bit conversion steps, due to the split capacitor structure. Considering the driving capability of the PGA and the decrease in switching energy, the 12-bit SAR ADC is designed to take 200 ns to sample VPGA, 100 ns to convert each upper 8-bit, 50 ns to convert each lower 4-bit, and 100 ns to obtain VKth_ERR. Therefore, each A/D
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with an exception of the second bit, sixth bit, and seventh bit conversion steps, due to the split capacitor the driving capability of the PGA and the decrease in switching energy, the 12-bit SAR ADC is designed to take 200 ns to sample VPGA , 100 ns to convert each upper 8-bit, 50 ns to conversion time becomes 1.2 μs for the first conversion, and then is reduced to 0.45 μs for the second convert each lower 4-bit, and 100 ns to obtain VKth_ERR . Therefore, each A/D conversion time becomes Sensors 2016,conversion. 16, 27 to seventeenth 1.2 µs for the first conversion, and then is reduced to 0.45 µs for the second to seventeenth conversion. Sensors 2016, 16, 27 structure. Considering
conversion time becomes 1.2 μs for the first conversion, and then is reduced to 0.45 μs for the second to seventeenth conversion.
Figure7.7.Normalized Normalizedmaximum maximumswitching switchingenergies energiesof ofthe thecapacitor capacitorDAC. DAC. Figure Figure 7. Normalized maximum switching energies of the capacitor DAC.
Figure showsthe thetheoretical theoretical normalized noise of SAR the SAR with the proposed FMS Figure 88 shows normalized noise of the ADCADC with the proposed FMS method method and conventional DCMS method, which repeats the same operations for each A/D Figure 8 shows the theoretical normalized noise of the SAR ADC with the proposed FMS and conventional DCMS method, which repeats the same operations for each A/D conversion, method and conventional DCMS method, which repeats the same operations for each A/D conversion, according the conversion total A/D conversion time. the of number of samplings L, the according to the total to A/D time. When theWhen number samplings is L, the is noise for conversion, according to method the total decreases A/D conversion time. When the number ofofsamplings is L, the to noise for the proposed FMS by one over the square root (L − 1), according the proposed FMS method decreases by one over the square root of (L ´ 1), according to Equation (6), noise(6), forand the proposed decreases by one over the square root ofby (L one − 1), over according to Equation theconventional noiseFMS for method theDCMS conventional DCMS method theHowever, square and the noise for the method decreases by onedecreases over the square root of L. Equation (6), and the noise for the conventional DCMS method decreases by one over the square root ofthe L. However, the number of samplings is 17, which is the maximum number for the when number of when samplings is number 17, which is the maximum number formaximum the developed CIS, root of L. However, when the of samplings is 17, which is the number for the the total developed CIS, the total A/D conversion time of the SAR ADC using the proposed FMS method is A/D developed conversion time theA/D SAR ADC using proposed FMS method is reduced 8.4 µsisfrom CIS, the of total conversion timethe of the SAR ADC using the proposed FMS to method reduced to 8.4toμs from μs, which isusing that SAR using themethod. conventional DCMS method. 19.2 µs, which is8.4that of19.2 the19.2 SAR ADC the conventional DCMS reduced μs from μs, which is thatof ofthe the SAR ADC ADC using the conventional DCMS method.
Figure 8. Theoreticalnormalized normalized noise ADC output. Figure 8. Theoretical noiseof ofthe theSAR SAR ADC output. Figure 8. Theoretical normalized noise of the SAR ADC output. 3.2. Design of Digital Processing Logic
3.2. Design of Digital Processing Logic 3.2. DesignFigure of Digital Processing Logic 9 shows the block diagram of the proposed up/down counter-based digital processing Figure 9 shows the block ofthe theproposed proposed up/down counter-based digital processing logic for the 12-bit SAR ADCdiagram employing FMS method. The proposed digital processing Figure 9 shows the block diagram of the proposed up/down counter-based digital processing logic logic for the 12-bitof SAR ADC employing the proposed FMS proposed digital processing consists a digital-to-pulse converter (DPC) and 17 method. unit cells The for the maximum number of logic for the 12-bit SAR ADC employing the proposed FMS method. The proposed digital processing of a17,digital-to-pulse of which each unit cell consists of a T-F/F andunit 3-input Themaximum T-F/F outputnumber or its of logic samplings consists of converter (DPC) and 17 cellsMUX. for the logic consists of a digital-to-pulse converter (DPC) andto17the unit cells forthough the maximum number of inverting output, Q or each Qb, respectively, is transferred next T-F/F samplings of 17, of which unit cell consists of a T-F/F and 3-input MUX. the The3-input T-F/F MUX output or samplings of 17, of which each unit cell consists of a T-F/F and 3-input MUX. The T-F/F output its according to the control signal, UP. The DPC, which consists of a 2-input MUX, selects a signal, GNDor its inverting output, Q or Qb, respectively, is transferred to the next T-F/F though the 3-input MUX inverting output, Q or Qb, respectively, transferred to the next T-F/F DPC_OUT, though theis 3-input MUX or PULSE, to the comparator is output, CMP_OUT, output, applied to according to theaccording control signal, UP. The DPC, which consistsand of aits2-input MUX, selects a signal, GND one of through 3-input MUXwhich selected by the control signal,MUX, SEL. The control signal,GND according tothe theT-F/Fs control signal,the UP. The DPC, consists of a 2-input selects a signal, or PULSE, according to the comparator output, CMP_OUT, and its output, DPC_OUT, is applied to EN_T,according becomes low to maintain the output of the T-F/F whenand the control signal, UP or SEL,is changes. or PULSE, to the comparator output, CMP_OUT, its output, DPC_OUT, applied to one of the T-F/Fs through thesubtracts 3-input the MUX selected by result the control signal, SEL. Thefrom control signal, The digital processing logic A/D conversion of the PGA reset voltage thatsignal, of one of the T-F/Fs through the 3-input MUX selected by the control signal, SEL. The control EN_T,the becomes low to maintain the output of the T-F/F when the control signal, UP or SEL, changes. amplified signal voltage, and the CIS uses uppersignal, 13-bit, UP from OUT[16] to EN_T, becomes lowpixel to maintain the output of developed the T-F/F when thethe control orDSEL, changes. DOUT[5], among the 17-bit outputs of the digital processing logic for displaying the captured image. The digital processing logic subtracts the A/D conversion result of the PGA reset voltage from that of The MSB generated via subtraction is used as a sign bit. the amplified pixel signal voltage, and the developed CIS uses the upper 13-bit, from DOUT[16] to DOUT[5], among the 17-bit outputs of the digital processing logic for displaying the captured image. The MSB generated via subtraction is used as a sign bit.
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The digital processing logic subtracts the A/D conversion result of the PGA reset voltage from that of the amplified pixel signal voltage, and the developed CIS uses the upper 13-bit, from DOUT [16] to DOUT [5], among the 17-bit outputs of the digital processing logic for displaying the captured image. Sensors 2016, 16, 27 The MSB generated via subtraction is used as a sign bit. Sensors 2016, 16, 27
Figure 9. 9.Block ofthe thedigital digital processing Figure Blockdiagram diagram of processing logic.logic. Figure 10 shows the timing diagram of the digital processing logic. Before converting the PGA
Figure 10 shows the timing diagram of theofdigital processing logic. logic. Before converting the PGA diagramsignal, the digital reset voltage, all T-F/Fs areFigure reset 9. byBlock the control RST, processing and the digital processing logic acts as a reset voltage, all T-F/Fs are reset by the control signal, RST, and the processing logic down counter by setting the control signal, UP, to low. At the first A/Ddigital conversion, the 12-bit SARacts as a Figure 10 shows the timing diagram of the digital processing logic. Before converting the PGA down ADC counter by setting the control UP, toDlow. Atfrom the the firstMSB A/D conversion, the 12-bit SAR converts the PGA reset voltagesignal, to 12-bit, and CMP_OUT to the LSB is sequentially reset voltage, allDPC. T-F/Fs are reset bytothe signal, RST, andfrom the digital processing as a provided to the When DCMP_OUT is control low or high, DPC_OUT keeps or MSB toggles output the ADC converts the PGA reset voltage 12-bit, and DCMP_OUT the to the thelogic LSBacts isofsequentially down counter by setting the control signal, UP, to low. At the first A/D conversion, the 12-bit SAR T-F/F, starting from DOUTis [15] to or DOUT [4] sequentially. OUT becomes two’s of the provided to respectively, the DPC. When DCMP_OUT low high, DPC_OUTTherefore, keeps orDtoggles the output ADC converts reset voltage to 12-bit, DCMP_OUT fromtothe MSB to theA/D LSBconversion, is sequentially complement of the the PGA first A/D conversion result. and From the second seventeenth the T-F/F, respectively, fromDD to or DOUT [4] sequentially. Therefore, Doutput OUT [15] OUT becomes provided thestarting DPC. When CMP_OUT is low high, DPC_OUT keeps orDPC_OUT toggles the of the two’s 12-bit SARtoADC converts the PGA reset voltage to the lower 4-bit, and is sequentially complement of the first starting A/D conversion result. From the second to seventeenth A/Dtwo’s conversion, T-F/F, respectively, DOUT[15] toT-F/F, DOUT [4] sequentially. Therefore, DOUT4-bit. becomes provided from the fourteenthfrom to seventeenth which corresponds to the lower Therefore, complement the first A/D conversion result. From thethe second A/D conversion, the the 12-bit SAR ADC converts the PGA voltage to lower 4-bit, and DPC_OUT is sequentially the lower 4-bitofconversion results are reset repeatedly subtracted fromtoDseventeenth OUT 16 times, and then averaged 12-bit SAR ADC converts the PGA reset voltage the[4], lower 4-bit,aand is sequentially provided from the fourteenth to seventeenth T-F/F, which corresponds to the lower 4-bit. by 16. Therefore, the upper 13-bit, from DOUT [16] toto DOUT becomes finalDPC_OUT A/D conversion resultTherefore, of provided fromvoltage. the fourteenth seventeenth which corresponds to the lower 4-bit. Therefore, the PGA Afterwards, the 12-bit T-F/F, SARsubtracted ADC converts theDamplified pixel signal voltage the lower 4-bitreset conversion resultstoare repeatedly from 16 times, and then averaged OUT the lowerThe 4-bit conversion results are repeatedly subtracted from conversion DOUT 16 times, and then averaged to 12-bit. same operations as those in the PGA reset voltage are repeated, with the by 16. Therefore, the upper 13-bit, from DOUT [16] to DOUT [4], becomes a final A/D conversion result by 16. Therefore, upper 13-bit, from DOUTwhich [16] to acts DOUT[4], becomes a final A/D conversion of exception ofvoltage. the the digital processing logic, as an up counter by setting UP result tosignal high. of the PGA reset Afterwards, the 12-bitSAR SAR ADC converts the amplified pixel the PGA reset voltage. Afterwards, the 12-bit ADC converts the amplified pixel signal voltage voltage Therefore, the upper 13-bit becomes the difference between the A/D conversion results of the PGA to 12-bit. The same operations asas those resetvoltage voltage conversion are repeated, to 12-bit. The same operations thosein inthe the PGA PGA reset conversion are repeated, with thewith the reset voltage and the amplified pixel signal voltage. exception of the digital processing which an counter up counter by setting to high. exception of the digital processing logic,logic, which acts acts as anasup by setting UPUP to high. Therefore, Therefore, the upper 13-bit becomes the difference the A/D conversion results of the reset PGA voltage the upper 13-bit becomes the difference between thebetween A/D conversion results of the PGA reset voltage and the amplified pixel signal voltage. and the amplified pixel signal voltage.
Figure 10. Timing diagram of the digital processing logic.
Figure Timingdiagram diagram of processing logic.logic. Figure 10.10. Timing ofthe thedigital digital processing
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The proposed up/down counter-based digital processing logic uses a T-F/F and 3-input MUX The digital processing logic uses a T-F/F andcompared 3-input MUX per unit proposed cell. As a up/down result, the counter-based number of transistors per unit cell is reduced by 29% with per unit cell. As a result, the number of transistors per unit cell is reduced by 29% compared with that of the SAR ADC described in [3]. Moreover, the proposed digital processing logic is that also of the SAR ADC [3]. ADC Moreover, digitalalgorithm processinginlogic applicable applicable to thedescribed multi-bit in cyclic with the the proposed error correction [18] is byalso controlling the to the multi-bit cyclic ADC with the error correction algorithm in [18] by controlling the number of number of output pulses from the DPC without the use of additional circuits in the unit cell. The output pulses from the DPC without the use of additional circuits in the unit cell. The multi-bit cyclic multi-bit cyclic ADC sequentially generates the multi-bit per clock cycle to compensate for the ADC sequentially comparator offset.generates the multi-bit per clock cycle to compensate for the comparator offset.
4. Experimental Results 4. Experimental Results The proposed FMS method is verified using a 256 ˆ 128 pixel array CIS with column-parallel The proposed FMS method is verified using a 256 × 128 pixel array CIS with column-parallel 12-bit SAR ADCs. Figure 11 shows the chip photomicrograph and readout channel layout of the 12-bit SAR ADCs. Figure 11 shows the chip photomicrograph and readout channel layout of the developed CIS which is fabricated using a 0.18 µm 1-poly 4-metal CMOS process. The developed CIS developed CIS which is fabricated using a 0.18 μm 1-poly 4-metal CMOS process. The developed occupies an area of 2.35 mm ˆ 2.35 mm. CIS occupies an area of 2.35 mm × 2.35 mm.
Figure11. 11.Photomicrograph Photomicrographand andreadout readoutchannel channellayout layoutofofthe thedeveloped developedCIS. CIS. Figure
The developed CIS uses supply voltages of 2.8 V for the pixel array, analog circuit, and 1.8 V for The developed CIS uses supply voltages of 2.8 V for the pixel array, analog circuit, and 1.8 V digital circuit. The total power consumption excluding PAD power is obtained from post layout for digital circuit. The total power consumption excluding PAD power is obtained from post layout simulation results under the operating conditions at the number of sampling of 17 and 90 frames/s. It simulation results under the operating conditions at the number of sampling of 17 and 90 frames/s. It has 4.4 mW which includes the power consumptions of the pixel array of 0.79 mW, reference and has 4.4 mW which includes the power consumptions of the pixel array of 0.79 mW, reference and bias bias circuits of 1.14 mW, and readout channel array of 2.3 mW. In a readout channel, the PGA, SAR circuits of 1.14 mW, and readout channel array of 2.3 mW. In a readout channel, the PGA, SAR ADC, ADC, and digital processing logic consume 20.6 μW, 11.3 μW, and 4.3 μW, respectively. and digital processing logic consume 20.6 µW, 11.3 µW, and 4.3 µW, respectively. Figure 12 shows the measured sensor output signal and random noise of the developed CIS Figure 12 shows the measured sensor output signal and random noise of the developed CIS according to light intensity, which is obtained from the average and standard deviation values of according to light intensity, which is obtained from the average and standard deviation values of 100 images, respectively, at a PGA gain of ×1 and the number of samplings of 17. The output signal 100 images, respectively, at a PGA gain of ˆ1 and the number of samplings of 17. The output signal and random noise increases linearly according to the light intensity. However, the nonlinearity of and random noise increases linearly according to the light intensity. However, the nonlinearity of the the conversion capacitor and source follower in the pixel causes the non-linear behavior [3,19]. The conversion capacitor and source follower in the pixel causes the non-linear behavior [3,19]. The light light sensitivity obtained from the slope of the output signal is 6.2 V/lx·s. Random noise has a sensitivity obtained from the slope of the output signal is 6.2 V/lx¨ s. Random noise has a minimum minimum value of 1.2 LSB (270.4 μV) in near-dark condition, where flickers and thermal noises of value of 1.2 LSB (270.4 µV) in near-dark condition, where flickers and thermal noises of the pixel and the pixel and readout circuits are the dominant sources of noise. As the light intensity increases, readout circuits are the dominant sources of noise. As the light intensity increases, random noise random noise increases due to photon shot noise. At a light intensity of 40 lx, the measured output increases due to photon shot noise. At a light intensity of 40 lx, the measured output signal and random signal and random noise have 3110 LSB and a maximum value of 34 LSB, respectively. An output noise have 3110 LSB and a maximum value of 34 LSB, respectively. An output signal of 3110 LSB signal of 3110 LSB corresponds to the full well capacity of 11.4 ke − with a conversion gain of corresponds to the full well capacity of 11.4 ke´ with a conversion gain of 60 µV/e´ [19]. The dynamic 60 μV/e− [19]. The dynamic range obtained from the ratio of the full well capacity to the minimum
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range obtained from the ratio of the full well capacity to the minimum random noise measured in Sensors 2016, 16, 27 random noise measured in near-dark conditions is 68.1 The obtained signal-to-noise ratio (SNR) obtained near-dark conditions is 68.1 dB. The signal-to-noise ratiodB. (SNR) from the ratio of the output from the ratio of the output signal to random noise is 39.2 dB at a light intensity of 40 lx. signal to random noise is 39.2 dB at a light intensity of 40 lx. random noise measured in near-dark conditions is 68.1 dB. The signal-to-noise ratio (SNR) obtained from the ratio of the output signal to random noise is 39.2 dB at a light intensity of 40 lx.
Figure Figure12. 12.Measured Measuredoutput outputsignal signaland andrandom randomnoise noiseaccording accordingto tolight lightintensity. intensity. Figure 12. Measured output signal and random noise according to light intensity.
Figure 13 shows thethe measured differential non-linearity(DNL) (DNL)and andintegral integral non-linearity (INL) Figure shows measureddifferential differential non-linearity non-linearity (INL) Figure 1313 shows the measured non-linearity (DNL) and integral non-linearity (INL) of the 12-bit SAR ADC for the developed CIS. The measurement results of the DNL and INL are of the 12-bit SAR ADC for the developed CIS. The measurement results of the DNL and INL are of the 12-bit SAR ADC for the developed CIS. The measurement results of the DNL and INL are −0.62/+1.37 LSBLSB and −1.42/+3.55 respectively. Since codesaturations saturationsare are caused the parasitic −0.62/+1.37 and −1.42/+3.55LSB, LSB, code caused byby the parasitic ´0.62/+1.37 LSB and ´1.42/+3.55 LSB,respectively. respectively.Since Since code saturations are caused by the parasitic capacitors connected to upper capacitors in the capacitor DAC, the peaks of the DNL and capacitors connected to upper capacitors in the capacitor DAC, the peaks of the DNL and INLINL capacitors connected to upper capacitors in the capacitor DAC, the peaks of the DNL and INL repeatedly occur. In addition, a mismatch of C ATT repeatedly causes peaks of DNL and INL in each repeatedly occur. In addition, a mismatch of CATT repeatedly causes peaks of DNL and INL in each repeatedly occur. In addition, a mismatch of C ATT repeatedly causes peaks of DNL and INL in each 128 128 LSBLSB over thethe fullfull code range. not affected affectedby bythe theINL INL ADC, over code range.Linearity Linearityof of the the CIS is not of of thethe ADC, butbut are are 128 LSB over the full code range. Linearity of the CIS is not affected by the INL of the ADC, but are determined photon shotnoise noiseand andphoto photo conversion conversion nonlinearity addition, thethe error of of determined by by thethe photon shot nonlinearity[3]. [3].InIn addition, error determined by the photon shot noise and photo conversion nonlinearity [3]. In addition, the error of V ERR is not occurred due to capacitance mismatch of the capacitor DAC since the D/A conversion VERR is not occurred due to capacitance mismatch of the capacitor DAC since the D/A conversion VERR is not occurred due to capacitance mismatch of the capacitor DAC since voltage the D/Atoconversion error error of the capacitorDAC DACisiscancelled cancelled out out while while converting D1st_Nbit andand error of the capacitor converting the theinput input voltage to D1st_Nbit of the capacitor DAC is cancelled out while converting the input voltage to D and generating generating VERR from D1st_N-bit . However, since since the the asymmetry asymmetry of REF and −V1st_Nbit REF causes an offset generating VERR from D1st_N-bit . However, of+V +V REF and −VREF causes an offset VERR from D . However, since the asymmetry of +V and ´V causes an offset error in REF REF 1st_N ´ bit error , the A/D conversionrange range for for the the lower lower 4-bit bebe wider than the the error in VinERRV,ERR the A/D conversion 4-bit conversion conversionshould should wider than VERR , the A/D conversion range for the lower 4-bit conversion should be wider than the offset error. offset error. offset error.
(a)
(a)
(b) Figure13. 13.Measured Measured (a) (a) DNL ADC. Figure DNL and and(b) (b)INL INLofofthe theSAR SAR ADC.
(b)
Figure 13. Measured (a) DNL and (b) INL of the SAR ADC.
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Figure 14 14 shows shows the the measured measured and and theoretical theoretical input input referred referred noises noises according according to to the the number number of of Figure samplings and PGA gain at the same exposure time. As the number of samplings increased from samplings and PGA gain at the same exposure time. As the number of samplings increased from 11 Figure 14 shows the measured and theoretical input referred noises according to the number of to 17, 17, the the input input referred referred noise noise decreases decreases from from 848.3 848.3 μV μV to to 270.4 270.4 μV, μV, 449.2 449.2 μV μV to to 155.8 155.8 μV, μV, and and 255 255 to samplings and PGA gain at the same exposure time. As the number of samplings increased from 1 to μV to to 96.5 96.5 μV, μV, for for aa PGA PGA gain gain of of ×1, ×1, ×2, ×2, and and ×4, ×4, respectively. respectively. V VKth_ERR Kth_ERR,, which which is is the the sum sum of of input input μV 17, the input referred noise decreases from 848.3 µV to 270.4 µV, 449.2 µV to 155.8 µV, and 255 µV to referred noises at the 1st and Kth conversions, is repeatedly converted to lower 4-bit after 1st A/D referred noises at the 1st and Kth conversions, is repeatedly converted to lower 4-bit after 1st A/D 96.5 µV, for a PGA gain of ˆ1, ˆ2, and ˆ4, respectively. VKth_ERR , which is the sum of input referred conversion. conversion. noises at the 1st and Kth conversions, is repeatedly converted to lower 4-bit after 1st A/D conversion.
Figure 14. Measured and theoretical theoretical input input referred referred noise. noise. Figure Figure 14. 14. Measured Measured and
Therefore, lower lower 4-bit 4-bit for the the fast conversion conversion is is derived derived by by considering considering aa measured measured input input Therefore, Therefore, lower 4-bit forfor the fastfast conversion is derived by considering a measured input referred referred noise of 848.3 μV, which corresponds to 3.9 LSB, at the number of samplings of 1 and referred noise µV, of 848.3 μV, which corresponds toat3.9 LSB, at theofnumber of samplings 1 and aa noise of 848.3 which corresponds to 3.9 LSB, the number samplings of 1 and a of PGA gain PGA gain of of ×1. ×1. Theoretically, Theoretically, for for the the number number of of samplings samplings of of L, L, the the input input referred referred noise noise should should be be PGA of ˆ1.gain Theoretically, for the number of samplings of L, the input referred noise should be decreased decreased by by one one over over the the square square root root of of (L (L −− 1), 1), but but the the measured measured input input referred referred noise noise is is greater greater decreased by one over the square root of (L ´ 1), but the measured input referred noise is greater than the than the the theoretical theoretical noise noise due to to the the linearity linearity error error of of the lower lower 4-bit 4-bit conversion conversion of of the the SAR SAR ADC. ADC. than theoretical noise due to thedue linearity error of the lower the 4-bit conversion of the SAR ADC. The lower The lower 4-bit 4-bit conversion results results after after the the first first conversion conversion exhibits exhibits a Gaussian Gaussian distribution distribution due due to to The 4-bitlower conversionconversion results after the first conversion exhibits a Gaussiana distribution due to temporal temporal noise, but linearity error distorts the distribution. In addition, the measured input referred temporal but linearity error the distorts the distribution. In addition, the measured referred noise, butnoise, linearity error distorts distribution. In addition, the measured input input referred noise noise proportionally proportionally decreases decreases according according to to the the PGA PGA gain gain because, because, for for the the input input referred referred noise, noise, the the noise proportionally decreases according to the PGA gain because, for the input referred noise, the noise noise caused by by the the readout readout circuit circuit is is dominant dominant compared compared with with what what is is caused caused by by the the pixel pixel circuit circuit noise causedcaused by the readout circuit is dominant compared with what is caused by the pixel circuit [1]. The [1]. The developed CIS achieves the lowest input referred noise of 96.5 μV at the number of [1]. The developed CIS achieves the lowest input referred noise of 96.5 μV at the number of developed CIS achieves the lowest input referred noise of 96.5 µV at the number of samplings of 17 samplings of 17 17 and aa PGA PGA gain gain of of ×4. ×4. samplings and a PGAof gain and of ˆ4. Figure 15 15 shows shows the the captured captured image image of the the developed developed CIS CIS at at the number number of of samplings samplings of of 17 17 Figure Figure 15 shows the captured image ofofthe developed CIS at thethe number of samplings of 17 and and a PGA gain of ×1. The captured image exhibits a 12-bit resolution, but it is difficult to evaluate and a PGA of The ×1. The captured image exhibits a 12-bit resolution, is difficult to evaluate a PGA gaingain of ˆ1. captured image exhibits a 12-bit resolution, but but it isitdifficult to evaluate the the noise noise performance performance of of the the CIS CIS with with the the naked naked eye eye because because the the monitor monitor system system generally generally features features the noise performance of the CIS with the naked eye because the monitor system generally features an an 8-bit 8-bit resolution. resolution. To solve solve the above above problem, problem, images images are are captured captured in short short exposure exposure time time and and are are an 8-bit resolution. ToTo solve thethe above problem, images are captured ininshort exposure time and are displayed by using the lower 5-bits among the 12-bit CIS outputs, corresponding to a digital gain of displayed corresponding to to a digital gain of displayed by by using usingthe thelower lower5-bits 5-bitsamong amongthe the12-bit 12-bitCIS CISoutputs, outputs, corresponding a digital gain ×128. Figure Figure 16a 16a and and Figure Figure 16b 16b show the the captured images images for for the the following following number number of of samplings, samplings, ×128. of ˆ128. Figure 16a,b shows the show captured captured images for the following number of samplings, 1 and 17, 1 and 17, respectively, at a PGA gain of ×1, in which Figure 16b has less noise than Figure 16a. 1respectively, and 17, respectively, at a PGA gain of ×1, in which Figure 16b has less noise than Figure 16a. at a PGA gain of ˆ1, in which Figure 16b has less noise than Figure 16a.
Figure 15. 15. Captured Captured 12-bit 12-bit image image at at the the number number of of samplings samplings of of 17. 17. Figure
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(a)
(b) Figure 16. Captured lower 5-bit images in short exposure time for the following number of
Figure 16. Captured lower 5-bit images in short exposure time for the following number of samplings: samplings: (a) 1 and (b) 17. (a) 1 and (b) 17.
The performance of the developed CIS is summarized in Table 1 and compared with prior CISs The performance of the CIS is2.summarized Table representing 1 and compared using column-parallel SARdeveloped ADCs in Table The figure ofinmerit, noisewith and prior energyCISs using column-parallel SAR efficiency, was defined as: ADCs in Table 2. The figure of merit, representing noise and energy
efficiency, was defined as:
Power Noise FOM Power ˆ Noise FOM “ Pixel _ rate
Pixel_rate
(7)
(7)
where Pixel_rate a product of the total number pixels andthe theframe framerate. rate.The TheCIS CISemploying employing the where Pixel_rate is aisproduct of the total number ofof pixels and the proposed FMS method achieves the best FOM of 145 μV· nJ by simultaneously reducing total proposed FMS method achieves the best FOM of 145 µV¨ nJ by simultaneously reducing thethe total A/D A/D conversion time and random noise. conversion time and random noise. Table1.1.Performance Performance summary. Table summary.
Parameter Parameter Process Process Supply voltage Supply voltage Chip size Pixel array array size Pixel size Maximum frame rate Maximum Pixel frame size rate Conversion Pixel sizegain Full well capacity Conversion gain Sensitivity Full well capacity Column FPN at dark SNR Sensitivity Dynamic range Column FPN range at dark ADC input ADC SNR resolution DNL Dynamic range INL Power consumption
Value Value 0.18 μm 1-poly 4-metal CMOS process 0.18 µm 1-poly 4-metal CMOS process 2.8 V/1.8 V 2.8 V/1.8 V 2.35×mm 2.35 mm 2.35 mm 2.35ˆmm 256×(H) 128 (V) 256 (H) 128ˆ(V) 90 frames/s 90 frames/s 4.4 µm ˆ 4.4 µm ´ 4.4 μm ×60 4.4µV/e μm ´ 11.4 ke 60 μV/e− 6.2 V/lx¨ s − 11.4 ke 0.17 LSB 39.2 6.2 V/lx·s dB 68.1 dB 0.17 LSB 0.9 V 39.2 dB12-bit ´0.62/+1.37 LSB 68.1 dB ´1.42/+3.55 LSB 4.4 mW
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Table 2. Comparison with prior CISs with column-parallel SAR ADCs. Parameter
This Work
[3]
[12]
[13]
[14]
[20]
[21]
Pixel array size Frame rate (frame/s) ADC Resolution (bit) Random noise (µVrms ) Power consumption (mW) FOM (µV¨ nJ)
256 ˆ 128
4112 ˆ 2186
1280 ˆ 800
920 ˆ 256
644 ˆ 488
54 ˆ 50
64 ˆ 45
90
60
35
9
120
7.4
21.2
12
14
11
9
14
10
8
96.5 (0.44 LSB)
130.5
1500
5300
83
0.98 LSB
0.5 LSB
4.4
108.5
40
1.1
78
0.014
0.021
145
265
1674
28147
171
-
-
5. Conclusions In this paper, a fast multiple sampling method for CISs with column-parallel 12-bit SAR ADCs is proposed. The SAR ADC repeatedly converts a pixel output to 4-bit after the first 12-bit A/D conversion. As a result, each A/D conversion time after the first A/D conversion is reduced to 37.5% of the first A/D conversion time, and the total A/D conversion time at the number of samplings of 17 is reduced to 44% of that of the SAR ADC using conventional DCMS method. The 12-bit SAR ADC uses a 10-bit capacitor DAC with an attenuation capacitor and four scaled reference voltages to reduce the area. A simple up/down counter-based digital processing logic, consisting of a 3-input MUX and T-F/F is proposed to perform complex calculations for multiple sampling and DCDS. The measurement results shows that random noise decreases from 848.3 µV to 270.4 µV by using the proposed multiple sampling method, and the best FOM of 145 µV¨ nJ is achieved. Therefore, the proposed multiple sampling method is suitable for low-noise, high-frame rate CISs with column-parallel SAR ADCs. Acknowledgments: This research was supported by the Industrial and Educational Cooperative R&D Program between Hanyang University and SK Hynix Semiconductor Inc. The authors would like to thank Jaseung Gou and Sang-Dong Yoo of SK Hynix Semi-conductor Inc. for their useful discussion and feedback. Author Contributions: M.-K.K. and O.-K.K. proposed the idea and designed the circuits; S.-K.H. verified the circuits; M.-K.K. performed the experiments; S.-K.H. and O.-K.K. verified the experiments; M.-K.K. and S.-K.H. wrote the paper. Conflicts of Interest: The authors declare no conflict of interest.
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