A Greedy Algorithm for Low Cost LNN Reversible Circuit Realization Mohammad AlFailakawi & Imtiaz Ahmad
Laila Al-Terkawi
Computer Engineering Department College of Computing Sciences & Engineering Kuwait University Email:
[email protected]
Accounting and Management Information Systems Department College of Business Administration Gulf University of Science and Technology State of Kuwait
Abstract—Physical adjacency is a typical constraint for quantum circuit realization in technologies such as liquid state Nuclear Magnetic Resonance (NMR) and simple trapped-ions. This restriction requires circuit realization to only Linear Nearest Neighbor (LNN) architectures which results in increased cost due to the introduction of additional gates to ensure adjacency. In this work, we present an input line ordering algorithm to reduce the overall quantum cost of circuits to be realized in LNN architecture. Experimental results shows that the proposed algorithm improves the cost of the reordered benchmark circuits by 29% on average compared to their unordered counterparts.
I.
I NTRODUCTION
The interest in quantum computing is growing in exponential rate in recent years for many reasons such as performance and low power operation. It was demonstrated that quantum computers outperform classical one on a set of problems such as number factoring, database search, and triangle counting in graph algorithms [1], [2], [3]. Moreover, shrinking transistor sizes and high power dissipation are some of the most important bottlenecks in the development of smaller and more powerful circuits for todays computer chips. A key feature of the quantum computation model is reversibility [4]. Reversible circuits are circuits that have one-to-one mapping between their input and output and thus do not lose information during computation. Unlike traditional computation that operate on bits, quantum computation operate on quantum bits, or qubits. Therefore, qubits is the unit used to represent quantum information but unlike traditional bits which allow only 0 and 1 state, qubits can be in any superposition of such states. Synthesis for reversible circuits is the first step towards the synthesis of quantum circuits and many have been introduced in recently [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]. Some of the algorithms proposed were optimal for the synthesis of reversible circuits [5], [7], [8], [9], however, due the intractability of the problem, only circuits with small number of inputs can be handled by such methods. Therefore, for circuits with large number of inputs, heuristic methods are preferred over their optimal counterparts which can be found in [6], [20], [21]. Physical realizations of quantum gates require interacting qubit(s) to be physically adjacent [22], [12], which is called Linear Nearest Neighbor configuration. It is common to use a pair of SWAP gates to bring distant interacting qubits of any quantum gate to adjacent lines and maintain correct
circuit functionality. Over the past few years, efficient LNN implementations have been reported for a wide range of applications [23], [24], [25], [26]. It has been shown that if a quantum circuit can be realized efficiently using an LNN architecture, it can be implemented in other architectures as well [12], [27]. Therefore, LNN architecture is often considered a good approximation to scalable quantum architecture. Several heuristic methods for converting a quantum circuit to its equivalent LNN architecture have been proposed in literature [27], [28], [29], [30], [31], [32], [33], [19], [34], [35], [36]. In this paper the focus is on the post-synthesis optimization of reversible circuits in LNN configuration. The proposed algorithm is a greedy algorithm that will finds input line ordering that will reduce the number of SWAP gates needed to reduce overall quantum circuit cost. Experimental results comparing the quantum cost of benchmark circuits before and after line ordering were observed to reduce the overall cost by 29% on average. The remainder of the paper is organized as follows. In Section II, we present a brief overview of reversible circuits and quantum cost. The proposed algorithms as well as the formulation of the cost function use are discussed in Section III. Experimental results on benchmark circuits are presented in Section IV and the conclusion are highlighted in Section V. II.
R EVERSIBLE C IRCUITS & Q UANTUM C OST
A reversible circuits is a circuit that have the same number of inputs and outputs with no feedback loops or fan-out. Reversible circuits consists of a cascade of reversible gates and it is common to use quantum gates for this purpose due to their inherit reversibility. Some of the most commonly used quantum gates are given in Figure 1. The NOT gate performs the conventional NOT operation which results in inverting the value of the input qubit. As for CNOT gate, it consists of one control qubit, denoted by (•), and one target qubit, denoted by (⊕). The target qubit in such gate is inverted if the control qubit is set, otherwise, it is left un-altered. As for controlled V and V+ , these gate perform the square root of NOT and its inverse, respectively. This set is known as the NCV library and can be efficiently implemented in quantum technologies such as NMR [37] and is considered as the primitive (i.e. elementary) gate set for all reversible boolean functions. It is unlikely to find circuits that realize classical functions implemented using elementary quantum gates; rather, more
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Fig. 1.
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(a) Graphical Representation Fig. 5.
Elementary Quantum Gates
During design synthesis, it is common to take into account the constraints posed by the targeted implementation technology. There are different constraints that need to be addressed for different technologies and synthesis tools take a leading role to conform designs to such constraints. Moreover, synthesis tools also optimize circuit realization using appropriate technology-relevant cost metrics. One of the most widely used cost metrics when realizing circuits is cost, and in the case of reversible circuit it is known as quantum cost. Quantum cost refers to the number of elementary gates needed to implement the design. In this work, the gates in the NCV gate library constitute the universe of elementary gates used to calculate the cost, nonetheless, for different technology other elementary gates can be used as well [6]. This distinction is important since using different gate library may result in different quantum cost for the same circuit. For example, the Toffoli gate needs five gates when realized using NCV library (two CNOT, two controlled-V, and one controlled-V+ gates) whereas it needs six CNOTs and several one-qubit gates when the universal set of one-qubit and CNOT gates [38]. •
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b c Fig. 2.
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SWAP Gate
as shown in Figure 3 with gives a quantum cost of 14.
complex multi-qubit gates are used. One of the most commonly multi-qubit gate that can implement any reversible function, thus a universal gate, is the multi-control toffoli gate (MCT). This gate, referred to as tm or Cm NOT, has the form tm (C, t) where CT= {xi1 , ..., xim } is the set of control lines and t = xj with C t = φ is the target line. In such gate, the target line value is inverted if and only if all control lines are equal to 1. For m=2,1, and 0, the gates are known as Toffoli, CNOT, and CNOT gates respectively.
a
• • (b) Circuit Realization
a •
For example, the swap gate, which is a type of Fredkin gate, can be implemented using CNOT gates as shown in Figure 5. This quantum circuit is drawn in a similar fashion as any classical logic circuit, read from left to right where wires in the figure represent passage of time or the movement of a particle (such as a photon) from one location to another. This circuit results in exchanging the input qubits with each other, hence referred to as a “SWAP” gate. The SWAP gate requires three elementary gates hence its cost is 3 (i.e. referred to as quantum cost). In recent years, the interest in linear nearest neighbor architecture of quantum circuits has been exploding. This interest stems from the fact that many of quantum technologies require both the control and target qubits of a given gate to be in close proximity to allow proper interaction. In technologies where such restriction exists, it is customary to include SWAP gates to bring both control and target gate close together. Adding such gates increases the cost of the overall implementation of the circuit. For example, consider the circuit shown in Figure 2 that has a cost of 14. When using a technology that requires nearest neighbor, SWAP gates must be introduced to bring the control and target lines of all gates close to each other as shown in Figure 4. In this case, the cost of the circuit increases to 32 since each SWAP gate cost 3 elementary gates as was shown in Figure 5. The previous example demonstrates the importance of reducing the cost of SWAP gates when targeting technology that requires LNN realization. Therefore, it is important for the synthesis tools to take into account SWAP cost to reduce overall implementation cost. III.
P ROBLEM F ORMULATION & C OST F UNCTION
In this section, we proposed a post processing greedy algorithms that reduces the number of SWAP gates needed to realize a circuit in LNN architecture using input line reordering. The algorithm assume the circuit to be synthesized is implemented using primitive gates from the NCV library, however the proposed algorithm can be easily extend to accommodate other libraries as well.
b c
Circuit 3-17 Realization using MCT Library
As mentioned before, many functions are normally implemented using complex multi-qubit quantum gates. Therefore, every such complex, gate must be decomposed into its elementary counterpart to calculate its quantum cost. For example, consider the circuit shown in Figure 2 which consists of NOT, CNOT and Toffoli gates. In order to find the quantum cost for this circuit, it must be first decomposed into elementary gates
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d e Fig. 6.
Circuit 4gt11-84
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Fig. 3.
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Circuit 3-17 Realized on LNN architecture
A circuit with n inputs line can be described as a fully connected graph G(V,Ejk ,wjk (x,y)) with n nodes where V = {1, 2, 3, ..., m} are its nodes, Ejk an edge between node j and k, and w(x,y) being the weight Ejk . Edge weight is given using two values, x which represents number of times two lines interact with each other as a target-control pair, whereas y represents distance of the two nodes in the LNN architecture. If the two input lines do not interact with each other, x in this case is equal to 0. As for y, it is calculated using the formula: yjk =| yj − yk | −1
(1)
where yi refers to nodes j and k index in a linear ordered array. In linear array, non-adjacent node cannot interact with each other directly and must communicate using other nodes. For example, a node P1 , i.e. first node, can not communicate with node P4 directory and must go through node P2 and P3 . Thus the distance value y for this node pair in this case is 2.
assignment in such a way to reduce overall SWAP cost SC(G) defined as: SC(G) =
(2,0)
V1 (2,3)
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e d Fig. 8.
IV.
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xjk × yjk
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Reorder Circuit Realization
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V5
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As a motivational example, consider the circuit given in Figure 6 with input line assignment V={1,2,3,4,5}→{a,b,c,d,e}. For LNN realization of this circuit, 7 swap pairs (i.e. total of 14 swap gates) are needed in addition to the original 7 gates which will result in total quantum cost to 49. On the other hand, if the node-input assignment were V={1,2,3,4,5}→{b,c,a,e,d}, the number of SWAP gates is reduced to one pair resulting in total cost of 13 ( 73% cost reduction). Figure 8 shows the circuit after using the new input assignment.
V2 (0,2)
(1,1)
n−1 X
j=1 k=j+1
For example, for the circuit shown in Figure 6, graph G is shown in Figure 7 where where the inputs “a” through “e” are ordered linearly (input a assigned node 1, input b assigned to node 2,...etc). In this graph only four edges have non-zero value for x representing circuit structure, which is fixed, whereas y values are calculated using input order assignment V={1,2,3,4,5}={a,b,c,d,e,f} which would change if input assignment we chosen differently.
Fig. 7.
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Circuit 3-17 Realization using NCV Library
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Interaction Graph (IG) for Circuit 4gt11-84
In order to minimize the cost of a given circuit when implemented in LNN architecture, we proposed input order
P ROPOSED A LGORITHM & E XPERIMENTAL R ESULTS
The algorithm proposed is a greedy algorithm that tries to minimize the cost of the graph by swapping the order of two different nodes (i.e. assignments) and calculating the resulting cost. If the cost of the new graph is lower than the original cost, the new order is used otherwise a new pair of nodes is selected for possible reordering. Note that the cost function used in this implementation is the cost function defined in equation 2. Algorithm 1 gives the pseudocode of the proposed algorithm. It worth to mention that the value of Max Iteration
is a user defined input and it was set to 150 in our experiments. Algorithm 1 Proposed Algorithm iteration = M ax Iteration while iteration 6= 0 do for i ← 1 to n − 1 do for j ← i + 1 to n − 1 do G′ = Swap(G, i, j) if (SC(G′ ) < SC(G)) then G = G′ end if end for end for iteration = iteration − 1 end while return G The proposed algorithm was implemented using Java and was ran on a PC running windows operating system. Benchmark circuits from RevLib [39] were used as test cases. The RevLib is a database of different functions and circuit realizations which have been extensively used to evaluate various synthesis and optimization approaches for reversible circuit. In the discussion that follows, we only present the results for only a subset of the circuits available in this database. A. Experimental Setup The RevLib contains different reversible circuits implemented using various reversible circuit gate libraries such as NCT or MCT library. In order to evaluate the proposed algorithm impact on LNN realization, all circuits were first decomposed into elementary gates appropriate the NCV gate library. The toolset proposed in [40] was used for this purpose in this work. After decomposing all circuits into their primitive counterparts, the number of SWAPs required to convert the circuit into LNN realization was calculated. Then, the proposed algorithm was ran on the decomposed circuits to reorder the input lines and calculate the number of SWAPs needed for LNN realization. Once the number of SWAPs was found, the total quantum cost between both realizations is calculated and compared. B. Line Reordering Results The proposed algorithm was executed on a subset of the benchmark circuits available and the results are shown in Table I. In the table, the second till fifth column give original circuit characteristics where columns Name, GC, QC give the name, gate count, and quantum cost of the original circuit as specified by the RevLib.The number of SWAPs and cost of LNN realization for the original circuit are given as # Swap and LNN respectively. The remaining columns give the number of swaps, LNN cost, and percent reduction in quantum cost for the proposed algorithm respectively. From the table, it can be seen that on average, the proposed algorithm was able to reduce the LNN cost by 29% on the simulated benchmark circuits. The algorithms require negligible run time to find its solution, hence not an issue to be concerned with. The
proposed algorithm perform well when compared to advanced heuristic algorithm can be found in [41]. V.
C ONCLUSION
This paper proposed a greedy algorithm to minimize quantum cost of reversible circuits for Linear Nearest Neighbor realization. The algorithm performance on benchmark circuits was found to reduce quantum cost of the original circuits by approximately 29% for LNN realization. In addition to its simplicity, the greedy algorithm has been recently shown to perform rather compared to more advanced algorithm [41] R EFERENCES [1] P. Shor, “Polynomial time algorithms for prime factorization and discrete logarithms on a quantum computer,” SIAM Journal on Computing, vol. 26, no. 5, pp. 1484–1509, October 1997. [2] L. Grover, “Quantum computers can search arbitrarily large databases by a single query,” Physical Review Letters, vol. 79, no. 23, pp. 4709– 4712, 1997. [3] F. Magniez, M. Santha, and M. Szegedy, “Quantum algorithms for the triangle problem,” in 16th annual ACM-SIAM symposium on Discrete algorithms, 2005, pp. 1109–1117. [4] M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information. Cambridge University Press, 2002. [5] V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, “Synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710–722, June 2003. [6] M. Saeedi and I. L. Markov, “Synthesis and optimization of reversible circuits - a survey,” ACM Computing Surveys, vol. 45, no. 2, June 2013. [7] V. V. Shende, S. S. Bullock, and I. L. Markov, “Synthesis of quantumlogic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1000–1010, june 2006. [8] K. N. Patel, I. L. Markov, and J. P. Hayes, “Optimal synthesis of linear reversible circuits,” Quantum Information & Computing, vol. 8, no. 3, pp. 282–294, March 2008. [9] O. Golubitsky and D. Maslov, “A study of optimal 4-bit reversible toffoli circuits and their synthesis,” IEEE Transactions on Computers, vol. 61, no. 9, pp. 1341–1353, September 2012. [10] M. Saeedi, M. S. Zamani, M. Sedighi, and Z. Sasanian, “Reversible circuit synthesis using a cycle-based approach,” ACM Journal on Emerging Technologies in Computing Systems, vol. 6, no. 4, pp. 1–26, December 2010. [11] D. M. Miller, D. Maslov, and G. W. Dueck, “A transformation based algorithm for reversible logic synthesis,” in 40th annual Design Automation Conference, June 2003, pp. 318–323. [12] D. Maslov, G. W. Dueck, and D. M. Miller, “Techniques for the synthesis of reversible toffoli networks,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 4, pp. 42:1–42:28, 2007. [13] D. Wang, S. Sun, and H. Chen, “Matrix-based algorithm for 4-qubit reversible logic circuits synthesis,” Energy Procedia, vol. 13, pp. 365– 371, 2011. [14] K. Fazel, M. A. Thornton, and J. E. Rice, “Esop-based toffoli gate cascade generation,” in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 2007, pp. 206–209. [15] M. H. A. Khan and M. A. Perkowski, “Multi-output esop synthesis with cascades of new reversible gate family,” in International Symposium On Representations and Methodology of Future Compo Technology, 2003. [16] P. Gupta, A. Agrawal, and N. K. Jha, “An algorithm for synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2317–2330, November 2006. [17] J. Donald and N. K. Jha, “Reversible logic synthesis with fredkin and peres gates,” ACM Journal on Emerging Technologies in Computing Systems, vol. 4, no. 1, pp. 2:1–2:19, April 2008.
TABLE I. Name 4mod5-v1 23 4 49 17 4gt11 84 3 17 13 4gt5 75 4gt10-v1 81 4gt12-v1 89 4gt13-v1 93 4mod7-v0 95 alu-v4 36 hwb4 52 rd73 140 rd53 135 rd84 142 adder8 172 cnt3-5 180l ham7 104 hwb5 55 hwb6 58 cycle10 2 110.real hwb7 62 sym9 148 urf2 152 hwb9 123 plus63mod4096 163 urf5 158 plus63mod8192 164 urf6 160 urf1 149 plus127mod8192 162 urf3 155
R EORDERING R ESULTS ON R IV L IB B ENCHMARKS GC 24 32 7 14 5 36 53 17 40 32 23 76 78 112 96 125 87 109 146 1212 2663 4452 25150 20421 29020 51380 37102 53700 57770 65456 132340
After Decomposition QC # Swap 24 25 32 21 7 7 14 3 22 20 36 41 53 86 17 26 40 36 32 35 23 14 76 119 78 132 112 234 96 47 125 200 87 102 109 115 146 179 1212 2636 2663 4412 4452 8424 25150 45338 20429 42315 29036 77834 51380 114784 37130 105638 53700 239034 57770 122802 65500 188367 132340 331578 Average
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NNC 174 158 49 32 142 282 569 173 256 242 107 790 870 1516 378 1325 699 799 1220 17028 29135 54996 297178 274319 496040 740084 670958 1487904 794582 1195702 2121808
# Swap 15 16 1 3 14 16 26 6 22 17 9 75 68 142 45 182 70 60 145 2265 3810 6198 35640 35933 60285 90880 75420 126038 90052 170462 229414
Greedy NNC 114 128 13 32 106 132 209 53 172 134 77 526 486 964 366 1217 507 469 1016 14802 25523 41640 238990 236027 390746 596660 489650 809928 598082 1088272 1508824
Red. 34% 19% 73% 0% 25% 53% 63% 69% 33% 45% 28% 33% 44% 36% 3% 8% 27% 41% 17% 13% 12% 24% 20% 14% 21% 19% 27% 46% 25% 9% 29% 29%
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