A Hybrid Interleaved/Switched–Capacitor Boost Converter Julio C. Rosas-Caro
Hilda L. Torres-Espinosa
Academia de Electrica, Electronica y Control Universidad Panamericana Campus Guadalajara Zapopan Jalisco, México
[email protected]
Research and Graduate Studies Division Instituto Tecnologico de Ciudad Madero Ciudad Madero Tamaulipas, México
[email protected]
Fernando Mancilla-David
Antonio Valderrabano-Gonzalez
Department of Electrical Engineering University of Colorado Denver Denver Colorado, USA
[email protected]
Academia de Electrica, Electronica y Control Universidad Panamericana Campus Guadalajara Zapopan Jalisco, México
[email protected]
Abstract—This paper proposes a boost dc–dc converter topology with the capability of canceling the input current ripple at an arbitrarily preselected duty cycle, high–voltage gain without utilizing extreme values of duty cycle or boosting transformers, it contains a switched-capacitor structure in which the current among capacitors is continuous. The paper provides details on the principle of operation via topological considerations and a mathematical model. The key factor of reactive components sizing is also discussed. The converter was validated in the laboratory through the construction of a hardware prototype.
I.
INTRODUCTION
The voltage provided by a number of small power– generating sources such as renewables is usually low in amplitude. As a result of this, a boost–type architecture with a large voltage gain is required to link this voltage to an inverter. Another important requirement for a converter in renewable energy applications (for example in fuel cells) is to drain a continuous current with minimum ripple. Therefore, converters combining these two features are expected to find many applications within the renewable energy context. A traditional boost converter can achieve an infinite voltage gain as the duty cycle approaches 100% in theory, but in practice the leakage resistance in the inductor– charging loop limits the boost ratio [1], [2]. Because of this, a boost converter is not used when the required boost ratio is higher than four. A standard approach to overcome this issue is the use small reactive components by increasing the converter’s switching frequency for a given amount of acceptable ripple. It is well documented in the literature that
978-1-4799-0336-8/13/$31.00 ©2013 IEEE
small reactive elements also feature a small leakage resistance [1]–[5]. However, the finite switching–time in actual power semiconductors limits the switching frequency when the duty ratio is too small or too high. A traditional solution to this is the employment of intermediate transformers to increase the voltage without using extreme values of duty cycles. Several topologies have been proposed in the literature for overcoming those challenges, including the use of coupled inductor and/or transformers [6]–[12]. Moreover, the literature offers additional solutions based on the switched capacitors (SC) principle, with a combination of converters featuring coupled inductors with voltage multipliers or switched capacitor multipliers [13]–[19]. Converters without coupled inductors based on pure SC circuits have found applications in low power on–chip applications, but at larger power levels solutions based on traditional converters have been preferred due to the number power semiconductors required, current spikes among capacitors, and high switching frequency limitations. The interleaving of SC circuits has also been proposed as a solution for high voltage gain [20]–[22]. A number of power converters for higher power application that eliminate the use of coupled inductors or transformers have been proposed [1]–[5], [23]–[27]. These topologies are expected to penetrate the market of high–gain dc–dc converter as silicon carbide and other wide band-gap fast–switching power semiconductors become available. This will make the switching frequency limitation in power converters to become a transformers issue, since transformers increase
797
their losses when the frequency is too high. The interesting paper of [27] uses the SC principle with Complete Charge Interchange (CCI) [28] along with an additional pulse width modulated (PWM) boost converter for voltage regulation. As explained in the literature [29], SC circuits with CCI are not utilized for voltage regulation, because this negatively affects the converter’s efficiency. However, combining a CCI–SC circuit with a PWM controlled converter allows for optimizing the efficiency of both converters. In summary, converters with a high voltage gain which do not require a transformer, coupled inductors or extreme duty cycle values are highly desirable given the quick penetration of low– voltage power–generating sources. Another main challenge in a renewable energy power processing circuit is the expected low input current ripple. The standard solution of using large inductors leads to a small current ripple but large inductors are heavy, large in size and expensive. In addition, a large inductor also slows down transient response of the converter. The topology proposed in this paper corresponds to an improved and different version of an approach recently proposed in the literature [30]. Herein, a dc–dc boost converter topology is proposed which combines two principles highly used in state–of–the–art power converters: (i) at the converter’s input two inductors are interleaved for canceling the input current ripple and (ii) at the converter’s output a switched capacitor voltage multiplier is utilized to increase the voltage gain. The switched capacitor stage has been improved by using a small resonant inductor to limit the peak current resulting from the switching process and hence preventing large current spikes. Different from [13]– [19], the proposed converter does not require transformers or coupled inductors, and is intended to be used along with fast–switching power semiconductors. Different from [27], the topology proposed herein is able to cancel the input current ripple. Further, it combines a CCI–SC circuit with a boost converter into a single converter, and is able to provide voltage regulation without sacrificing the converter’s efficiency. The paper is organized as follows. Section II provides the topological details of the proposed converter, followed by its mathematical model and reactive components selection in Section III. Experimental results validate the approach in Section IV, and the conclusions of Section V close the paper II.
PROPOSED TOPOLOGY
The proposed topology is illustrated in Fig. 1(a). As the figure suggests, the topology contains two transistors (s1, s2), three diodes (d1, d2, d3), three capacitors (C1, C2, C3), two inductors for energy storage (L1, L2) and a small inductor (L3) for current limiting through d3. In practical implementation L3 is around 100 times smaller than L2 and 50 times smaller than L1. As a result of its reduced size, small–ripple approximations do not apply to L3, and hence
the selection of its inductance is based on the CCI between C2 and C3 [28]. Details on the procedure for its selection are provided in Subsection III-C. L1 d1
L2
ii vin
s2
c1
s1 Vo
R d2
c2
d3
c3 L3
(a)
L1
L1
ii
L2
d1
vin
s2
s1 d2
c2
ii
c1
d1
L2 s2
vin Vo
c2
c3
d3 iin
I
c1
s1 Vo
d2
c3
d3
(b)
(c)
vin-vc2
iL2
L2
vin
∆iL2
L2
iLD3
vin-vc1 L1
vin 0 s2
∆iL1
iL1
L1
t
DTs
s1 (1-D)Ts
(d)
Fig. 1. (a) Circuit schematic of proposed topology; (b)–(c) equivalent circuit schematics for each switching state; and (d) waveforms of input current, current through input inductors, and switching sequence.
The transistors switch complementary, i. e., when s1 is closed, s2 is open and viceversa. The operation of the converter may be explained considering the small–ripple approximation [31] for the voltage across capacitors and continuous conduction mode for L1 and L2. The details on the circuit operation are conveniently introduced by employing several analytical waveforms, which are later validated via experiments. As illustrated in Figs. 1(b) and (c), the converter has two equivalent circuits resulting from the switch action. When s1 is on (and s2 is off), the topology is represented by the equivalent circuit of Fig. 1(b). During this time, the diode d1 is reverse biased blocking the voltage across C1. Similarly, diode d3 is reverse biased blocking the voltage across C3. The current through L2 forces the diode d2 to be closed since transistor s2 is open. Fig. 1(d) shows, from top to bottom, typical waveforms for the currents
798
through L1 and L2, the input current and the switching sequence for s1 and s2. While s1 is conducting, the current through L1 rises with a slope of vin/L1 and L2 discharges at a rate of (vin-vc2)/L2. On the other hand, while s2 is on (and s1 is off) the resulting equivalent circuit is as depicted in Fig. 1(c). During this time, the L1 discharges with a slope equal to (vin-vc1)/L1 while L2 charges at a rate of vin/L2. Furthermore, while s2 is conducting the capacitors C2 and C3 are connected in parallel, leading to a switched capacitor– type behavior. As a result of this, a small inductor (L3) is needed in order to limit the peak current around this loop. A typical waveform for the current through L3 is also depicted in Fig. 1(d). A key feature of the proposed topology can be observed in Fig. 1. The converter’s input current corresponds to the sum of the currents through L1 and L2. Since L1 and L2 charge/discharge in a complimentary manner, one can size those two inductors such that the input current is ripple–free for a selected value of the converter’s duty cycle. Current waveforms illustrated in Fig. 1(d) corresponds to a converter that features a zero input current ripple at a duty cycle of D = 75%. This is possible if both inductors are charged with the same voltage and L2 = 3L1. Further, the principle of operation of the converter suggests that both inductors may (or may not) be coupled for improving the design, but not for energy transfer as it is required in topologies such as the flyback converter. III.
ANALYSIS AND SELECTION OF COMPONENTS
As Fig. 1 suggests, the proposed architecture corresponds to an interleaving–type converter, combining features from a boost converter and a three–switch high–voltage converter [2]. The topology features a small inductor for peak current limiting which has no effect on the basic operation of the converter for power transfer. Additionally, the interleaving of two inductors allows current ripple cancelation at an arbitrary preselected duty cycle. Furthermore, the switch count is reduced to two and as a result the converter is controlled by a single duty cycle. A. Voltage gain analysis The dynamics of L1, L2 and C1 may be conveniently analyzed considering their average behavior [31], as their state variables feature triangular waveforms similar to those in traditional dc/dc converters. On the other hand, C2, C3, and L3 form a SC circuit and therefore their dynamic behavior has to be formulated with additional considerations. However, a number of the converter’s features can be explained focusing on L1, L2 and C1 where dynamic averaging applies. Under this assumption, switching functions may be readily replaced by their corresponding duty cycles. For the analysis below the converter’s duty ratio d(t) is defined as percentage of time over the switching period that the switch s2 is on, that is,
d (t ) =
1 TS
∫
t +TS
t
q2 (τ )dτ
(1)
where TS is the switching period and q2 is the switching function of s2 that is equal 1 while s2 is closed and 0 otherwise. Under this assumption, and neglecting for now inductors’ ESR, the equations that represent the average dynamics for inductors L1 and L2 are,
diL1 = d (vin − vC1 ) + (1 − d )(vin ) dt di L2 L 2 = d (vin ) + (1 − d )(vin − vC 2 ) dt L1
(2) (3)
In steady state the average voltage across the inductors must be equal to zero. Thus, by zeroing the left–hand–side of (2) and (3) the steady state voltage across C1 and C2 may be expressed as,
VC1 =
1 Vin D
(4)
VC 2 =
1 Vin 1− D
(5)
In (4) and (5) (and through the rest of the paper) capital letters denote steady state quantities. It readily follows from (4) and (5) that the voltages across C1 and C2 are proportional to one another, that is,
VC1 =
1− D VC 2 D
(6)
VC 2 =
D VC1 1− D
(7)
On the other hand, the equation that represents the average dynamics for C1 is,
C1
dvC1 v +v = diL1 − C1 C 3 dt R
(8)
In steady state the average current through the C1 must be equal zero, which leads to the following expressions for the current through L1,
I L1 =
1 VC1 + VC 3 D R
(9)
As C2 and C3 form a switched–capacitor circuit, average dynamic equations do not apply. However, the steady state current through L2 can be computed by input/output power balance considerations. It becomes,
IL2 =
799
1 VC1 + VC 3 1− D R
(10)
Furthermore, from Fig. 1(a) the output voltage is,
V0 = VC1 + VC 3
rewrite (3) as, (11)
L2
Thus, combining (4), (5), (9), (10) and (11) the converter gain becomes,
V0 1 = Vin D(1 − D)
VC1 D 1 VC1 1 = I L1 = 1 + D D R D D R 1 − (1 − )
(14)
VC 2 1 1 − D 1 VC 2 I L 2 = 1 + = D 1− D R D(1 − D ) R
(15)
diL1 = d (vin − RL1iL1 − vC1 ) + (1 − d )(vin − RL1iL1 ) dt
(20)
And substituting (15) in (20) the ratio between the voltage across C2 and the input voltage becomes.
VC 2 1 = RL 2 Vin (1 − D) + D(1 − D) R
(21)
Finally, using (11) and (13) the converter’s practical gain is obtained by adding (18) and (21),
(13)
The above equations simplify the inclusion of ESRs’ as the inductor currents have been expressed in terms of the voltages across the capacitors they directly connect to. By including L1’s ESR (2) becomes,
L1
0 = D(Vin − RL 2 I L 2 ) + (1 − D)(Vin − RL 2 I L 2 − VC 2 ) 0 = Vin − RL 2 I L 2 − (1 − D)VC 2
The gain expressed by (12) corresponds to an ideal case as the inductors’s ESR has been neglected. In a practical implementation, the leakage resistance in inductors greatly limits this gain. In order to quantify this, consider first rewriting (9) and (10) using (6), (7) and (11),
(19)
Which in steady state becomes,
(12)
As mentioned earlier, this circuit has a switched capacitor stage which may be increased by including additional capacitors and diodes [1], [2], [32]. Capacitors C2 and C3 work in a switched capacitors way because C2 clamps the voltage across C3 while the switch s2 is closed. This is because the energy stored in L3 is negligible compared to other energy storage elements in the converter. Furthermore, in steady state C2 and C3 feature the same average voltage [2], then,
VC 2 = VC 3
diL 2 = d (vin − RL 2iL 2 ) + (1 − d )(vin − RL 2iL 2 − vC 2 ) dt
V0 = Vin D +
1 1 + RL1 RL 2 (1 − D) + D(1 − D) R D(1 − D) R
(22)
By construction, smaller inductor features a smaller ESR. As explained earlier, the topology proposed herein sizes the inductors to cancel the input current ripple at a given duty ratio. For example, if L2 = 3L1 the input current is ripple– free at D = 75%. As a first approximation, it may be assumed that the inductors ESR’s follow the same trend, that is, RL2 = 3RL1. Fig. 2 shows the converter’s voltage gain under this assumption for different values of the ratio between the load resistance (R) and RL2. The figure is readily obtained by plotting (22).
(16)
Where RL1 is the ESR resistance of L1, In steady-state (16) becomes,
0 = D(Vin − RL1I L1 − VC1 ) + (1 − D)(Vin − RL1I L1 ) 0 = Vin − RL1I L1 − DVC1
(17)
By substituting (14) in (17) the ratio between the voltage across C1 and the input voltage becomes.
VC1 = Vin D +
1 RL1 D(1 − D) R
(18)
Similarly, the inclusion of the ESR in L2 (RL2) leads to
Fig. 2. Voltage gain vs duty cycle considering inductor’s ESR.
As the figure suggests, the minimum voltage gain is 4 and occurs at D = 50%. If the duty cycle is smaller than 50% the
800
gain increases again, and therefore the minimum gain the converter can operates is around 4. The operating range is selected to be at D > 50%, which ensures that L3 will have enough time to discharge. This is discussed in detail in Subsection III-C. As a result of the analysis, the selection of the inductors has to be such that L2>L1, in order to achieve ripple cancelation for the input current. Further, L2>L1 implies that RL2>RL1 and thus larger voltage gains are obtained for D < 10%, which can be observed in Fig. 2. This is a compromise between canceling the input current ripple and obtaining a larger voltage gain. However, in practical application dc/dc converters are operated at duty cycles of about 20% < D < 80%. It can be seen from the figure that between that range the voltage gain is practically symmetric, and hence the voltage gain lost is minimal. It is noteworthy that selecting D > 50% as the operating range translates into having the SC part of the converter handling a larger amount of the converter’s throughput power. The figure also suggests that, as in most dc/dc converter’s topologies, the inductor’s ESR limits the practical gain of the approach. Therefore, this topology is more suitable if a large switching frequency is employed as in that case reactive components (and hence ESRs) are very small. B. Energy storage inductors sizing From Fig. 1(d) it readily follows that the current ripple on the inductor is given by,
∆iL1 =
Vin (1 − D) L1 FS
(23)
∆iL 2 =
Vin D L2 FS
(24)
Where FS = 1/TS is the converter’s switching frequency. The input current ripple, denoted by ∆iin, corresponds to the difference between each inductor’s current ripple, that is,
V D (1 − D) ∆iin = in − FS L2 L1
D 1− D
∆iin =
(26)
For example, if the expected input and output voltages are such that the duty cycle is equal to 75%, by sizing L1=3L2 the input current ripple is eliminated. Once the values of L1 and L2 are selected, (25) may be used to predict the input current ripple for the full operating range. Thus, if L1=3L2,
Vin 4 D − 1 FS L2 3
(27)
It is clear from (27) that there is a linear dependence of the input current ripple with respect to the value of the duty cycle, and the assumption of ripple–free input current becomes weaker as the operating point departs from the selected duty ratio. C. Peak current limiting inductor sizing As discussed earlier, the diode d3 connects the capacitors C2 and C3 in parallel and as a result a peak current limiting inductor is needed. Moreover, the average current through the diode equals the load current, as it may be evident from Fig. 1(a). However, the shape of the current through d3 may be undesirable, and hence the need to control it. In order to understand the phenomenon, consider the switching process at the time when s2 turns off. As suggested by Fig. 1(c), at that instant capacitors C2 and C3 feature exactly the same voltage because they were connected in parallel. Call this voltage VC.0. After s2 opens, the circuit commutes into the topology of Fig. 1(b) and as result of this C2 and C3 are no longer connected. While s2 is off (during (1-D)TS sec), C3 discharges following the load current while C2 charges following the current through L2. Call VC2.1 and VC3.1 the final voltage across capacitors C2 and C3, respectively. They can be expressed as,
VC 2.1 = VC .0 + ∆vC 2 = VC .0 +
I L2 (1 − D ) TS C2
(28)
VC 3.1 = VC .0 − ∆vC 3 = VC .0 −
I0 (1 − D ) TS C3
(29)
At the end of (1-D)TS the voltage difference between them is given by,
I I Vdiff = ∆vC 2 + ∆vC 3 = L 2 + 0 (1 − D ) TS C2 C3
(25)
As it is evident from (25), the input current ripple can be eliminated by zeroing out the left-hand-side of this equation. This leads to the following relationship,
L2 = L1
(25) becomes,
(30)
If there is no inductor in series with d3, the peak current would be Vdiff (some volts) over the resistance in this loop, given by the on–state resistance of s2 and d3, and the ESR of C2 and C3 (some tens of mΩ). Figs. 3(a) and (b) show a circuit schematic for the current loop where Req stands for the lumped resistance of the various elements around the loop. This may lead to a peak current that overpass the peak current limit of the various devices in that loop. At the time of design this peak current can be computed using manufacturers datasheets and thus the inductor in series with d3 may (or may not) be required. If the current overpass the peak current limit of devices the inductor is
801
mandatory. As shown in Fig. 3(c), this current raises rapidly and may destroy power semiconductors if the inductor L3 is not properly designed. L1 d1
L2
ii
s2
vin
d3
c1
s1 Vo
d2
c2
ceq
Req iLD3
c3
îL3 =
(a)
Ld3
∆vC1 =
Ld3 C3
iO
iL2
Tdis
C3
∆vC 2 =
Vdiff L3
∆q
iL3
i0
1 2f0
s2
ipeak t
(1-D)Ts
DTs
s1 (c) Fig. 3. (a)–(b) Equivalent circuit schematics and (c) waveforms for the reactive components selection.
From Figs. 3(a) and (b) is also evident that Ceq is the series connection of C2 and C3. Since L3 stores a small amount of energy, it charges and discharges completely in a switching cycle, smoothing out the current among capacitors. However, it also produces a resonant current peak at a frequency of,
ω 1 f0 = 0 = 2π 2π L3Ceq
I0 (1 − D)TS C1
(33)
Also, while s1 is closed the capacitor C2 charges following the current through L2, and hence,
(b)
∆vC3= ∆q
(32)
ω0 Ld 3
D. Capacitors sizing The selection of the capacitance for C1, C2 and C3 may be approached following a procedure analogous to that used in the sizing of the inductors L1 and L2. While s1 is on, the current through C1 follows the load current, and thus,
d3
vC3
Vdiff
(34)
Finally, C3 may be selected recognizing that L3 carries the same average current as the load. When the instantaneous value of current through this inductor overpass the output current, the capacitor C3 begins charging which leads to a voltage increase ∆VC3 given by ∆q/C3. This is graphically illustrated in Fig. 3(c), where the shaded area represents the charge ∆q. After L3 has been selected, the time while C3 is charging can be computed by finding the time at which i0 < iL3(t), as suggested in Fig. 3(c). Next, C3 discharges through the remaining of the switching period, and hence,
1 i 2 − arcsin 0 Tdis = TS − 2f ω 0 îL3 0
(35)
Where Tdis corresponds to the time while C3 discharges. Since during this period C3 follows the load current it is possible to state,
∆vC 3 =
(31)
As explained in Subsection III-A, the converter will operate at a duty cycle larger than 50%. Therefore, L3 should be selected such that f0>FS. This ensures the inductor will complete the discharge process before the beginning of the next switching stage for all values of the duty cycle within the operating range. Furthermore, Fig. 3(c) provides the basis for the calculation of the peak current around the loop. At the beginning of the charging period the current starts rising at a rate of Vdiff / L3. Hence, representing the current through the loop as iL3(t)=îL3sin(ω0t) its derivative at t=0 can be computed and equated to Vdiff / L3. This allows solving for îL3,
I L2 (1 − D)TS C2
I0 Tdis C3
(36)
Which allows for the sizing of C3. IV.
EXPERIMENTS
The converter proposed herein was prototyped in the laboratory in order to validate its principle of operation. The topology of Fig. 1(a) was implemented in hardware as depicted in the photo of Fig. 4. A complete list of parameters is provided in Table I. A Texas Instruments microcontroller MSP430G2231 was used to provide the gate driver signals. According to (26) and the values of L1 and L2 given in Table 1, the input current should be ripple–free at D = 70.6%. Fig. 5(a) and (b) shows illustrative waveforms for the converter operating at D = 70%.
802
validated. Currently, the authors are investigating the optimal sizing of inductors over a duty cycle range rather than a fixed duty cycle. This will be the subject of a publication in the future.
Fig. 4. Hardware photo.
TABLE 1 EXPERIMENTAL PARAMETERS Parameter Input voltage Duty Cycle Output voltage L2 L1 C1, C2, C3 Mosfets Diodes FS
Value 15V 70% 71V 330 µH 140 µH 10 µF IRFP4668PBF MBR40250G 25Khz
1A/div
It is evident from the experimental plots that the input current is almost ripple–free. A closer examination of the measurements also suggests the experimental data are consistent with the analytical results developed earlier in the paper. Fig. 6 shows the efficiency measured on the experimental prototype. V.
CONCLUSION
This paper proposes a boost dc–dc converter topology with the novel capability of canceling the input current ripple at an arbitrarily preselected duty cycle. This is accomplished without increasing the number of components count. Additionally, the converter features a high–voltage gain without utilizing extreme values of duty cycle or boosting transformers. These features make the converter ideal to process electric power coming from low–voltage power–generating sources, such as renewables. Moreover, the rapid development of silicon carbide and other wide bandgap fast–switching power semiconductors will enable the use of smaller reactive components and hence provide further advantages to the approach proposed herein against transformer or coupled inductor–based topologies. Experimental results are consistent with the analytical predictions of the various formulas developed through the paper and hence the approach may be considered definitely
10µsec/div (a)
10V/div
10µsec/div (b)
Fig. 5. Experimental waveforms for D = 70% (a) currents through inductors and input current; and (b) voltage across switches and output voltage.
Fig. 6. Converter’s efficiency for different values of the output power.
VI.
REFERENCES
[1] J. C. Rosas-Caro, J. M. Ramirez, F. Z. Peng, and A. Valderrabano, “A dc-dc multilevel boost converter,” IET Power Electronics, vol. 3, no. 1, pp. 129–137, January 2010.
803
[2] Z. Dongyan, A. Pietkiewicz, and S. Cuk, “A three-switch high-voltage converter,” IEEE Trans. on Power Electronics, vol. 14, no. 1, pp. 177183, January 1999. [3] D. Maksimovic, and S. Cuk, “Switching converters with wide dc conversion range.” IEEE Trans. on Power Electronics, vol. 6, no. 1, pp. 151-157, January 1991. [4] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switchedcapacitor/ switched-inductor structures for getting transformerless hybrid dc-dc pwm converters.” IEEE Trans. on Circuits and Systems I, vol. 55, no. 2, pp. 687-696, March 2008. [5] R. D. Middlebrook, “Transformerless dc-to-dc converters with large conversion ratios.” IEEE Trans. on Power Electronics, vol. 3, no. 4, pp. 484-488, October 1988. [6] L.H.S.C. Barreto, P.P. Praça, D.S. Oliveira, and R.P.T. Bascope, "Single-stage topologies integrating battery charging, high voltage step-up and photovoltaic energy extraction capabilities," Electronics Letters, vol.47, no.1, pp.49-50, January 2011. [7] Y.P. Hsieh, J.F. Chen, T.J. Liang, and L.S. Yang, "Novel High StepUp DC-DC Converter for Distributed Generation System," IEEE Trans. on Industrial Electronics, vol.60, no.4, pp.1473,1482, April 2013. [8] S. M. Chen, T. J. Liang, L. S. Yang, and J. F. Chen, “A cascaded high step-up dc-dc converter with single switch for microsource applications,” IEEE Trans. on Power Electronics, vol. 26, no. 4, pp. 1146-1153, April 2011. [9] C. S. Leu, P. Y. Huang, and M. H. Li, “A novel dual-inductor boost converter with ripple cancellation for high-voltage-gain applications,” IEEE Trans. on Industrial Electronics, vol. 58, no. 4, pp. 1268-1273, April 2011. [10] B. R. Lin, J. Y. Dong, and J. J. Chen, “Analysis and implementation of a zvs/zcs dc-dc switching converter with voltage step-up,” IEEE Trans. on Industrial Electronics, vol. 58, no. 7, pp. 2962-2971, July 2011. [11] M. H. Todorovic, L. Palma, and P. N. Enjeti, “Design of a wide input range dc-dc converter with a robust power control scheme suitable for fuel cell power conversion,” IEEE Trans. on Industrial Electronics, vol. 55, no. 3, pp. 1247–1255, March 2008. [12] T. J. Changchien, S. K.and Liang, J. F. Chen, and L. S. Yang, “Stepup dc-dc converter by coupled inductor and voltage-lift technique,” IET Power Electronics, vol. 3, no. 3, pp. 369–378, May 2010. [13] Y. Berkovich, and B. Axelrod, “Switched-coupled inductor cell for dcdc converters with very large conversion ratio,” IET Power Electronics, vol. 4, no. 3, pp. 309–315, March 2011. [14] T. J. Liang, S. M. Chen, L. S. Yang, J. F. Chen, and A. Ioinovici, “A single switch boost-flyback dc-dc converter integrated with switchedcapacitor cell,” in Proc.2011 International Conference on Power Electronics and ECCE Asia, May-June 2011, pp. 2782–2787. [15] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, “Novel high stepup dc-dc converter with coupled-inductor and switched-capacitor techniques,” IEEE Trans. on Industrial Electronics, vol. 59, no. 2, pp. 998–1007, February 2012. [16] R. J. Wai, C. Y. Lin, R. Y. Duan, and Y. R. Chang, “High-efficiency power conversion system for kilowatt-level stand-alone generation unit with low input voltage,” IEEE Trans. on Industrial Electronics, vol. 55, no. 10, pp. 3702–3714, October 2008. [17] K. B. Park, G. W. Moon, and M. J. Youn, “Nonisolated high step-up stacked converter based on boost-integrated isolated converter,” IEEE Trans. on Power Electronics, vol. 26, no. 2, pp. 577–587, February 2011. [18] L. S. Yang, T. J. Liang, H. C. Lee, and J. F. Chen, “Novel high stepup dc-dc converter with coupled-inductor and voltage-doubler circuits,”
IEEE Trans. on Industrial Electronics, vol. 58, no. 9, pp. 4196-4206, September 2011. [19] S. V. Araujo, R. P. Torrico-Bascope, and G. V. Torrico-Bascope, “Highly efficient high step-up converter for fuel-cell power processing based on three-state commutation cell,” IEEE Trans. on Industrial Electronics, vol. 57, no. 6, pp. 1987–1997, June 2010. [20] S. C. Tan, M. Nur, S. Kiratipongvoot, S. Bronstein, Y. M. Lai, C. K. Tse, and A. Ioinovici, “Switched-capacitor converter configuration with low emi emission obtained by interleaving and its large-signal modeling,” in Proc. 2009 IEEE International Symposium on Circuits and Systems, May 2009, pp. 1081-1084. [21] S. C. Tan, S. Bronstein, M. Nur, Y. M. Lai, A. Ioinovici, and C. K. Tse, “Variable structure modeling and design of switched-capacitor converters,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 2132–2142, September 2009. [22] S. C. Tan, S. Kiratipongvoot, S. Bronstein, A. Ioinovici, Y. M. Lai, and C. K. Tse, “Adaptive mixed on-time and switching frequency control of a system of interleaved switched-capacitor converters,” IEEE Trans. on Power Electronics, vol. 26, no. 2, pp. 364-380, February 2011. [23] L. S. Yang, T. J. Liang, and J. F. Chen, “Transformerless dc-dc converters with high step-up voltage gain,” IEEE Trans. on Industrial Electronics, vol. 56, no. 8, pp. 3144-3152, August 2009. [24] A. A. Fardoun, and E. H. Ismail, “Ultra step-up dc-dc converter with reduced switch stress,” IEEE Trans. on Industry Applications, vol. 46, no. 5, pp. 2025–2034, September-October 2010. [25] S. Choi, V. G. Agelidis, J. Yang, D. Coutellier, and P. Marabeas, “Analysis, design and experimental results of a floating-output interleaved-input boost-derived dc-dc high-gain transformer-less converter,” IET Power Electronics, vol. 4, no. 1, pp. 168-180, January 2011. [26] B. Axelrod, Y. Berkovich, S. Tapuchi, and A. Ioinovici, “Single-stage single-switch switched-capacitor buck/buck-boost-type converter,” IEEE Trans. on Aerospace and Electronic Systems, vol. 45, no. 2, pp. 419–430, April 2009. [27] D. Gu, D. Czarkowski, and A. Ioinovici, “A large dc-gain highly efficient hybrid switched-capacitor-boost converter for renewable energy systems,” in Proc. of 2011 IEEE Energy Conversion Congress and Exposition ECCE 2011, September 2011, pp. 2495-2500. [28] S. Ben-Yaakov, “Behavioral average modeling and equivalent circuit simulation of switched capacitors converters,” IEEE Trans. on Power Electronics, vol. 27, no. 2, pp. 632–636, February 2012. [29] A. Ioinovici, C. K. Tse, and H. S. H. Chung, “Comments on “design and analysis of switched-capacitor-based step-up resonant converters”,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 6, p. 1403, June 2006. [30] J. C. Rosas-Caro, J. E. Valdez-Resendiz, J. C. Mayo-Maldonado, R. Salas-Cabrera, J. M. Ramirez-Arredondo, and J. Salome-Baylon, “Interleaved power converter with current ripple cancelation at a selectable duty cycle,” in Proc, 2011 IEEE Energy Conversion Congress and Exposition ECCE 2011, September 2011, pp. 122–126. [31] R. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publishers, 2001. [32] J. C. Rosas-Caro, J. C. Mayo-Maldonado, R. F. Vzquez-Bautista, A. Valderrbano-Gonzlez, R. Salas-Cabrera, and J. E. Valdez-Resndiz, “Hybrid voltage-multipliers based switching power converters”,” Book Chapter by American Institute of Physics AIP: IAENG Transactions on Engineering Technologies, vol. 1373, pp. 29–43, August 2011.
804
