A Low-Power Wideband Reconfigurable Integrated ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

1997

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR Athanasios Vasilopoulos, Student Member, IEEE, Georgios Vitzilaios, Gerasimos Theodoratos, Student Member, IEEE, and Yannis Papananos, Senior Member, IEEE

Abstract—In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12- m CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately 20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively.

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Index Terms—Active-RC filter, compensation technique, low power, operational amplifiers, programmable resistor arrays, tuning circuit.

I. INTRODUCTION NTEGRATED continuous-time high-frequency baseband filters are essential building blocks in a wide variety of applications such as wireless transceivers, video signal processors, and hard-disk drives read/write channels [1]–[5]. - or the The majority of these filters employ either the MOSFET-C technique in conjunction with an automatic tuning method in order to alleviate the uncertainty in the value of filter elements [6]–[10]. Nonetheless, the trend towards low voltage supply entails new challenges in the realization of these techniques. In the - case, it is difficult to attain a broad dynamic range and good linearity performance with small power consumption, whereas CMOS implementations suffer from reduced programmability [11], [12]. In contrast, the MOSFET-C approach - in terms of power dissipation and noise may excel performance, but for low supply voltages, linearity and tuning range may be poor. Thus, when both low voltage operation and high linearity are demanded, the adoption of either of these filtering techniques will not suffice. To avoid the aforementioned drawbacks, some designs utilize mixed MOSFET-C and polysilicon resistor filters [13] or, preferably, plain active-RC filters that substitute transconductors or MOS resistors with simple polysilicon resistors [14]–[16]. This approach accomplishes excellent linearity,

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Manuscript received February 8, 2005; revised March 1, 2006. The authors are with the School of Electrical and Computer Engineering, National Technical University of Athens, Zografou 157 80, Athens, Greece (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2006.880616

fine noise performance, and minimum current dissipation. Moreover, its tuning range and accuracy is acceptable by many applications. The adjustment of the filter cut-off frequency is established by means of capacitor or resistor arrays. Capacitor matrices are superior in terms of frequency performance than their resistive counterparts, but they claim more silicon area [17]. Hence, for cost and chip area reduction, engaging resistor banks is a better solution. Integrated, continuous-time filters usually necessitate an automatic tuning scheme for their proper operation. In conventional filters, the tuning mechanism generally relies on an analog phase-locked loop (PLL) circuit, which often calibrates the time constant with a precision surpassing 1%. In active-RC filters, accuracy of correction improves as the number of switches in the or bank increases. Yet, given the tolerances of the passive elements in CMOS processes, it would be impossible for the tuning system to compete the accuracy of its classic counterpart as this dictates an impractical number of switches. However, several applications, like video filters, do not need more than 5% tuning precision [3]. The present paper describes an active-RC filter developed with the usage of programmable resistor arrays (PRAs). The designed filter is able to switch between a fifth-order Chebyshev structure and a third-order Elliptic form accompanied by an all-pass second-order equalizer. Furthermore, its cut-off frequency can be set at either 5 or 10 MHz. In all four states, an upgraded automatic tuning scheme, originating from [15] and [18], compensates the tolerances of the filter’s passive components in only one iteration, within a limit designated by the number of switches in the PRA (defined to be 5% for this work). The operational amplifiers of the filter operate on a 1-V supply and demonstrate a very good compromise between high-frequency performance and current consumption, due to the compensation technique employed. In particular, a 20 times boost is rendered to the dominant pole of the amplifier relative to traditional compensation practices without causing any stability problems in the presence of an output load. Measurements of a fabricated prototype evidence that the filter’s spurious free dynamic range (SFDR) reaches 73 dB when operating at 5 MHz. In the Chebyshev operating mode, the 1-dB compression point is as high as 3.6 dBm (differential input signal of 0.96 V ), while IIP3 is in excess of 20 dBm. This paper is organized as follows. In Section II, the filter architecture is analyzed. Section III discusses the operational amplifier design and examines the introduced compensation technique. The automatic tuning method is explained in Section IV. Finally, in Section V, experimental results are presented, and in Section VI, conclusions are summarized.

0018-9200/$20.00 © 2006 IEEE

1998


Fig. 1. Topology of the designed filter.

Fig. 3. Unit resistor. Fig. 2. Structure of (a) R

and (b) C

, presented for clarification purposes.

II. FILTER ARCHITECTURE It is desirable for some filters to facilitate invariant group delay [4], [5], whereas others are required to exhibit a programmable bandwidth [2]. Keeping in mind the above, the filter presented in this work incorporates the ability to modify both its transfer function and cut-off frequency. A fifth-order Chebyshev transfer function or a third-order Elliptic followed by a second-order all-pass equalizer that features very linear phase response, are the two implemented options. In both cases, the passband gain is 0 dB, the passband ripple is 0.1 dB, and the bandwidth can be set to either 5 or 10 MHz. These attributes make the filter usable in a variety of applications, as will be briefly explained in Section VI. A fully balanced cascade configuration [19] was chosen for the filter synthesis, as illustrated in Fig. 1. It was preferred over other configurations, such as the leapfrog, because of its straightforward utilization and its easily modifiable transfer function. The selection amongst the four states is feasible by digital signals that manipulate the values of all the resistors and and capacitors depicted. For clarification, the structure of is outlined in Fig. 2, as an example. The signal BAND controls the bandwidth of the filter, whereas signals CH and its complementary, ELL, determine the transfer function by regulating resistor and capacitor values. is assembled by series and parallel As it can be seen, combinations of a “unit resistor” that takes different values for and , respectively). the Chebyshev and Elliptic case ( The form of the unit resistor , as implemented in the present ) and work, is displayed in Fig. 3. It consists of a constant ( ), the latter being a 3-bit variable binary weighted part ( responsible for the time constant compensation. The general

Fig. 4. General structure of R

.

structure of , when an -bit digital word is used for tuning, is presented in Fig. 4. ), then in the genAssuming ideal switches (having can be expressed as follows: eral case ( -bit control word),

(1) If both resistors and capacitors obtain their maximum values (as a result of process and/or temperature variations) then the minimum value of the unit resistor must be chosen. In this case (the digital word is 0), thus is calculated:

(2) In the opposite extreme condition (resistors and capacitors are , consequently minimum) it should be is derived as shown below:

(3)

VASILOPOULOS et al.: A LOW-POWER WIDEBAND RECONFIGURABLE INTEGRATED ACTIVE-RC FILTER WITH 73 dB SFDR

In the above relations we have that (4) (5)

,

digital word used for tuning; decimal value of the digital control word; total number of stages that are comprised by parallel combinations of (see Fig. 4); variation of resistor and capacitor values, owing to process and temperature drifts; constant part of unit resistor ; variable binary weighted part of unit , , resistor ; nominal design resistor value; step of change for ; basic building block of .

product emanating from the The error in the value of the inherent quantization of the above approach is (6) . Considering the number of and becomes maximum for ) and the characteristics of the CMOS process used bits ( 20%, 15%), we derive that 7.4%. ( 5.1%. It should be The average quantization error is pointed out that, in practice, the switches’ is added to and affects the quantization error considerably as grows. A principal aspect that should be deliberated during the de, especially if the filter is to be deployed in a transsign of channels, is the matter of matching ceiver featuring and transforms when the tuning performance. The topology of is adapted to eliminate discrepanword is altered because cies in the product. Therefore, the above ought to be taken matching, and naturally ’s, differs for into account as every tuning word. by series and parallel comThe decision to manufacture binations of a basic resistor , is justified by the fact that this practice establishes very good matching [20]. At the same time, it is important to keep the area occupied by the resistances as small as possible. This calls for the minimum number of basic , which also simplifies routing resistors encompassed in during layout. To estimate this number, we inspect the general in Fig. 4. structure of , is The total number of basic resistors included in formulated as (7) One can easily derive that the minimum number of resistances is acquired for (8) which gives

for

.

1999

All the switches involved in the tuning circuitry, as well as those defining the transfer function, are implemented by nMOS transistors. The voltage driving the gates of these MOSFETs is 2.7 V, instead of 1 V (nominal supply of amplifier transistors). This is compulsory for two reasons. Firstly, if this voltage was in the order of 1 V, then a large input signal to the filter of these transistors would lead to improper switching as would vary significantly. The second reason is related with the the sum of the switches’ switches’ parasitics. Defining as when all of them are in the ON state and the corresponding total parasitic capacitance, then the time constant associated with the switches must be negligible compared to the bandwidth of the filter. A voltage lower , and consequently , than 2.7 V raises the switches’ to a level that drastically deteriorates the filter’s gain response. We should stress here that the nMOS switches are thick gate oxide devices that operate at 3.3 V (provided by the CMOS process employed) in order to avoid long-term reliability issues that would occur if thin gate oxide MOS were driven by 2.7 V. Also, it must be stated that the 2.7-V supply is used solely to drive the gates of the MOSFET switches. Accordingly, the power consumption owed to this supply is virtually zero. The generation of the necessary 2.7-V gate voltage from a single 1-V supply is possible by means of a charge pump circuit [13], hence only one supply would suffice for the realization of the design. III. OPERATIONAL AMPLIFIER DESIGN The active elements of the filter are five identical operational amplifiers. Each amplifier operates on 1-V supply and consumes 0.74 mA. It consists of a differential input stage, an output stage, and a common-mode feedback (CMFB) circuit, as outlined in Fig. 5. In order to expand the amplifier’s bandwidth without sacrificing gain and consuming more current, a new compensation technique is adopted, based on the same principle as in [21]. The idea described there, is the placement of two cross-coupled capacitors between the input differential pair and the output buffer. These capacitors act as a negative capacitance connected of in parallel with the parasitic base-collector capacitance the input transistors, thus evoking an “anti-pole-splitting” action that augments the amplifier’s gain-bandwidth product. The proposed compensation technique of this paper exploits the “anti-pole-splitting” idea, but in a different way than the technique in [21]. The compensation capacitors ( ) are cross connected to the outputs of the first and second stages of the amplifier, combined with the classic Miller RC compensation network. This practice yields not only an “anti-pole-splitting” action, but also a “phase-controlling” action, that holds the output phase away from 180 for frequencies spanning far beyond the unity gain frequency, thus providing extra bandwidth and securing adequate phase margin. For an in depth discussion of the technique, the simplified ac equivalent model of the ampli, depicted fier in the presence of an output capacitive load in Fig. 6, is considered. The differential open-loop voltage gain is denoted in (9), shown at the bottom of the next page, except for a third-order

2000


Fig. 5. Operational amplifier schematic.

Fig. 6. AC equivalent model of the amplifier with an output load included.

term in the denominator, which for the sake of simplicity is ignored, since its contribution is marginal at the frequency range of interest compared to lower order terms. This term will and strongly be discussed later on. Moreover, the factors depend on parasitic capacitances, as well as on the output load, is kept small. The analysis that and are negligible if follows presumes that the values of capacitors and are substantially greater than the values of the circuit’s parasitic capacitances.

Equation (9) indicates that as long as the coefficients of the first- and second-order terms of the denominator are positive, the poles reside on the left-half plane, hence the amplifier is stable. Consequently, in order to prevent oscillations the subsequent two relations must be valid: (12) (13)

(9)

(10) (11)


2001

safety margin for stability and guarantees a bandwidth close to the optimal value. We now focus our discussion on the numerator of (9). From , we can rewrite (9) as the previous analysis and ignoring

(15) As it is evident, the transfer function contains three zeros. One is located in the right-half plane at extremely high frequencies. The other two lie on the left-half plane and are

Fig. 7. Root locus for the denominator of (9), as a function of C .

(16)

The above inequalities were derived under the assumption that terms and are insignificant. In practice, their existence grants a safety margin, since they are positive, which allows (12) and (13) to hold as equalities. It is important to comment here on on the stability of the amplifier. Observation of the role of (10) and (11), shown at the bottom of the previous page, reveals is added positively in the terms and . Therefore, that its existence actually enhances stability as it expands the safety margin for which the amplifier stays stable in an open-loop configuration. Assuming that the aforementioned coefficients are positive, increases to then if the value of the compensation capacitor a degree that keeps the discriminant of the denominator positive, the two poles move towards each other on the real frequency axis. The dominant pole moves to higher frequencies and starts to approximate the second pole, which shifts to lower frequengrows further, the discriminant becomes negative cies. If and the poles depart from the real axis developing into complex conjugate, but until these coefficients turn negative the poles remain on the left-half plane. Fig. 7 depicts the root locus of the , for given values of denominator of (9) as a function of and . We should note here that can be about 15% greater than (selected value 0.5 pF) without stability problems, as simulations manifest, due to the contribution of term , which cannot be totally neglected. Also, it is observed that beyond a certain the poles approach the origin and the bandwidth value of decreases. The quality factor of the amplifier can easily be calculated from (9) and is given below:

(14) The maximum bandwidth without peaking is accomplished for a quality factor and, for the selected values of and in the design, this happens for . A value of equal to was selected for the amplifier since it provides a

It is obvious that these two zeros are on the real frequency . The third-order coefficient that was omitted axis if in (9) is

(17) It can be proven that, as increases, the third pole moves to lower frequencies. From (15), it accrues that larger values for generate wider bandwidth as the two more significant poles shift to higher frequencies. In addition, considering (12) we select . Therefore, (16) creates a double zero at frequency . In practice, there might still be a minor imaginary part in (16) for the chosen value of , but this has a negligible effect in our investigation. Also, disregarded parasitic capacitances have as a result these two zeros and the third pole to appear at rather lower frequencies than our analysis suggests. One last remark is that the dependence of the zeros on is much stronger than that of the two dominant poles. This imparts more flexibility to the positioning of the zeros in the frequency compensation procedure, as they can be moved without altering the location of the two poles. Practically, because of the term , the value of can be a little greater than without loss of stability. This double zero features a very important characteristic. It adds positively to the phase response, thus moving the 180 intersect at a much higher frequency. Fig. 8 illustrates a comparison of the gain and phase achieved when the above described technique and the classic pole-splitting method are applied to the amplifier of Fig. 5. The amplifier core is identical in both cases except for the elements reported in Table I. We define the minimum phase presented in this table as the minimum distance (occurring below ) between the phase curve and the 180 line. The proposed topology offers a 20 times increase in the ) with respect frequency of the amplifier’s dominant pole ( to the classic RC approach for the same current dissipation. The profit in open-loop gain at 10 MHz is 23 dB. The unity gain frequency is of lesser importance for the filter performance.

2002

Fig. 8. Amplifier (a) gain and (b) phase accomplished with the proposed technique and the conventional RC compensation network.

TABLE I SIMULATION RESULTS OF THE COMPARED COMPENSATION TECHNIQUES

At this point, a critical remark must be made, regarding the phase response of this work’s amplifier. As seen from Fig. 8 and Table I, the phase margin (the amount by which the phase is above 180 ) is 53 , just 1 less than the one of the at conventional amplifier. The phase of the proposed technique is below the unity non-monotonic, showing a minimum of gain frequency , but this is not the relevant phase to consider for stability, as can be clearly deduced from a Nyquist plot. Of course, this minimum raises questions about the possibility of ringing or overshoot in the filter’s response. However, such phe-


nomena did not surface as will be shown in Section V, where experimental results are provided. Above all, the presented compensation method is much less susceptible to process variations than the pole-splitting approach. Based on (13), we conclude that in open-loop configuration, deviations in capacitor values do not lead to instability as long as their ratio remains constant. Phase margin and the minimum phase are dependent on capacitor ratios rather than absolute values. Resistor tolerances of 20% cause an aggravation of only around 4 in phase margin and minimum phase, as it stems from simulations. On the other hand, in the classic Miller compensation technique the decline of phase margin was 22 for the same amount of resistor tolerances. From the above, we interpret that the non-monotonicity in the phase response of our technique does not endanger stability. In any case, extensive simulations were executed with the amplifier in closed-loop embedded in the filter. These involved ac analyses to measure phase margin in all of the filter’s amplifiers [22], corner analyses, transient simulations including start-up tests and pulse inputs, etc. None of them exposed stability problems. to be As mentioned earlier in this chapter, we selected equal to . This provides an almost optimal bandwidth and a slightly improved phase margin. Therefore, simulations on the amplifiers of the various filter stages showed that the worst phase margin and minimum phase in corner cases are no less than 40 and 25 , respectively, whereas in typical case they vary between 45 —62 and 27 —34 , correspondingly. The tests were performed for all of the filter’s configurations. The proposed compensation technique drastically improved the amplifier’s frequency behavior to the benefit of the filter performance. The filter’s linearity is improved and so does the frequency response. Simulations revealed that using the amplifier with the proposed technique in the filter, provides significant improvement in both in-band and out-of-band IIP3 performance compared to the conventional approach. More specifically, this performance gain increases as the two input tones move higher in frequency. Close to the cut-off frequency of the filter the enhancement is 8 dBm. Measurements agreed with simulation results, within a 4 dB maximum deviation, in in-band IIP3 performance. Another interesting advantage of this work’s compensation technique over the conventional pole-splitting method is that it notably mitigated the filter’s passband ripple. To conclude our discussion on the operational amplifier we will comment briefly the biasing of the input stage and the is used to CMFB circuitry. As Fig. 5 demonstrates, resistor bias the differential input pair instead of a MOS current source. The above approach is necessary as a consequence of the 1-V supply, which does not accommodate three stacked transistors operating in saturation region. The cost is deterioration in the common-mode rejection ratio (CMRR) of the circuit. Despite this fact, measurements indicated that the CMRR of the filter is at satisfactory levels. The input of the amplifier in the filter’s first stage is ac courequired purely for the meapled by external capacitors surement setup. If the filter is to be incorporated in an integrated system, its input can be simply dc coupled to the preand in this amceding stage. The gates of transistors


2003

Fig. 10. Block diagram of the automatic tuning scheme.

Fig. 9. Bias method for the first amplifier.

plifier are biased with the help of the circuit in Fig. 9. Using an external voltage reference, a conversely proportional to absois created and mirrored lute temperature (CTAT) current in a commercial version of the chip to these transistors. would be generated by a bandgap voltage reference. For simplicity reasons the external voltage emulates the bandgap reference in our design. Simulations uncovered that the fluctuations over process and/or temperature drifts are kept in a of level that preserves the bandwidth and gain characteristics of the amplifier virtually unaffected. The input of the remaining filter amplifiers is biased from the output of the preceding amplifier. Notice that the dc level at the input and output stages of the amplifiers is the same because of the CMFB circuit. The CMFB circuitry is depicted at the right-hand side of is in the region of half the supply voltage Fig. 5. Voltage (typically, 500 mV) and is produced as shown in Fig. 9 (it is of ). The same current flows through and equal to only if their is equal. Given the fact that remains constant, then the half sum of the voltage at the two output for a current equilibrium in stages must equalize and . Hence, the loop that closes through , , , , and maintains the dc output voltage equal . This loop must have small gain to be wideband and to and improve loop phase margin so stable. Capacitors also that common mode oscillations cannot be sustained. enhances the bandwidth of the CMFB loop in order to have sufficient CMRR at high frequencies.

Fig. 11. Oscillator having a period proportional to the RC product.

IV. DIGITAL AUTOMATIC TUNING SCHEME The digital automatic tuning scheme is presented in Fig. 10. Its main structural blocks are a reference oscillator, a limiter, an external clock, a downcounter and a register. Under nominal conditions, the oscillator frequency is 500 kHz, while the external clock frequency is always kept constant and equal to 32 MHz. The external and the reference frequencies must have a ratio of 64 for reasons clarified later in this section. The most important merit of this approach compared to the ones reported in [15] and [18] is that it corrects the oscillator frequency and the filter characteristics in one iteration of the algorithm, instead of gradually approaching the right oscillating period. The concept upon which the algorithm of the tuning scheme relies is that the period of an oscillator, as the one represented product. As a result, any in Fig. 11, is proportional to the change in the value of this product would lead to fluctuation of

Fig. 12. Chip microphotograph.

the oscillating frequency. Needless to say, the product value affects the time constant of the filter in a similar manner if the passive components of the oscillator are of the same material with those comprising the filter. Accordingly, a measurement product value that maintains the freand modification of the quency of the oscillator equal to 500 kHz, would also correct the characteristics of the filter. The system in Fig. 10 performs this adjustment by means of an algorithm that is elucidated below. It can easily be proven that the circuit in Fig. 11 is governed by a relation of the form (18)

2004


Fig. 13. Filter gain response in four modes: (a) Chebyshev, 5 MHz; (b) Elliptic, 5 MHz; (c) Chebyshev, 10 MHz; (d) Elliptic, 10 MHz.

where . Therefore, it is obvious that oscillations are sustained, having a period . The resistors of the os, thus allowing cillator are constructed by the unit resistor the control of the period with a 3-bit digital word. The amplifiers are identical to the ones deployed in the filter. The selection of the frequency is a compromise between the desirable accuracy and the value of the elements (especially the capacitors) of the oscillator. Greater periods are sharply achieved, but impose larger values for the components. Hence, the oscillator period was opted to be 2 s. The optimal case would be for the oscillator frequency to fall outside the passband of the filter. However, the large bandwidth of the filter does not permit this as there is considerable error in the oscillator period. Thus, actions should be taken during the design and layout process to minimize oscillator feed-through to the main filter. Some of these actions entail the use of guard rings around the digital and analog parts of the design, placing the digital and analog blocks as distantly as possible, employing separate power supplies, etc. Furthermore, the signals that flow into the filter and the oscillator from the digital logic circuitry pass through buffers before reaching the analog circuits. As outlined in Fig. 10, the output of the oscillator and an external clock are connected to the enable (EN) and clock (CLK) inputs of the downcounter, respectively. Prior to each iteration, the downcounter is initialized in the value 32 and

under nominal conditions in each oscillator period decrements 32 times. Therefore, if the oscillator period is greater than the nominal, the downcounter will reach negative values, but if it is lower, the downcounter will stop before it gets to zero. The outcome of the addition of the downcounter’s final value and the digital word that controls the resistors of the filter provides the new digital word that will be fed into the resistors. The altering of the resistor value produces an oscillating period that is approximately 2 s. Consequently, until a significant change in circuit conditions arises, the digital control word remains the same. Actually, in the addition, the MSB of the downcounter is disregarded (its only aim is to generate the value 32) and the residual bits are rounded so as to immune the system to slight deviations in the frequency of the oscillator. One important observation is that care should be exercised in the design to certify that the duty cycle of the oscillator is 50%, in order for the tuning scheme to operate aptly. An alternative approach is to connect the output of the on-chip oscillator to the CLK input of the downcounter and use an external clock that is 64 times slower than the oscillator as the EN input. In this case, the duty cycle of the oscillator is of no importance, whereas the external clock duty cycle might be somewhat easier to manage. However, the price to pay is that both frequencies fall inside the passband of the filter.


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TABLE II LINEARITY RESULTS

TABLE III INTEGRATED OUTPUT NOISE (PASSBAND)

Fig. 14. Group delay of the filter. TABLE IV SPURIOUS FREE DYNAMIC RANGE

TABLE V PSRR OF THE FILTER

Fig. 15. CMRR of the filter.

V. EXPERIMENTAL RESULTS A filter prototype was fabricated in a 0.12- m CMOS process. A chip microphotograph is illustrated in Fig. 12. The main filter occupies 0.17 mm , the oscillator 0.065 mm , and the digital logic 0.014 mm . The main filter and the oscillator operate on a 1-V supply and draw 4.6 mA and 1.5 mA, respectively. Measurements indicated that experimental results closely match the simulated ones. The frequency tuning range for the filter is 3.6 MHz–7.4 MHz in the 5 MHz configuration, and 7.3 MHz–14.7 MHz in the 10-MHz mode. Fig. 13 illuminates how the gain varies as the tuning word changes. A peaking is observed in the 10-MHz mode as the corner frequency of the filter increases. However, it is not severe for the nominal tuning word, but merely for words that set resistor values smaller than the nominal, for which the cut-off frequency is beyond 10 MHz. The reference oscillator frequency was found to be roughly 510 kHz, a 2% deviation from 500 kHz. Moreover, the tuning error agrees with the theoretical one, predicted by (6). Fig. 14 displays the group delay in the four different filter configurations. In the Elliptic implementation, which is optimized

for group delay performance, the deviation is less than 4 ns throughout the passband. The CMRR of the filter is depicted in Fig. 15. The stopband attenuation for the Chebyshev filter measured at two times the corner frequency is 30 dB in both modes (5 MHz and 10 MHz). In the third-order Elliptic filter the was found to be 15 dB in both states. attenuation at Linearity results are given in Table II. The Elliptic filter is a little worse as far as linearity is concerned because it has not been optimized for dynamic range performance. The filter’s output noise (integrated in the passband), SFDR (at 2.5 MHz), and power-supply rejection ratio (PSRR) (for both VDD supply and VSS ground) are shown in Tables III–V, respectively. The AC response of the filter (Elliptic, 5 MHz) at four different temperatures is illustrated in Fig. 16. Due to the resistors’ small temperature coefficient ( 720 ppm C), the filter’s corner frequency deviates merely 3.6% for a 50 C temperature variation. Therefore, as a result of the tuning scheme’s 5% precision, the digital tuning word is adjusted only at temperatures exceeding 100 C. Before concluding this section, we should make a comment on the phase margin and minimum phase of the amplifier and their impact on the filter behavior. The simulated differential output of the filter (Elliptic, 10 MHz), for a square wave input

2006

Fig. 16. AC response of the filter (Elliptic, 5 MHz) at various temperatures. The number in brackets corresponds to the value of the tuning word used.


Fig. 18. A snapshot of the oscilloscope’s screen showing the filter’s (Elliptic, 10 MHz) output transient response to a square wave (200 mV , f = 1 MHz) input signal.

TABLE VI COMPARISON OF FILTER IMPLEMENTATIONS

Fig. 17. The filter’s (Elliptic, 10 MHz) simulated output transient response to a square wave (200 mV , f = 1 MHz) input signal for four amplifier implementations.

signal of 100-mV amplitude and 1-MHz frequency, is depicted in Fig. 17 for four different amplifier implementations: • conventional amplifier with pole-splitting technique possessing the characteristics reported in Table I; • ideal amplifier model (infinite gain and no poles); • amplifier with proposed technique having almost the same bandwidth as the adopted amplifier, but with 79 phase margin and 55 minimum phase; • adopted amplifier for the filter with 53 phase margin and 27 minimum phase. It is obvious, that the two amplifiers utilizingthe proposed compensation technique produce a transient response that is almost identical to the one of the ideal amplifier. The overshoot present is a characteristic of the transfer function of the filter, mainly attributable to its group delay characteristic, rather than amplifier owned. On the contrary, in the case of the conventional Miller compensated amplifier the overshoot is greater, meaning that its non-idealities affect to a larger extent the filter’s performance. It should be noted, that the modified amplifier (the one with 79 phase margin and 55 minimum phase) exhibits 7 dB less

TABLE VII COMPARISON OF VIDEO FILTER REQUIREMENTS AGAINST MEASURED PERFORMANCE OF THIS WORK’S FILTER (CHEBYSHEV, 5 MHZ)

gain and 10% raised power consumption with respect to the original amplifier. Moreover, it is somewhat inferior in terms of dynamic range, as well as noise performance due to intensified flicker noise. These trade-offs are required to increase its phase margin without altering bandwidth performance. Thus, we decided to implement the smaller phase margin version in order to additionally demonstrate the robust stability of the proposed compensation technique.


Fig. 18 demonstrates the filter’s measured differential output (Elliptic, 10 MHz), for a square wave input signal of 100-mV amplitude and frequency of 1 MHz (identical to the one applied in the simulation). As it is apparent, the overshoot is similar to the simulated, which implies that neither the phase margin nor the minimum phase of the manufactured amplifiers poses a problem to the filter operation. The filter’s (Elliptic, 5 MHz) performance is compared against previous realizations reported in the literature, in Table VI. The performance is evaluated by expanding the definition of the figure of merit (FoM) introduced in [12] and [13]:

where

stands for power dissipation. VI. CONCLUSION

An active-RC filter with modifiable transfer function and bandwidth was presented. The filter operates on a 1-V supply and dedicates a digital automatic tuning scheme to cancel its time constant variations. The amplifiers of the filter utilize a new compensation technique that yields extra bandwidth at no cost to current consumption. Experimental results verify the excellent linearity expected from the design and evidence a wide dynamic range. All the above constitute the filter practical for many applications. As an example, we mention that the 5-MHz Chebyshev filter meets the specifications of a consumer-quality filter for a PAL video system, as shown in Table VII [3]. Another application for the filter could be as a channel-select filter in a receiver, due to its reconfigurable bandwidth capability.

2007

[9] F. Krummenacher and N. Joehl, “A 4-MHz CMOS continuous-time filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 750–758, Jun. 1988. [10] M. Ismail, S. V. Smith, and R. G. Beale, “A new MOSFET-C universal filter structure for VLSI,” IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 183–194, Feb. 1988. [11] R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, “Low-voltage analog filters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 42, no. 11, pp. 827–840, Nov. 1995. [12] Y. P. Tsividis, “Integrated continuous-time filter design – An overview,” IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 166–176, Mar. 1994. [13] A. Yoshisawa and Y. P. Tsividis, “Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 357–364, Mar. 2002. [14] T. Oshima, K. Maio, W. Hioe, and Y. Shibahara, “Novel automatic tuning method of RC filters using a digital-DLL technique,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2052–2054, Nov. 2004. [15] H. Huang and E. K. F. Lee, “Design of low-voltage CMOS continuoustime filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1168–1177, Aug. 2001. [16] A. M. Durham and W. Redman-White, “Integrated continuous-time balanced filters for 16-b DSP interfaces,” IEEE J. Solid-State Circuits, vol. 28, no. 7, pp. 835–839, Jul. 1993. [17] A. M. Durham, J. B. Hughes, and W. Redman-White, “Circuit architectures for high linearity monolithic continuous-time filtering,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 9, pp. 651–657, Sep. 1992. [18] A. A. Emira and E. Sánchez-Sinencio, “A pseudo differential complex filter for Bluetooth with frequency tuning,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 10, pp. 742–754, Oct. 2003. [19] J. O. Voorman, A. van Bezooijen, and N. Ramalho, “On balanced integrator filters,” in Integrated Continuous-Time Filters: Principles, Design, and Applications, Y. P. Tsividis and J. O. Voorman, Eds. New York: IEEE Press, 1993, pp. 66–86. [20] Y. P. Tsividis, Mixed Analog-Digital VLSI Devices and Technology: An Introduction. New York: McGraw-Hill, 1996, pp. 205–257. [21] M. Vadipour, “Capacitive feedback technique for wideband amplifiers,” IEEE J. Solid-State Circuits, vol. 28, no. 1, pp. 90–92, Jan. 1993. [22] R. D. Middlebrook, “Measurement of loop gain in feedback systems,” Int. J. Electron., vol. 38, pp. 485–512, Apr. 1975.

REFERENCES [1] W. Hioe, T. Oshima, Y. Shibahara, T. Doi, K. Ozaki, and S. Arayashiki, “0.18-m CMOS Bluetooth analog receiver with 88-dBm sensitivity,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 374–377, Feb. 2004. [2] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, and K. A. I. Halonen, “A 2-GHz wideband direct conversion receiver for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1893–1903, Dec. 1999. [3] S.-S. Lee and C. A. Laber, “A BiCMOS continuous-time filter for video signal processing applications,” IEEE J. Solid-State Circuits, vol. 33, no. 9, pp. 1373–1382, Sep. 1998. [4] W. Dehaene, M. S. J. Steyaert, and W. Sansen, “A 50-MHz standard CMOS pulse equalizer for hard disk read channels,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 977–988, Jul. 1997. [5] I. Mehr and D. R. Welland, “A CMOS continuous-time G -C filter for PRML read channel applications at 150 Mb/s and beyond,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 499–513, Apr. 1997. [6] J. Silva-Martínez, J. Adut, J. M. Rocha-Perez, M. Robinson, and S. Rokhsaz, “A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 216–225, Feb. 2003. [7] J. Silva-Martínez, M. S. J. Steyaert, and W. Sansen, “A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1843–1853, Dec. 1992. [8] J. M. Khoury, “Design of a 15-MHz CMOS continuous-time filter with on-chip tuning,” IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1988–1997, Dec. 1991.

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Athanasios Vasilopoulos (S’05) received the diploma degree in electrical and computer engineering from the National Technical University of Athens (NTUA), Greece, in 2001. He is currently working toward the Ph.D. degree at the NTUA. The subject of his thesis is the design of low-voltage, low-power analog circuits for radio transceivers. His research interests are in the areas of RF and baseband IC design for telecommunication systems, and CAD tools for microelectronic design.

Georgios Vitzilaios received the B.Sc. degree in physics from the University of Warwick, U.K., in 1998 and the M.Sc. and DIC degrees in analog and digital integrated circuit design from Imperial College, U.K., in 1999. He is currently working toward the Ph.D. degree at the National Technical University of Athens (NTUA), Greece. His main research interests focus on low-noise amplifier design and optimization for low-voltage, low-power radio transceivers in CMOS technology. He has been involved in the design of several analog building blocks for radio transceivers. His current interests are on linearization techniques of CMOS RF blocks for broadband wireless applications.

2008

Gerasimos Theodoratos (S’06) received the diploma degree in electrical and computer engineering from the National Technical University of Athens (NTUA), Greece, in 2001. He is currently working toward the Ph.D. degree at the National Technical University of Athens (NTUA), Greece. His thesis focuses on RF integrated mixer design and analysis of nonlinear behavior of RF structures. He has also been involved in the design of several analog circuits for radio transceivers. His current interests include design, analysis, and linearity optimization of RF blocks in CMOS technologies.


Yannis Papananos (S’83–M’96–SM’98) received the Dipl. Eng. degree in electrical engineering from the National Technical University of Athens (NTUA), Greece, in 1983, the M.S. degree from Columbia University, New York, in 1984, and the Dr. Eng. degree from the National Technical University of Athens in 1988. In 1992, he joined the Department of Electrical and Computer Engineering of the NTUA, where he is now Professor. He is the author of three books and numerous technical papers. His research interests are in the areas of analog, mixed signal, and RF IC design, and CAD for microelectronic design.