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Abstract—A voltage reference of low supply voltage, low power consumption, no resistors and high threshold voltage devices has been proposed and simulated ...
A Low-Voltage, Low-Power Subthreshold CMOS Voltage Reference without Resistors and High Threshold Voltage Devices Jun Zhang*, Yunling Luo*, Qiaobo Wang, Jingjing Li, Zhuqian Gong, Hong-Zhou Tan**, Yunliang Long Department of Electronics and Communication Engineering Sun Yat-sen University Guangzhou, P. R. China E-mail: {zhangj89, luoyunl2} @mail2.sysu.edu.cn*, [email protected]** Abstract—A voltage reference of low supply voltage, low power consumption, no resistors and high threshold voltage devices has been proposed and simulated using 0.18μm technology in this paper. The range of supply voltage is from 0.9V to 3V with a maximum current consumption of 532.9nA and a line sensitivity of 6.7ppm/V. Temperature compensation is enhanced by taking body effect into consideration, and a temperature coefficient lower than 25ppm/°C is achieved in most cases. The power supply rejection ratio without any filtering capacitor is -45dB at 100Hz and -15dB at 10MHz.

I.

consumption is presented in this paper. The body effect cancellation technique has been implemented and a steady temperature coefficient is achieved. II.

⎛ V − VTH ⎞ I DS = μn Cox (η − 1) K N VT 2 exp ⎜ GS ⎟. ⎝ ηVT ⎠

INTRODUCTION

The development of small area, low voltage, low power and high performance power management devices based on a standard CMOS technology are promoted resulting from the widespread use of portable devices. And the voltage reference circuit plays an important role in the family of power management devices, therefore, the research and design of small area, low supply voltage, low quiescent current and high precision voltage reference circuit is gaining more and more attention. By using a weighted difference between the gatesource voltage of two MOSFETs operating in subthreshold region (ΔVGS), one can obtain a thermal voltage (VT) term with a positive temperature coefficient (TC), while the threshold voltage (VTH) of transistor has a negative TC, a temperature independent reference voltage could be generated by interaction of the positive and negative TC [1], [2]. Resistors using in voltage reference leads the tradeoff between the area and quiescent current, by utilizing a MOSFET biased in deep-triode region instead of conventional resistors, area and quiescent current could be decreased significantly [3], but these architecture could not be operated with a supply voltage lower than sub-1V. Ref. [4], [5] could satisfy the requirement for no resistor and low supply voltage, however, the using of high threshold voltage (HVT) devices limits their application. To solve these problems, based on SMIC 0.18μm CMOS technology, a novel voltage reference circuit without resistors and HVT devices that could be operated with a supply voltage lower than sub-1V and with sub-microwatt power

(1)

Where μn is the carrier mobility, Cox is the gate-oxide capacitance, η is the subthreshold slope factor and KN = (W/L)N is the aspect ratio of NMOS while the thermal voltage VT = κBT/q, where κB is the Boltzmann constant, T is the absolute temperature and q is the elementary charge. The schematic of the voltage output structure is showed in Fig. 1 (a), output voltage Vref is given by Vref = VGS 4 + VGS 5 .

(2)

Working MOSFET in deep-triode region, traditional cumbersome resistor in voltage reference could be replaced, and the equivalent resistance R6 of NMOS6 could be given by R6 =

1

μn Cox K N 6 (Vbias − VTH 6 )

.

(3)

Where Vbias = VGS6 is the voltage biasing NMOS6 in deeptriode region. As shown in (3), one could increase R6 by reducing the aspect ratio of NMOS6 in order to minimize the power dissipation. If NMOS4, 5 work in subthreshold region, as it follows from (1) and (3), (2) could be rewritten as

This work was supported in part by NSFC-Guangdong Key project under Grant number U0935002.

978-1-4577-1729-1/12/$26.00 ©2012 IEEE.

OPERATING PRINCIPLE

When a N-type MOSFET (NMOS) operates in subthreshold region, and the drain-source voltage VDS > 4VT, IDS is almost independent of VDS and given by

384

Vref = ΔVTH + ηVT ln

I in I out . SN K N 4 K N 5 2

(4)

(a)

(b)

Figure 1. (a) Schemetic of voltage output circuit. (b) Schemetic of current source for body effect cancellation.

Figure 2. Full schemetic of the proposed voltage reference circuit.

Where ΔVTH = VTH4+VTH5*, SN = μnCox(η-1)VT2, Iout = μnCoxKN6VGS4(Vbias-VTH6). Based on a weighted ΔVGS, one can use the schematic showed in Fig. 1 (b) as the current source to generate Iin. A self-biased voltage reference circuit is achieved by combination of the voltage output circuit and the current source circuit. According to the expression of Vref, selecting Iin and Vbias appropriately will achieve a cancellation of parameters depended on temperature in the logarithmic function. Hence, ΔVTH has a negative TC, and VT has a positive TC, and the temperature dependence of Vref could be removed by adjusting the size of the transistors. A start-up circuit is used to ensure the normal operation condition could always be achieved. The full schematic of proposed voltage reference circuit is showed in Fig. 2, the following section will describe the operation mechanism in detail. III.

I = μn Cox (η − 1)

⎛ V *⎞ K N1 K N 3VT 2 exp ⎜ − TH 1 ⎟ . KN 2 ⎝ ηVT ⎠

Where VTH1* is the threshold voltage of NMOS1 considered the body effect when VTH2 = VTH3 is assumed. Supposing X= KP5/KP2 is the ratio of current mirror, here KP = (W/L)P is the aspect ratio of PMOS. From the I-V characteristic of MOSFET in subthreshold region and (5), we could express VGS4 as VGS 4 = VTH 4 − VTH 1* + ηVT ln

Vbias = VGS 7 = VTH 7 +

A. Reference Voltage In Fig. 2, the difference between gate-source voltage of NMOS2 and NMOS1 equal to the gate-source voltage of NMOS3, then current I could be expressed as

XK N 1 K N 3 . KN 2 KN 4

(6)

Because of KP3=YKP4, and NMOS7 is biased in saturation region by Io, Vbias is given by

PROPOSED VOLTAGE REFERENCE CIRCUIT

The proposed CMOS voltage reference circuit showed in Fig. 2 consists of a start-up circuit, a current source circuit and a voltage output circuit. All the MOSFETs have a standard threshold voltage (STV). Since the substrate of NMOS should be connected to ground for N-well technology, the impact of body effect must be considered for improving the range of supply voltage and the independence of temperature variation. The start-up circuit consists of PMOSS1 and NMOSS1, 2, while the entire circuit is working properly, the quiescent current of this circuit is negligible. The current source circuit consists of NMOS1~3 and PMOS1, 2 where PMOS1, 2 are used as the current mirror to ensure the current in each branch is proportional to the other. The voltage output circuit consists of NMOS4~7 and PMOS3~5. Here PMOS3~5 are also functioned as current mirror and NMOS7 that is biased in saturation region by Io, generates Vbias for NMOS6. Impose 2(Vbias-VTH6) >> VDS6 = VGS4 for this Vbias, then NMOS6 is biased in deep-triode region. Therefore, all the MOSFETs work in the subthreshold region except for NMOS6, 7.

(5)

2YI o . μn Cox K N 7

(7)

From (3), (6) and (7), we can obtain that Io is Io =

VGS 4 YK N 6 2 = 2μ n Cox VGS 4 2 . R6 KN 7

(8)

Substituting (5) and (8) into (4), where the current X*I and Io correspond to Iin and Iout respectively, Vref could be rewritten as VREF = VTH 4 + VTH 5* − VTH 1*

+ηVT ln B.

2 XYK N 1 K N 3 K N 6 2VGS 4 2 . K N 2 K N 4 K N 5 K N 7 (η − 1) VT 2

(9)

Impact of Body Effect The expression of VTH* is given by[6] VTH * = VTH + γ

(

)

2Φ F + VSB − 2Φ F .

(10)

Where γ is the body-effect constant, ΦF is the Femi potential of substrate, VSB is the source-bulk voltage, if VSB = 0, then VTH* = VTH. Following[7], VTH could be written as a linear function of temperature

385

VTH = VTH (T0 ) + k (T − T0 ) .

(11)

Where T0 is the reference temperature, a negative constant k is the TC of VTH. For the proposed circuit in this paper, since ΦF > VSB, the second term in (10) could be approximated as [8], [9]

γ

(

)

2Φ F + VSB − 2Φ F ≈

γ VSB = (η − 1) VSB . 2 2Φ F

(12)

Eq. (11) and (12) are substituted into (10), rewriting VTH* as

VTH * = VTH (T0 ) + k (T − T0 ) + (η − 1) VSB .

(13)

And VSB1, VSB5 could be written as VSB1 = VGS 3 = VT ln

K N1 , KN 2

1 ⎡ ⎤ ⎛ K N 1 ⎞η K N 3 ⎥ ⎢ = ηVT ln X ⎜ . ⎟ ⎢ KN 2 ⎠ KN 4 ⎥ ⎝ ⎣⎢ ⎦⎥

VSB 5 = VGS 4

(14)

(15)

C. Temperature Compensation Assuming the TC of VTH related to all N-type MOSFETs equal to each other, that is k1 = k2 = k3 = k4 = k5 = k6 = k, and by using (13), (14) and (15) in (9), we find that Vref becomes Vref = VTH (T0 ) + k (T − T0 ) + (η − 1) ΔVSB ⎡S ⎤ +ηVT ln ⎢ N 1 ln 2 ( S N 3 ) ⎥ . S ⎣ N2 ⎦

(16)

simulations are carried out with the aid of SPICE simulator using SMIC 0.18μm Mixed Signal/RF technology. To study the dependence of the output voltage on process variation, Monte Carlo simulations are performed assuming related process parameters obey a Gaussian distribution condition on the typical process corner and room temperature. The results for 300 runs are depicted in Fig. 3.There are 224 samples whose TC is lower than 50ppm/°C, while 23 samples higher than 150ppm/°C. The mean value of the output voltage μ is 591.6mV and the standard deviation σ is 20mV, the coefficient of variation σ/μ is 3.4%. As it is showed in Fig. 4, when VDD = 0.9V, which is the minimum supply voltage, the TC is 16.1ppm/°C. When VDD = 3V, which is the maximum supply voltage, the TC increases to 45.6ppm/°C. Fig. 5 shows that at room temperature the overall current consumption varies from 368nA to 429nA with the supply voltage varies from 0.9V to 3V. At the temperature of 80°C the overall current consumption is 532.9nA with maximum supply voltage and 470.7nA with minimum supply voltage. Fig. 6 shows that the power supply rejection ratio (PSRR) is -45dB at frequency 100Hz and -15dB at 10MHz at room temperature with supply voltage of 0.9V and without any filtering capacitor. Fig. 7 shows, the output voltage of the reference has a difference of 8.3mV with the supply voltage ranging from 0.9V to 3V, that implies the line sensitivity is 6.7ppm/V. Table I concludes the main characteristic of the proposed voltage reference circuit. Thanks to resistor-free, voltage reference in this paper has a lower power consumption than circuit proposed in [2]. Comparison with [3], a lower supply voltage can be achieved by using less stacked-cascode connection. Because of no HVT devices, the proposed voltage reference has a wider application than circuit proposed in [4], [5].

Where ΔVSB = VSB5-VSB1 = ηVTln(XKN3/KN4), SN1 = 2XYKN1KN3KN62η2, SN2 = KN2KN4KN5KN7(η-1), SN3 = X(KN1/KN2)1/η(KN3/KN4). From (16), the TC of Vref could be given by ∂ΔVSB = k + (η − 1) ∂T ∂T +η

⎡S ⎤ ln ⎢ N 1 ln 2 ( S N 3 ) ⎥ . q ⎣ SN 2 ⎦

κB

100

100

200 300 400 Temperature coefficient (ppm/°C)

500

(a) 140 120 100

(18)

That is, properly adjusting the size of the transistors, the output reference voltage becomes independence of temperature variation. IV.

150

0 0

SIMULATION RESULTS

Samples

⎡S ⎤ = ln ⎢ N 1 ln 2 ( S N 3 ) ⎥ . ηκ B ⎣ SN 2 ⎦

200

50

(17)

From (17) and the expression of ΔVSB, one can simply set KN3 = KN4 to eliminate the impact of body effect from the TC. A zero TC of output voltage Vref could be achieved under the condition of qk

TC(avg)=53 ppm/°C TC(min)=15.2 ppm/°C TC(max)=460.1 ppm/°C

250 Samples

∂Vref

300

80 60 40 20 0 520

540

560

580 600 620 Reference voltage (mV)

640

660

(b)

In order to evaluate the performance of the proposed voltage reference and validate the design procedure, a series of

386

Figure 3. Monte Carlo simulation, (a) distribution of TC. (b) distribution of Vref at 27°C

0.6

VDD=0.9V VDD=1.2V VDD=1.8V VDD=2.5V VDD=3V

0.602 0.6 0.598

Reference voltage (V)

Reference voltage (V)

0.604

0.596 0.594 0.592 0.59 -20

0

20 40 Temperature (°C)

60

Ref. [2]

Ref. [3]

Ref. [4]

Ref. [5]

CMOS technology

SMIC 0.18μm

TSMC 0.18μm

0.35μm

AMS 0.35μm

UMC 0.18μm

T range (°C)

-20/80

-20/140

-20/80

0/80

0/125

TC (ppm/°C)

16

193

7

10

142

0.9/3

0.9/2.5

1.4/3

0.9/4

0.45/2

532.9 (max)

3300@ 0.85V

214@ 1.4V

55@ 4V

8@ 1.8V

222

745

670

263.5

6.7

5.6

20

2.7

3.9

PSRR (dB)

-45@ 100Hz

N.A.

-45@ 100Hz

Other devices

None

Resistors

None

-47@ 100Hz HVT devices

-45@ 100Hz HVT devices

[2]

[3]

[4] -7

x 10 VDD=0.9V VDD=1.2V -5 VDD=1.8V VDD=2.5V VDD=3 -4.5

Total quiescent current (A)

-5.5

[5]

[6] -4

[7]

-3.5

60

80

[8]

Figure 5. Supply current versus temperature for different supply voltages -10

[9]

PSRR=-45dB@100Hz PSRR=-15dB@10MHz

PSRR (dB)

-20

-30

-40

-50 10

2

10

4

10 Frequency (Hz)

6

10

1

1.5 2 Supply voltage (V)

2.5

3

CONCLUSION

REFERENCES

591.6

20 40 Temperature (°C)

0.592

A low supply voltage, low power consumption voltage reference has been proposed and simulated in 0.18μm technology. Temperature dependence of the parameters is suppressed by body effect cancellation technique. Low quiescent current, no need of resistors and high threshold devices make this voltage reference especially applicable to such cost and energy constraint scenarios.

[1]

0

0.594

V.

This work

-3 -20

0.596

Figure 7. Output voltage versus VDD

COMPARISON WITH PREVIOUS VOLTAGE REFERENCE

Supply voltage (V) Supply current (nA) Voltage reference (mV) Line sensitivity (ppm/V)

0.598

0.59 0.5

80

Figure 4. Temperature dependence of Vref for various VDD.

TABLE I.

Line sensitivity=6.7ppm/V

8

Figure 6. PSRR at room temperature for VDD=0.9V

387

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