PRIME 2013, Villach, Austria
Session W2A – Power Management
A Nano-power Power Management IC for Piezoelectric Energy Harvesting Applications M. Dini, M. Filippi, M. Tartagni, A. Romani Department of Electrical, Electronic and Information Engineering "Guglielmo Marconi" (DEI) University of Bologna Via Venezia 52, 47521 Cesena, Italy
[email protected]
Abstract—This paper describes a power management IC for piezoelectric energy harvesting which integrates an active ACDC converter with residual charge inversion together with a smart self-supply architecture to speed up the start-up phase and increase harvesting effectiveness. Due to randomness of available power and to its typical intrinsic limitation to tens of μW the IC has been carefully designed to reduce quiescent current down to 150 nA while the efficiency is estimated to be at least 81%. Moreover this allows the system to be fully autonomous even with very low input energy. The IC has been designed in a 0.32 µm BCD technology from STMicroelectrics and its area is 4.6 mm2. Keywords— energy harvesting; piezoelectric transducer; nanopower circuits; synchronous charge extraction; energy storage.
I.
INTRODUCTION
Energy harvesting has been widely explored in the last years with the purpose of developing a new class of autonomous systems, supplied by environmental energy. Vibrational energy is widely diffused, and piezoelectric transducers allow to achieve high power density during energy conversion [1]. Conversion schemes based on synchronous electrical charge extraction (SECE) [2-4] have been extensively studied (Fig. 1(a)) and have proved to be more efficient than passive interfaces (e.g. based on diode rectifiers). In many foreseen applications of autonomous systems it is crucial to store high amounts of energy, for example by using supercapacitors in order to compensate for fluctuations of harvested energy while sustaining load power requirements. Moreover, storing large amount of energy on small capacitances leads to voltage levels which are not compatible with new CMOS technologies. However, for self-powered systems, a passive (i.e. not actively controlled) conduction path, as could be a simple diode, is required to charge CST up to the minimum necessary voltage for active operations. In case of supercapacitors this phase can be very long, reducing the overall effectiveness of the energy harvester. In this work a new highly efficient IC for piezoelectric energy harvesting and power management is presented. The IC is fully autonomous and presents intrinsic nano-power consumption. The proposed architecture, which introduces residual charge inversion and a two-way storage topology, implements optimized power management policies.
Fig. 1. (a) block diagram of a SECE converter, (b) equivalent circuit during first phase of SECE, (c) equivalent circuit during second phase of SECE, (d) qualitative waveforms under ideal conditions.
Fig. 2. (a) NVC schematic with piezoelectric transducer connected, (b) qualitative waveforms of NVC input and output.
II.
This research was funded by the European Community's FP7 2007-2013 under grant agreement Nanofunction no. 257375 and by the ENIAC Joint Undertaking under grant agreement END no. 120214.
978-1-4673-4581-1/13/$31.00 ©2013 IEEE
INPUT STAGE
As the typical output voltage VP(t) of a piezoelectric transducer (PZ) is an AC signal, a rectifier stage is required. The SECE conversion scheme extracts energy from CP when it reaches a local maximum. Thus, a negative voltage converter (NVC, Fig. 2 (a)), which converts the negative half-waves into positive ones but does not force a current direction, can be used instead of a classical diode full bridge. An advantage of this choice is that the NVC does not have voltage drop due to diode threshold and behaves like a resistor (the MOSFETs in Fig. 2 (a) work in triode region). In order to operate correctly, the NVC needs a minimum input voltage Voff (as in Fig. 2 (b)) equal to the highest threshold voltage between the N and P channel MOSFET. Similarly, the first phase of SECE conversion (Fig. 1 (b), signal A=on, B=off) cannot extract the whole energy on CP as the NVC stops conducting before
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reaching CP=0 C. Moreover, the residual charge QR=VoffCP on CP prevents VP(t) from reaching the maximum possible absolute value after the next peak-to-peak elongation since the current IP is integrated on CP starting from Voff (i.e. QR) and not from –Voff (i.e. –QR) as in Fig. 3 (a) (starting from –Voff is advantageous because the sign of IP in a semi-period is opposite with respect to the previous one, therefore |VP(t)| can reach |VP0+2Voff| instead of |VP0|). An inversion of residual charge (RCI) is proposed, in a way similar to the SSHI principle in [2], by exploiting a resonant circuit (Fig. 3 (b) and (d)) to change the sign of the residual charge QR after an energy extraction cycle has been executed, in order to introduce an advantageous offset in VP(t) for the next elongation as shown in Fig. 3 (a). The parallel resonant circuit (Fig. 3 (d)) is composed of CP and L2 plus the resistance RX of the switch and of L2. Equation (1) shows the expression of the current iL2(t) considering t=0 s at the beginning of the RCI phase and where a=RX/2L2, 02 1
2 a2 . L2 C P , 2 02
i L 2 (t )
QR e a2t sin2 t 2 L2 C P
(1)
The duration tRCI of the RCI phase (signal X=on in Fig. 3 (b)) is half of the oscillation period: at time tRCI=π/ω2 iL2(tRCI)=0 A, QR has been inverted and the switch can be safely opened. Integrating (1) and considering the initial conditions (VP(0)=QR/CP) the PZ voltage after the RCI phase can be expressed as
VP (t RCI )
1 CP
t RCI a Q i (t )dt QR e . R L 2 CP 0
(2)
The increase of performance of the converter then depends on QR (i.e. the threshold voltage of the NVC), the precision of timing and the parameter a. RCI provides a significant increase to the maximum voltage reached by VP(t) and thus to the available energy. Fig. 4 shows the theoretical effect of RCI on the available energy, obtained from analytical calculations on energy relations and numerical simulations to evaluate the effect of realistic component values. RCI increases its relative effectiveness when the maximum of VP is close to Voff (about
Fig. 3. (a) Qualitative waveforms of VP(t) with (red) and without (black) RCI, (b) NVC with RCI circuit, (c) qualitative waveforms of SECE extraction cycle and RCI phase, (d) equivalent circuit during RCI phase.
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Fig. 4. Energy on CP with RCI (red, square) and without RCI (blue, diamond), difference (absolute energy gain) between them (black, cross) and relative increase of energy (green, triangle). Arrows specify the correct axis for each curve. Curves are obtain from analytical calculations and numerical simulations with CP=52 nF, L2=10000 μH and RX=20 Ω, Voff=580 mV.
580 mV in this design), i.e. in case of weak vibrations, the absolute energy gain is directly proportional to the maximum of VP. III.
IC ARCHITECTURE
Fig. 5 depicts the architecture of the system, designed in a 0.32 µm BCD technology from STMicroelectronics. As shown (gray boxes), the converter can be divided in sub-systems with specific tasks. The required external components are the inductors L1 and L2, the capacitors CDD and CST, and the resistor shown. A single inductor could be theoretically used, as it would still be used with a very low duty cycle. In order to speed up the start-up time, an additional capacitor CDD has been added (two-way storage) and is responsible for supplying the power conversion circuits. The use of CDD allows the active operation of the converter even if CST is fully discharged. The converter is fully operative when VDD>1.4 V. Until that moment CDD is passively charged through a conductive path that is cut off by an under-voltage lock-out (UVLO) circuit. A second UVLO (Voltage Monitor block in Fig. 6), with a nominal threshold of 2.5 V and an hysteresis windows of several hundreds of mV, decides if the energy harvested by the SECE circuit has to be directed towards CDD or CST, by controlling two active rectifiers. This policy allows to charge
Fig. 5. block diagram of the designed converter.
PRIME 2013, Villach, Austria
Session W2A – Power Management
CDD with priority when it is getting too discharged to supply the converter. The piezoelectric transducer (PZ) is connected to a NVC which converts the negative half-wave to a positive one, without forcing the current direction. As shown in Fig. 6, an analog peak detector monitors VNVC determines the correct timing for starting each conversion cycle. However, the PZ voltage can exceed the supply voltage of the converter and, for this reason, the peak detector core circuitry is supplied by the higher voltage between VNVC and VDD. This is accomplished with the circuit formed by M14 and M15 in Fig. 6. In case VDD and VVNC are almost equal, conduction occurs through the body diodes of M14,15 and VHH is thus lower of about a pMOS threshold voltage. However, a diode-connected pMOS M13, which has a lower threshold voltage, also feeds the VHH node from VDD, with a limited amount of current (10 times Ibias), in order to reduce the voltage drop on VHH. In order to be compliant with the common mode input voltage range VCMi of comparators and in order to avoid malfunctions on supply switching, the peak detector is fed by a down-shifted version of VNVC (M5…7 in Fig. 6). Circuit simulations show an increase of available input energy of at least 42% (with respect to the same converter without RCI and with VP0=3.7 V) due to RCI, which is performed by connecting the PZ to L2 for half of the oscillation period of the CP-L2 resonant circuit. The duration tRCI of RCI is constant and in first approximation depends on CP and L2. In this implementation an external trimmer is used to set the proper timing (RRCI in Fig. 5). RCI is started together with the second phase of SECE (Fig. 9). The SECE core integrates the switches for connecting L1 to the two active rectifiers, for charging alternatively CDD and CST, and the analog circuitry to detect the end of the first and second phases of SECE (ZCV and ZCC signals, respectively activated at zero voltage/current on the inductor) as shown in Fig. 7. The
Fig. 6. schematic of PZ-specific circuitry: M1-M4 NVC, M5-M7 and Rf, Cf create a scaled and filtered version of VNVC to feed the peak detector, M8-M12 and the comparator form the peak detector, M13-M15 and the current generator realize the circuit to obtain the higher supply (VHH) between VDD and VNVC.
Fig. 7. SECE core schematic. Acronyms ZCV (Zero-crossing voltage) and ZCC (Zero-crossing current) represent the stop signals of Phases I and II of SECE conversion.
controller is implemented with asynchronous logic in order to reduce power consumption due to clock switching and distribution. Moreover, it communicates to the other blocks (RCI, PZ circuitry) the start and stop commands of each phase. The designed active rectifiers are slightly different as shown in in Fig. 7: the one responsible for charging CDD has only a pMOS switch, since the voltage on CDD is always in the VCMi range of a n-type differential couple; the other one has a nMOS/pMOS switch and two comparators with different VCMi and the correct output is chosen by a voltage monitor (VCMi Voltage Monitor block in Fig. 7). In order to minimize circuit absorption the comparators in Fig. 7 are kept shut down except during conversion phases. MN3 has the function of creating a conductive path in parallel to L1 to slowly dissipate the residual energy and so avoid ringing. The same principle is implemented in the RCI circuit for L2. The circuit is fully-autonomous and the quiescent current is 150 nA, leading to 400 nW at 2.7 V on CDD. For the simulations of the IC, performed with Eldo® from Mentor Graphics®, the values in Table I have been used and simulation waveforms are shown in Fig. 8 and Fig. 9. The net efficiency, including circuit consumption, of the SECE converter is at least 81% during active operation of the IC. The
Fig. 8. Simulation waveforms of start-up showing the two-way storage (VDD, the blue curve on top, is quickly charged before VST, black curve). Until about 40 ms the IC operates in passive mode, as can be seen in the VP curve (in red, on bottom); instead in the active operation mode VP is chopped.
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a)
c)
b)
Fig. 9. simulation waveforms showing a SECE conversion and an RCI cycle; a) I phase of SECE conversion, b) II phase of SECE conversion, c) RCI cycle. Fig. 11. layout of the designed IC.
effectiveness of the designed two-way storage is show in Fig. 10: simulations, performed with the same storage capacitor CST=1 mF and same input vibrations, show that the presence of the two-way storage improve performance significantly in the initial start-up with respect to the same converter without the presence of CDD and its associated active rectifier. The small value of CDD, comparable with CP, allows the converter to start almost immediately in the active operation mode, increasing effectiveness of energy extraction (blue waveform in Fig. 10) with respect to the passive operation mode (red waveform in Fig. 10). Supply voltage VDD is kept in the 2.2-3 V range (the UVLO circuit has a smaller hysteresis window but, due to the value of CDD comparable with CP, it is not possible to have a close control on the upper limit of VDD as each SECE conversion contributes with an unpredictable energy packet which can exceed the nominal required energy). Fig. 11 shows the final layout of the designed IC. Chip dimensions, which were not specifically optimized, are 2142 µm for each side and total area is slightly less than 4.6 mm2 and the active area used by the converter is 0.92 mm2.
TABLE I.
COMPONENT VALUE USED IN SIMULATIONS.
Name
Value
Name
Value
L1 L2 RRCI
10 mH 10 mH 13.95 MΩ
CDD CST CP
220 nF 1 mF 52 nF
IV.
CONCLUSIONS
A power management IC for piezoelectric energy harvesting has been designed in a 0.32 µm BCD technology from STMicroelectronics. It integrates an actively controlled AC-DC converter with RCI to enhance energy extraction of over 42% and a smart supply scheme to speed up the start-up phase to increase efficiency in charging a supercapacitor. Due to its quiescent consumption, as low as 150 nA, the IC is fully autonomous and can achieve a positive energy budget even with very low and irregular vibrations.
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[2]
[3]
[4] Fig. 10. Simulation waweforms showing the comparison of the same designed SECE converter with and without the two-way storage. The presence of CDD speeds up the start-up time of the converter (blue waveform) and increase havesting efficiency with respect to the same converter without CDD and its associated active rectifier. For both simulations CST=1 mF and same input vibrations are used.
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