A New Topology of Capacitor-Clamp Cascade Multilevel Converters Anees Abu Sneineh, Ming-yanWang and Kai Tian Harbin Institute of Technology/School of Electrical Engineering and Automation, Habin, China
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Abstract— Use of multilevel converter has become popular in recent years. This paper will present a new topology of capacitor-clamp cascade multilevel converter that is derived from two popular topologies. The new concept of the novel capacitor-clamp cascade converter is based on the connection of multiple three-level capacitor-clamp converter modules. Nine level waveform of the proposed multilevel converter is synthesized by adding of each converter output voltage. Sub-harmonic PWM method is employed in the new topology. The proposed converter is also verified by computer simulation using MATLAB-Simulink. Simulation results are also presented in this paper. Keywords- Cascade; Capacitor-clamp; Multilevel converter; Topology; Sub-Harmonic PWM
I. INTRODUCTION Multilevel power conversion has become increasingly popular in recent years due to its advantages [1-6]. The general concept of the researches in power conversions involves producing ac waveform from small voltage steps by utilizing isolated dc sources or a bank of series capacitors. The small voltage steps yield waveforms with low harmonic distortion as well as low dv/dt. The advantages of multilevel converters if they are compared with conventional two-level converters are the capability of increasing the output voltage magnitude and reducing the output voltage and current harmonic content, the switching frequency and the voltage supported by each power semiconductors. The most famous three types of multilevel converters are diode-clamp, flying-capacitor, and cascade converter with separated DC sources have been developed. In fact, the cascade multilevel converter with separated DC sources has been shown many advantages over the other two. Specially, the modularized circuit layout and packaging are possible. This makes the cascade multilevel converter feasible for manufacturing. Fig.1 shows a schematic of a single-phase cascade converter in which two cell of traditional two-level power converters with separated DC sources are seriesconnected [1, 2]. The output waveform is synthesized by adding of each converter output voltage. Assuming the DC bus voltage of each converter is E. Based on switch combinations, five output voltage levels can be synthesized (0, ±E, ±2E).
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Fig.1. Single phase Cascade multilevel convener
Fig.2. Capacitor-clamp multilevel convener
In traditional cascade converter, the dc bus voltage of each module has the same value, and switching frequency and voltage blocking capability of all switches are the same. Obviously by using proper control method applied to this topology, the stepped output waveform can be approximate to a sinusoidal waveform. Here, many algorithms can be employed, such as optimized stepped IPEMC 2006
waveform method, Sub-harmonic elimination PWM method, etc. [3, 4]. In general, the output voltage of a given multilevel converter can be calculated [5] from: Vo = (S −
n −1 )E 2
(1)
Where Vo is the output of the multilevel converter, n is the number of the output levels; S is the switching state that ranges from 0 to (n-1). E is the minimum voltage level the multilevel converter can produce. For example, when S= 0, 1, 2, 3, 4, then from (1) five output levels can be synthesized respectively. Fig.2 shows a schematic of a single phase Capacitorclamp multilevel converter. Assuming the DC bus voltage of the converter is 2E, it can be easily found that there are five-levels in the output waveform, according to (1), obtains: Vo = (S − 2) E
(2)
Where E is the minimum voltage level, S=0, 1, 2, 3, 4. For S select 0, 1, 2, 3, 4, five different values of the output voltage can be achieved, i.e. (0, ±E, ±2E) accordingly. Approximate sinusoidal output waveform can be achieved by applying proper control methods. II. A NEW CAPACITOR-CLAMP CASCADE MULTILEVE CONVERTER The basic concept of the cascade converter shown in Fig.1 is based on the connection of multiple two-level traditional power converter modules; the output waveform is synthesized by adding of each converter output voltage. The proposed new capacitor-clamp cascade topology is based on the traditional cascade and capacitor-clamp converter that mentioned in part I. The novel concept of the proposed topology is based on the connection of several 3-level capacitor-clamp converter modules, and the multilevel waveform is synthesized by adding of each converter output voltage. Unlike converters for different topologies proposed in ref. [6]. To clearly explain the proposed converter, an example of the novel converter is shown in Fig.3. It consists of two capacitor-clamp multilevel converters that are series connected together. Suppose the DC bus voltage of each capacitor-clamp converter is 2E, five output voltage levels of each cell in the proposed converter can be synthesized, i.e. (0, ±E, ±2E). The synthesized output waveform of the whole converter is nine levels in total (0, ±E, ±2E, ±3E, ±4E). According to (1) we get: Vac = (S −
9 −1 ) E = (S − 4) E 2
(3)
Where S=0, 1, 2, 3, 4, 5, 6, 7, 8, E is minimum voltage level the converter produces. From (3), the output level of the proposed converter can be defined by the switching states S, such as, when S=7, from (3), Vac= +3E.
Fig.3. New capacitor-Clamp Cascade Multilevel convener
Table I shows a group of switch combinations of the proposed converter .Because of more than one group of switch combination can be used to produce some certain voltage levels. For example, there are two switch combinations when yielding +E of cell one. So, Table I only shows a group of switching states. Obviously, more combination choices lead to complexity of control. The advantage of this topology is that it provides flexibility for expansion of the number of levels easily without introducing undue complexity in the power circuit [7]. Moreover, it requires the same number of switches as in diode-clamped cascade topology to achieve a given number of voltage levels [8]. One of the disadvantages in using a diode-clamped inverter is that the required voltage blocking capability of the clamping diodes varies with the levels. This may result in the requirement of multiple series diodes at the higher voltage levels. Another advantage of this topology is that there is no unbalanced capacitor voltage problem because of its independent voltage source structure. However, a problem associated with this approach is the requirement of a complicated control strategy to regulate the floating capacitor voltages [9, 10].
Table I Switching combinations states of the proposed converter S Output 8
+4E
7
+3E
6
+2E
5
+E
4
0
3
-E
2
-2E
1
-3E
0
-4E
Cell One +2E +2E +E +2E +E 0 +2E +E 0 -E +2E +E 0 -E -2E -2E -E 0 +E -2E -E 0 -2E -E -2E
Cell Two +2E +E +2E 0 +E +2E -E 0 +E +2E -2E -E 0 +E +2E +E 0 -E -2E 0 -E -2E -E -2E -2E
T11
T12
T13
T14
T15
T16
T17
T18
T21
T22
T23
T24
T25
T26
T27
T28
1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0
0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1
0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1
0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
1 1 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0
1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0
0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1
0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1
0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1
1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0
1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
III. SUB-HARMONIC PWM Sub-harmonic PWM (SHPWM) is a conventional control method suit for multilevel converter [3, 4]. The control principle of the Sub-harmonic PWM method is to use several triangular carrier signals with only one modulation wave per phase. For an n-level inverter, (n-1) triangular carrier of the same frequency fc, and the same peak-to peak amplitude Ac, are disposed so that the bands they occupy are contiguous. The zero reference is placed in the middle of the carrier set. The modulation wave is a sinusoid waveform of frequency fm and amplitude Am. At every instant each carrier is compared with the modulation waveform.
Each comparison switches the device on if the reference signal is greater than the triangular carrier assigned to that device level; otherwise, the device switches off. For example, a nine-level inverter shown in Fig.3 is considered. Eight triangular carriers are compared with a sinusoid modulation waveform shown in Fig.4, when Vsin>Vtri+4 the switching state S is 8, the output voltage of the proposed converter Vac is +4E, when Vtri+4>Vsin>Vtri+3, the switching state S is 7, Vac is +3E, when VSin
