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A Novel Delay Fault Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware at Strategic Probe Points A. Raychowdhury, S. Ghosh, S. Bhunia, D. Ghosh, and K. Roy Department of ECE, Purdue University, IN {araycho, ghosh3, bhunias, dghosh, kaushik}@ecn.purdue.edu Abstract We propose a delay fault testing methodology using on-chip delay measurement hardware. We have designed a processtolerant, low-overhead delay measurement hardware and developed an algorithm to judiciously insert the hardware at internal nodes of logic blocks. Experimental results for a set of ISCAS89 benchmarks show up to 16.9% improvement in transition fault coverage and up to 10.5% increase in the number of detected faults for segment delay fault model, with fixed test length. The reduction in test length is up to 59% for transition fault, with fixed target coverage. The delay and area overhead due to additional DFT logic is limited to 2% and 4% respectively. Keywords: Transition delay fault, segment delay fault, delay measurement hardware, fault coverage. I. Introduction * Shrinking transistor geometries has resulted not only in an increasing frequency of operation but also in increased process parameter variations. This has posed serious challenges to the traditional testing methodologies [1]. At-speed transition delay fault testing has become a necessity for high performance circuits. Scan architectures provide an efficient way to test for delay faults with reasonably high fault coverage. Both external (ATE-based) as well as Built-in Self-Test (BIST) architectures are popularly used. In both cases, transitions are applied to the primary inputs (PI) and/or to the state inputs (SI) and the responses are observed either at the primary outputs (PO) and/or the state outputs (SO). With increasing circuit complexity, the number of test vectors necessary to obtain reasonably high test coverage is growing rapidly. This has resulted in an exponential increase in the tester complexity/cost and the test application time. In this paper, we propose a novel and comprehensive testing methodology to test for transition [1] and segment delay faults [3]. It involves strategic insertion of observation points within the combinational logic. A hardware architecture, that can detect delay failures at these internal nodes, has also been proposed. The main contributions of the work are: 1. A novel, low overhead Delay Measurement Hardware (DMH) that can detect delay failures at the internal nodes. It is robust with respect to glitch and can easily be calibrated for process variation. 2. A test point insertion algorithm that can identify the strategic nodes where the DMH has to be inserted to increase fault coverage or reduce the test application time. 3. A complete transition and segment delay fault test methodology, with capabilities of fault detection as well as localization, and compatible with ATE based architecture. This can substantially reduce the number of test vectors for *

This research is supported in part by MARCO GSRC and National Science Foundation (NSF).

the same test coverage, thereby reducing the tester cost and testing time. Although, ample research has previously been conducted on test point insertion for stuck-at faults, very little work has been done on delay fault coverage improvement using Test Point Insertion (TPI). Several delay measurement circuits have also recently been proposed, including a Modified Vernier Delay Line [4] and on-chip phase delay measurement hardware [5]. However, implications to transition/segment delay fault coverage have not been studied. Note that in our scheme, we do not target measurement of exact delay at intermediate nodes, but whether there is a delay violation. Thus, our proposed DMH has significantly lower hardware overhead and design complexity than the designs mentioned in [4] and [5]. An ATPG-based TPI technique, to enhance the delay fault coverage by breaking the shift dependency using dummy flip-flop and combinational gate insertion, is proposed in [6]. But it should be noted that such test points act as control points only. Path delay fault testing using TPI is presented in [7], where controllable and observable test points are inserted. Here the sub-paths were tested by trimming the test clock successively and observing the output for failure. However, for practical purposes, it turns out to be expensive in terms of test application time. To the best of our knowledge, there is no previous work attempting to improve the transition/segment fault test coverage and/or test size reduction using on-chip delay measuring hardware. Here, we present a complete methodology that uses processtolerant delay measuring hardware at such points that a significant improvement of coverage and test set reduction is attained. We have applied our approach to a set of ISCAS89 benchmarks for transition delay and segment delay faults and the results show significant improvements in coverage and test length with small delay and area penalty. II. Methodology Before going into the detailed description of the delay measurement hardware, it will be worthwhile to mention the principle of operation of the DMH. Let us assume a combinational logic block with a state input coming from flip-flop FF1 and the output going to FF2. FF1 is triggered at the clock edge T1 and the FF2 is triggered at T2. Let us assume that node X makes a falling transition from a logic one to a logic zero and TD is the time interval between the clock edge T1 and the time when the voltage at node X makes a falling transition. Let us assume that the maximum delay that can be tolerated at node X is TMAX and hence TD > TMAX would mean a delay failure at node X. We propose the system illustrated in Fig. 1a for estimating the delay, TD. A sawtooth generator is so designed that the sawtooth waveform is extracted from the reference clock itself and it has pulse duration equal to the time period (T) of the reference clock. The output of the sawtooth generator goes into a track-and-hold circuit (TAH) and the sampling switch of the TAH is controlled by the observation node (X). As long as the node X is high, the TAH switch is ‘on’ and the output of the TAH tracks the sawtooth

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(a) (b) (a) (b) Figure 2: Schematic diagrams (a) Sawtooth Generator; (b) TrackFigure 1: (a) Block diagram and (b) the timing diagram of the and-Hold (TAH) circuit. DMH. Comparator: The value of the signal at node TAH_OUT goes into waveform. When X makes a falling transition, it turns the TAH the comparator input. The comparator used here is a latch-based switch ‘off’ and the output capacitor of the TAH holds its value sense amplifier, as been illustrated in Fig. 3a. After the track-and(say, VTAH). hold phase, CE goes high and the output of the comparator is noted The greater the delay TD is, the lower is VTAH. The comparator in the next clock cycle. evaluates at the next clock cycle when the Comparator-Enable Generation of reference voltages (CE) signal goes high (Fig. 1b). The reference voltage VREF of the The reference voltage, (VREF) which is an input to the comparator is a measure of the maximum tolerable delay (TMAX) of comparator stage must match with the required delay specification. the node X. The details of its derivation and implementation will Considering a linearly falling sawtooth waveform, the relationship be discussed subsequently. For the observation node X to meet its between reference voltage and allowed delay is given by the predefined delay criteria we require: following expression: (1) VREF ≤ VTAH ⎛ T ⎞ ⎛T ⎞ VREF = VDD ⎜ 1 − MAX ⎟ + VOL ⎜ MAX ⎟ (2) T T When (1) is true, the comparator output goes HIGH (logical ‘1’). ⎝ ⎠ ⎝ ⎠ Although we have discussed the case when X makes a falling where T is the clock period. In the proposed DMH, the stable transition, the same circuit can be used when X makes a rising voltage references (Vref’s) for the DMH have been designed based transition with minor modifications, as discussed in section IV. on the design of band-gap reference voltage. This has been illustrated in Fig. 3b. The principle of operation of sub 1V bandgap III. Design of the individual DMH blocks reference circuit is described in [9]. This has been suitably Sawtooth generator: The sawtooth generator is based on the modified and used in the proposed DMH. The opamp equalizes the principle of constant current discharge. The schematic diagram of voltage between nodes A and B. Hence all the PMOS transistors at the sawtooth generator is shown in Fig. 2a. the top have the same Vgs and hence they mirror the same current. A T flip-flop is used to generate a clock (CLK_2T) with a (3) I1 = I2 = I3 = Iref1 = Iref2 = …. period equal to twice the period of the reference system clock. Let Vd be the voltage across the diode D1. It has a negative Consider that the node OUT in Fig. 2a is precharged to VDD when temperature coefficient (NTC). dV is the voltage difference CLK_2T is low. When CLK_2T goes high (CLK_2TZ goes low) between diode D1 and diode D2 (of area N times that of D1) and the constant supply voltage (VDD) provides a constant current hence dV = VTln(N), where VT is the thermal voltage having a through the NMOS M1. This current discharges the capacitor C positive temperature coefficient (PTC). linearly as long as M1 is in saturation. During this phase the The total current I2 is: PMOS M2 remains ‘off’ and the output node shows a linearly V dV V V falling waveform. At the end of the clock period, the CLK_2TZ I2 = B + d = d + (4) signal goes high. This creates a low resistive path across the R R1 R R1 capacitor through M2 and thus helps to charge OUT back to VDD. Due to the current mirror, the same current is pumped into the The gate voltage Vbias of M1 provides the required current in the reference voltage generator arm. The output reference voltage of saturation region. The discharge is linear (ignoring Early effect the ith arm is thus: [13]) as long as M1 is in the saturation region. Hence we require VDD V DD Vds >= Vbias-Vt. To ensure this, the output node is allowed to discharge till VOL=Vbias-Vt (chosen to be 250mV, in this case) in a single clock period. I1 I2 Iref1 Iref2 OUT Track-and-Hold network: The track-and-hold network for the circuit is a complementary pass transistor switch with a capacitive V ref2 A B V ref1 load (Fig. 2b). The voltage at the observation point X is the input R1 VTAH_OUT signal, S to the TAH. As long as S is high it will charge the − VREF Rref1 R capacitor, CHOLD. The value of the capacitor in our design is 10fF. Rref2 D1 D2 To discharge the capacitor before the next delay measurement, an NMOS switch, triggered by a RESET signal is used in parallel CE with CHOLD. The RESET pulse is generated after the comparison between VREF and VTAH has been made. It is also worth(a) (b) mentioning, that the sampling switch has been made a Figure 3: The schematic diagram of the (a) comparator; (b) complementary one to avoid charge injection and clock feedreference voltage generator. through [8].

⎛ V V ln( N ) ⎞ Vref ( i ) = Rref (i ) ⎜ d + T ⎟ R1 ⎠ ⎝R

(5)

N is chosen such that the net temperature coefficient is zero. Note that, any voltage can be generated by changing the value of Rref. Several different arms have been shown in the circuit below. Further, the output voltage is not dependent on transistor parameters. Even under die-to-die parameter variations, the reference generator will deliver a stable reference voltage. It can be mentioned that bandgap reference usually forms an integral part of all mixed-signal and digital circuits. We can use the bandgap reference already present in the circuit and we can add the reference generator arms to it to obtain a wide range of temperature insensitive and stable voltage references. This will reduce the area overhead involved with the generation of stable reference voltages. If the bandgap reference is not already present, we can use one bandgap reference (as in Fig. 3b) and share it for all reference voltages. Impact of process variation and input glitch It has been mentioned that we generate process variation tolerant reference voltages using a modified bandgap reference. The other important DMH block that can be affected by process variation is the sawtooth generator. Process variation changes the discharge rate of the capacitor C and hence, impacts VOL and the Node X Sawtooth

TAH Output

Figure 4: Spice simulation showing how the proposed DMH can work even when there is a glitch in the net to be probed. choice of VREF. To compensate for this, we propose an initial calibration cycle where the capacitor C is trimmed depending on the process corner, thereby ensuring a linear discharge from Vdd to VOL across all dies. The TAH circuit is a transmission gate with large-sized transistors. Hence, process variation cannot considerably impact functionality or performance of this block. Finally, the comparator is differential in nature and die-to-die Net to be probed

Sawtooth Generator

S TAH and Comparator (Rise transition) S

DMH r

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Figure 5: Schematic for measuring both rise and fall transition delay at a node using DMH.

variation cannot impact its functionality. Further, latch-based comparators, tolerant to within-die variation, have been reported in [10] and extensively studied in the design of our proposed DMH. We have also studied the effect of glitch [13] in the node to be probed. It can be noted that the TAH follows the sawtooth once the glitch dies and holds the value only at the last transition. This can be noted from Fig. 4. Thus, the proposed DMH is robust with respect to glitches. IV. Adaptation of scan architecture It can be easily observed from the discussion presented above that a single DMH can validate only one kind of transition delay fault (e.g., a falling transition as described in Section III). But, a net under consideration can undergo both rising and falling transitions and therefore, it is vital that our design can validate both. This is achieved by a simple circuitry shown in Fig. 5. As evident from the figure, DMHr and DMHf are connected in parallel and receive the original (S) and complemented ( S ) signals from the net under consideration. The decision for a falling transition is made by DMHf and that of a rising transition is made by DMHr. If the transition in S is rising (falling) then the TAH of DMHr (DMHf) follows the sawtooth waveform from TD to T and hence goes to zero. Consequently, the comparator output of DMHf (DMHr) is zero. In case the delay meets the given criteria, the output of the corresponding DMH is ‘1’. Hence, if we XOR the outputs of DMHr and DMHf, then a delay fault (either slow-to-rise or slow-to-fall) is detected if the output of the XOR (DMHout) is ‘0’. Otherwise, the node under test passes the delay criteria. One interesting observation is that we do not need any response analyzer for a pass-fail decision. Instead, the pass-fail decision is automatically available at DMHout. Moreover, insertion of DMH has minimal area and delay overhead (as explained in section VI). ATE-based test architecture ATE-based test architecture with four DMHs is depicted in Fig. 6a. It is obtained by modifying the conventional scan architecture. The scan chain consists of four flip-flops, namely, FF1, FF2, FF3 and FF4. The test application procedure for skewed-load transition delay fault testing [2] using ATE is as follows. The setup vector v1 is shifted into the scan chain (using the scan_in signal) by keeping the test control (TC) and CE signals low and applying the clock. The corresponding PIs are applied by the ATE once v1 has been shifted in. After the application of v1, activation vector v2 is obtained by a one-bit shift and applied to the circuit under consideration. The corresponding PI vectors are simultaneously applied and signal TC is asserted. In the following clock cycle, TC is de-asserted and the PO is observed by the ATE. The CE signal is asserted for one clock cycle (Fig. 6b) so that the DMHs can verify the delays of the nets under consideration and produce an output signal, DMHe. The DMHe signal is generated by AND-ing all the individual DMH outputs. If the DMHe output is low, it means that at least one of the observation nodes has suffered a delay failure. In the following cycle, the DMHe signal is latched in a separate flip-flop (FFdmh), which is introduced to avoid an extra pin for observing the DMH error signal. DMHe is inverted and AND-ed with CE and fed to the select signal of a MUX chain. If both DMHe and CE are high (i.e, the comparison between VREF and VTAH has been performed and there is a delay violation), then the DMH values are latched in part of the scan chain. Otherwise, the scan chain latches the test responses from the combinational logic. Enhanced-scan and broadside test application [2] for scan-based delay testing can be similarly achieved with the proposed architecture using DMH.

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(a) (b) Figure 6: (a) ATE-based test architecture using delay measuring hardware; (b) the timing diagram for test application. Pmi = w1*Ti + w2*NPi, where It is worth noting that in case of a fault, the latching of DMH outputs helps in diagnosing the faulty circuit segment. Now, the Ti = (1 - Oi)* (Pr(i) + Pf(i)), new setup vector is shifted in and scan chain contents are shifted NPi = Normalized number of uncolored path segments in the fanout simultaneously from this cycle as depicted in Fig. 6b. When in cone of ith node. the ATE observes an error signal on FFdmh during scan-out, it Number of uncolored incident paths for node i = knows that the scan-out values at the following cycles are DMH M aximum number of uncolored paths for any edge outputs. This can be subsequently used for diagnosis purposes to where, Ti is the testability of the ith node's output and w1, w2 are localize the failure. By identifying the failing DMHs, we can the weights assigned to two components of the probe metric. Note localize a failure within the intersection of their fan-in logic cones. that by using testability Ti, we target the nodes that have good It can be noted that the DMH delay verification causes an extra controllability but poor observability. An observation point at such clock cycle delay compared to the normal scan test. But since the nodes will always improve the test length if large number of faults length of the scan chain is considerably large, an extra clock cycle is incident on these nodes (which are determined by NPi). delay in one two-pattern test application is expected to be Weights (w1, w2) are initialized to (1, 1) but they can be tuned insignificant. experimentally to maximize the coverage for given test length. In our test architecture, dynamic power consumption can be saved An ideal probe point must have maximum probing metric value. by turning off the DMHs (disabling the CLK to Sawtooth To ensure that probing points are inserted only in paths that meet generator and the CE signal) during the normal operation of the the slack constraint, we maintain the worst-case slack values at all circuit. nodes. Depending on the timing slack available in a node chosen V. Observation point insertion for DMH insertion, we have the following two options: For probe point insertion, we choose a node that is: (a) easily • If the chosen node belongs to a timing critical path, and does not controllable but have poor observability; (b) lying at the meet the slack constraint, then the insertion is aborted and the intersection of many incoming path segments. Our probe metric node is marked. accounts for both of these factors during probe point selection. • If the slack constraint is met, then the node is selected for insertion. At the same time, slacks of all timing paths passing Probe point insertion algorithm for transition delay faults through the selected node are updated. This can be done by The probe point insertion algorithm for transition delay faults simply subtracting the DMH delay overhead from the slacks of begins by creating a graph G of the input netlist. In this graph, the those paths. Note that we do not need to run complete timing nodes represent the gates and edges between two nodes represent analysis after each probe point insertion. Once the path slacks the net between the corresponding nodes. Now, the nodes are are updated, slacks of all nodes lying on these paths are also sorted topologically. Next, by traversing the graph in topological modified accordingly. order, the controllability and observability values of the input and In a similar manner, the next probe point is selected and this output nodes are computed in a manner described in [11]. From the process is repeated. The algorithm is computationally efficient 0 and 1 controllability values, we have defined the probability of a with overall complexity of O(n2) since it is dominated by the rising and a falling transition for each edge of graph G. As an topological sorting. The pseudo-code of the probe point insertion example, for a 2-input NAND gate, it is defined as: algorithm is given in Table 1. Pr (out) = Pf (in1) ∗ C1(in2) ∗ C1(in2) + Probe point insertion for segment delay faults Pf (in2) ∗ C1(in1) ∗ C1(in1) (7) The segment delay fault model has emerged as a popular delay Pf (out) = Pr (in1) ∗ C1(in2) + Pr (in2) ∗ C1(in1) fault model to test for possible delay violations in path segments Where, C1 is the 1 controllability, O is the output observability and [3, 12]. The segment length is an input parameter to the model. It Pr (Pf) is the rise (fall) transition probability. Similarly we can varies from 1 (corresponding to the transition delay fault model) to define the rise/fall transition probability of all other logic gates. the longest segment length (corresponding to the critical path At the inception of the algorithm, we start with all path segments length). The probe point insertion algorithm for the segment delay defined to be uncolored. If a probe point is inserted at a node fault is identical to the probe point insertion algorithm for the output, we color all path segments in its fan-in cone. Now for each transition delay fault. The probing metric, however, is different in node, we compute the number of uncolored path segments in its this case. The probing metric for segment delay fault for segment fan-in cone. Now the next step is to determine the best node where length L, is given by: the probe hardware can be inserted. Pm i = w1*Ti + w2*NSi, where To accomplish that, we define probing metric for the ith node as:

Ti = (1 - Oi)* (Pr(i) + Pf(i)), NSi = Normalized number of uncolored segments of length L in the fan-in cone of ith node. Number of uncolored incident segments of length L for node i

=

Maximum number of uncolored incident segments of length L at any node where, as before, Ti is the testability of the ith node's output edge and w1, w2 are the respective weights assigned to each component of the probe metric. VI. Results To check the functionality of the proposed DMH (containing DMHr and DMHf as shown in Fig. 5, we inserted it in an internal node (X) of an ISCAS89 benchmark circuit (s298). A test vector is applied in such way that node X undergoes a rising transition. Since node X meets the delay criteria, DMHout is ‘1’ (when CE = ‘1’). Now, the delay of node X is increased beyond the threshold value by inserting a resistive bridge. Since node X violates the delay requirement, DMHout becomes ‘0’. The simulation result from the spice is depicted in Fig. 7. Similar experiment is also repeated for a falling transition at node X and it was observed that the DMH circuitry gives expected output. The delay overhead due to a DMH insertion is less than 1% of critical path delay for s1196 (the maximum among all the ISCAS89 benchmarks considered here) and less than 0.4% on an average. We have also computed the area overhead with probe point insertions in terms of active area (W*L) of logic gates. The area overhead was computed for the number of probe points beyond which there was no considerable improvement in fault coverage. The result of one such experiment is shown in Fig. 8. The benchmark s5378 is simulated with 150 test patterns for

Table 1: Pseudo-code for the probe point insertion algorithm Algorithm InsertProbe() Input: Netlist in spice. Number of probing points (Y). Slack constraint. Target test coverage. Output: A set of probing points. Begin 1. Read the netlist and create a graph (G); 2. Order the nodes of G topologically; 3. Traverse G topologically and compute C(0,1) and O for each node; 4. Using static timing analysis, find worst case timing slack for each gate; do 5. Start traversing G from primary inputs 6. For each node (N) do 7. Find testability N(T); 8. Find number of uncolored path s segments (Un) to node N; 9. Find probing metric Pm = f(T, Un); end for 10. Get the node X with max(Pm); 11. If X meets the slack constraint then 11.1 mark all path segments in the fanin cone of X as colored; 11.2 update slack values of all paths containing node X; 11.3 re-compute the observabilities of the fan-in cone; else 12. mark node X as colored and continue; while (Y probing points are inserted or the target coverage is achieved); end

different number of probe points. The result indicates that a maximum of 10 probe points are necessary to achieve significant improvement in test coverage. The same study for all the benchmark circuits indicates an identical behavior and we conclude that 8-20 probe points are sufficient to achieve significant improvement in test coverage. For larger benchmarks like s35932 (s15850), the area overhead is just 0.7% (2.2%) with 20 probe points. However, for small benchmarks like s838, the area overhead was higher, leading to an average area increase of 3.9%. Next, the entire test methodology is verified by finding the set of probe points (where the DMH's will be inserted) for ISCAS89 benchmark circuits using our algorithm and treating them as pseudo primary outputs. The test circuits are mapped to the LEDA standard-cell library and simulations are performed with TSMC 180nm technology. The test coverage and the test patterns for the transition delay fault are obtained using Synopsys Tetramax ATPG tool [14]. The area overhead is limited by setting the maximum number of test points to 20 and the tolerance in critical-path delay overhead is set to 2%. Note that propagation delays to internal nodes may change during placement and routing requiring change in reference voltage of a DMH. Insertion of DMH after the physical design phase may violate design constraints on the original design. We suggest performing placement and routing with the DMHs as black boxes (at the probe points as determined by circuit topology using the proposed algorithm). Once the placement and routing phase is over and exact path delays to internal nodes are known, reference voltages for all DMHs can be set appropriately. Transition faults: Table 2 shows the fault coverage and number of test patterns required for the original (without test point insertion) and modified circuits (after TPI) for a target fault coverage of 85% and 90%. It can be observed that for all benchmark circuits, there is a significant reduction in the number of test patterns. An average reduction of 48.25% and 45.31% in number of test patterns is observed for the target coverage of 85% and 90% respectively. Table 3 shows the fault coverage of the original and the modified circuits for a set of 100 and 150 test patterns. Again, it can be observed that an average of 11.37% and 7.49% improvement in coverage is attained for 100 and 150 test patterns respectively. Note that, we achieve much higher coverage improvement if we

Figure 7: Spice simulations of the proposed DMH. Note that the Vref = 0.8V. Both faulty and fault-free operations are illustrated.

Table 2: Number of test patterns for a target coverage of 85% and 90%

s838 s1196 s1423 s5378 s9234 s13207 s15850

Number of Test Patterns (90%) Original After TPI 151 106 188 93 92 53 214 110 317 170 319 161 320 160

simulate for smaller number of test patterns. For example, circuit s1196 shows an improvement of 20% when simulated for 50 patterns (with and without TPI). The impact of the number of probe points on the transition fault coverage is shown in Fig. 8. The benchmark s5378 is simulated with 150 test patterns for different number of probe points. The result indicates that a maximum of 10 probe points are necessary to achieve significant improvement in test coverage. The same study for all the benchmark circuits indicates an identical behavior and we conclude that 8-20 probe points are sufficient to Table 3: Fault coverage (in %) with a fixed # of test patterns Circuit

s838 s1196 s1423 s5378 s9234 s13207 s15850

Fault coverage with 100 test patterns After Original TPI 81.17 88.81

91.27

96.29

78.35 92.58 80.84 73.09 76.75 78.31

86.89 97.69 87.35 79.21 81.49 83.73

95.77 99.24 92.01 89.08 88.43 91.17

91.58 96.76 89.73 85.41 84.96 86.37

Fault coverage with 150 test patterns Original

After TPI

achieve significant improvement in test coverage. Segment delay faults: We have also verified the proposed delay testing methodology using observable point insertion for the segment delay fault model. The segment length L has been chosen to be 2, 3 and 5 and a set of random input vectors are applied. It has been observed that the fault coverage of segment delay faults is lower than the transition delay faults due to its robust fault propagation requirement [12]. Hence, the metric of interest in this study is the percentage increase in the number of detected faults when the same set of input vectors are applied to the circuit both before and after test points are inserted. Table 4 depicts the percentage improvement in the number of detected faults for different ISCAS89 benchmark circuits when a set of 1000 random vectors are applied. It can be noted that there is a 6.3% average increase (for L=5) in the number of detected faults when observable test points are inserted. Table 4: Percentage increase in number of detected faults for different segment lengths (L) L 2 3 5

s838 5.00 3.93 7.14

s1196 6.76 8.02 9.56

s1423 1.62 2.65 2.83

s9234 9.68 10.5 7.55

s13207 2.15 3.06 4.41

VII. Conclusions This paper presents a novel delay fault testing methodology using on-die delay measurement. The design of a low-overhead, process-tolerant delay testing hardware used in this purpose has

Percentage fault coverage

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Figure 8: Variation of test coverage with number of probe points. been presented. An algorithm has been proposed to judiciously select probe points in the combinational circuit where the delay measurement hardware should be inserted. Simulation results show considerable improvement in fault coverage and reduction in test patterns for both transition as well as segment delay faults. References: 1. A Krstic et al., “Delay fault testing for VLSI circuits,” Kluwer, 1998. 2. M. L. Bushnell et al., “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer, 2000. 3. K. Heragu et al., “Segment delay faults: A new delay fault model,” VTS, pp. 32-39, 1999. 4. R. Datta et al., “On-chip delay measurement for silicon debug,” GLSVLSI, pp. 145-148, 2004. 5. Chauchin Su et al., “All digital built-in delay and crosstalk measurement for on-chip buses,” DATE, pp. 527-531, 2000. 6. S. Wang et al., “Hybrid Delay Scan: A Low Hardware Overhead Scanbased Delay Test Technique for High Fault Coverage and Compact Test Sets,” DATE, pp. 1296-1301, 2004. 7. S. Tragoudas et al., “Testing for path delay faults using test points,” DFT, pp. 86-94, 1999. 8. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw Hill, USA, 2000. 9. Banba et al., “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE JSSC, pp.670-674, 1999. 10. Sarpeshkar et al., “Mismatch sensitivity of a simultaneously latched CMOS sense amplifier”, IEEE JSSC, pp. 1413-1422, 1991. 11. C. Brglez, “On testability of combinational networks”, ISCAS, pp. 221-225, 1984. 12. K. Heragu et al., “SIGMA: A simulator for segment delay faults”, ICCAD, pp. 502-507, 1996. 13. J. M. Rabaey, “Digital Integrated Circuits”, Prentice Hall, 1996. 14. Synopsys Inc., “Tetramax ATPG”, www.synopsys.com/products.