A Novel Dual-Output Six-Switch Three-Phase Inverter M. Heydari1, Student Member, IEEE, A. Yazdian Varjani2, Member, IEEE, M. Mohamadian3, Member, IEEE, and A. Fatemi4, Student Member, IEEE
Power Electronic and Protection Laboratory (PEP Lab.), Faculty of Electrical and Computer Engineering Tarbiat Modares University, Tehran, Iran. Emails:
[email protected],
[email protected],
[email protected],
[email protected] Abstract- A novel dual-output six-switch inverter topology is proposed in this paper for independently supplying two threephase loads. This inverter employs less number of semiconductor devices compared to former dual-output inverters proposed so far in the literature. Reducing the number of switches and hence drive and control circuits results in reduction in total cost and loss and increases the system efficiency and reliability. The new configuration is introduced and carrier-based PWM schemes for its two defined modes of operation (constant frequency and variable frequency modes) are developed for it. Furthermore, analysis of semiconductor loss is performed and the results are compared with counterpart topologies. Simulation and experimental results will be presented to demonstrate the theoretical knowledge.
I. INTRODUCTION Implementing low cost power inverters is a recent trend towards cost reduction in power electronics based systems especially induction motor drive systems. In many sensitive applications such as robotic systems, in addition to cost reduction, reducing the system size and weight as well as providing a high degree of reliability is of utmost importance. These objectives could be achieved by reducing the number of active switches in power inverters. The resultant configurations are called reduced switch count inverters. Various topologies have been proposed so far for switch reduction in the literature [1-5]. Reduced switch-count inverters fall into two broad categories of single-output and multi-output inverters. A typical reduced switch count single-output inverter reported in [2] which is called B4 inverter is suggested as a practical alternative for B6 inverter which consists of six switches and free-wheeled diodes. Five-leg inverter [6] and nine-switch inverter [7] are among the multi-output topologies which are employed to independently supply and control two three-phase loads. In five-leg inverter, two phases of each load are separately connected to four legs of the inverter while one leg is shared between the third phase of the loads [6, 8]. Nine-switch inverter which is shown in Fig. 1 has three legs each composed of three switches. The middle switches QAM, QBM and QCM are the joints between the two outputs. By applying the appropriate control algorithm, nine-switch inverter makes supplying two-three phase loads possible using less number of switches compared to five-leg inverter. Nine-switch topology is used as an AC/AC converter in [9, 10]. In [11], its space vector modulation is elaborated. Also in [12], current-type nine-switch inverter is proposed for high power applications. Reference [13] has proposed a hybrid electric vehicle (HEV) based on a bidirectional z-source nineswitch inverter.
978-1-61284-972-0/11/$26.00 ©2011 IEEE
Fig. 1. Nine-switch inverter
In this paper, a novel dual-output inverter topology which consists of six active semiconductor devices is proposed for independently supplying two three-phase loads using less number of switches. The paper consists of seven sections. The topology of the proposed inverter and its carrier-based PWM modulation scheme are described in the following section. Two designated modes of operation are defined for it and the work specifications of each mode are classified in section three. Replacing dc link sources of the proposed inverter with capacitors is described in section four. The simulation results for loss analysis are inspected in section five. The validity of performance of the proposed inverter is verified by simulation and experimental results in the sixth section. Finally, section seven is dedicated to conclusion. II. THE PROPOSED DUAL-OUTPUT SIX-SWITCH INVERTER This section first describes the switch arrangement in the new configuration. The developed carrier-based PWM scheme for the proposed topology is presented afterwards. A.
The proposed configuration Fig. 2 illustrates the topology of the proposed dual-output sixswitch three-phase inverter. The inverter has two legs with three power switches in each one. In addition, three sources are placed in series at the dc link. Two phases of each three-phase ac load are connected to the two inverter legs and the other phase is connected to one of the joints of the dc link sources. The middle switches in the inverter legs are shared between the two ac loads and hence the number of switches is reduced by 33% and 40% respectively compared to nine-switch and five-leg inverters. Two modes of operation are defined for the proposed inverter: 1Variable frequency (VF) mode in which both frequency and amplitude of the output voltages are adjustable and 2- Constant frequency mode (CF) in which working frequency of both connected loads is similar and constant while the output voltage amplitude may vary. In Fig. 2, voltage levels of dc link sources are a function of three a, b and c coefficients. These coefficients are to be 1109
determined in a manner to achieve balanced three-phase outputs voltages without dc component. The values of a, b and c will be obtained for different inverter modes of operation and in each mode two different strategies are considered for determining these coefficients. The first strategy allows using dc sources of unequal voltage levels in the dc link. These levels are constant and do not vary with modulation index. The second strategy provides the best possible dc bus voltage utilization by changing dc link coefficients according to modulation indices. B.
Developed carrier-based PWM scheme Fig. 3(a) illustrates the carrier-based PWM modulation scheme of the proposed inverter and the resultant switching vectors. In each phase there are two reference signals for the two upper and lower outputs. The lower modulating signal (VrefL) should not be higher than the upper one (VrefU) at any moment. For this reason, the offset value for each reference waveform should be calculated to prevent interference between modulating signals. Gate signals of QAH and QBH switches are resulted from comparing the upper modulating signal with the carrier signal. Gate signals of QAL and QBL switches are the logical NOT of the values obtained by comparing the lower modulating signal with the carrier signal. Gate signals of QAM and QBM are generated by logical XOR of the upper and lower gate signals in each leg. Applying this scheme, there are always two ON switches in each leg. The upper output phase voltage waveforms are depicted in Fig. 3(b). For each output, there are three vectors in each switching cycle: {(10), (00) and (11)}. Similarity of the triangles in Fig. 3(b) yields the following equations: T 2 1 = (1) x 1 − VrefUB T 2 1 = y 1 − VrefUA
Fig. 3.(a) Carrier-based PWM modulation scheme and the resultant switching vectors of the proposed dual-output inverter; (b)Upper output phase voltages
Considering Fig. 3(b) and the defined modulating signals, the fundamental components of the three-phase voltages are derived in (7-9) for the upper output and in (10-12) for the lower output by replacing x and y with their equivalents from (1) and (2). a b c a b c v AS = Vdc [( + + ) mU sin ωt − ( + + ) mU sin(ωt + ϕ1 ) 3 3 3 6 6 6 (7) a b c a b c + − − + ( + + )offsetU ] 6 6 6 6 6 6 a b c a b c vBS = Vdc [ −( + + )mU sin ωt + ( + + ) mU sin(ωt + ϕ1 ) 6 6 6 3 3 3 (8) a b c a b c + − − + ( + + )offsetU ] 6 6 6 6 6 6 a b c a b c vCS = Vdc [−( + + ) mU sin ωt − ( + + )mU sin(ωt + ϕ1 ) 6 6 6 6 6 6 (9) a b c a b c − + + − ( + + )offsetU ] 3 3 3 3 3 3 a b c a b c v A′S ′ = Vdc [( + + )mL sin ωt − ( + + ) mL sin(ωt + ϕ2 ) 3 3 3 6 6 6 (10) a b c a b c + + − + ( + + )offsetL ] 6 6 6 6 6 6 a b c a b c vB ′S ′ = Vdc [−( + + ) mL sin ωt + ( + + )mL sin(ωt + ϕ2 ) 6 6 6 3 3 3 (11) a b c a b c + + − + ( + + )offsetL ] 6 6 6 6 6 6 a b c a b c vC ′S ′ = Vdc [ −( + + )mL sin ωt − ( + + ) mL sin(ωt + ϕ2 ) 6 6 6 6 6 6 (12) a b c a b c − − + − ( + + )offset L ] 3 3 3 3 3 3
(2)
Let the modulation signals of the upper and lower output phases be the shifted sinusoidal waves of (3) to (6). VrefUA = mU sin ωt + offsetU (3) VrefUB = mU sin ( ωt + ϕ1 ) + offsetU
VrefLA = mL sin ωt + offset L VrefLB = mL sin (ωt + ϕ2 ) + offsetL
(4) (5) (6)
where mx and φx are respectively the reference amplitude and the phase difference between the phases and U and L indices refer to upper and lower outputs.
Fig. 2. Proposed dual-output six-switch inverter
Considering (7) to (12) and the fact that a+b+c=1, it can be deduced that first for obtaining balanced output voltages the condition of (13) should be met and second that phase voltages of both inverter outputs contain dc component. (13) ϕ1 = ϕ2 = π 3 The values of a, b and c in VF and CF modes are distinctively determined to eliminate dc component from inverter output voltages via using two different strategies for each operation
1110
mode. Assuming the dc component being eliminated using one of the strategies, output voltages would be: (14) (15) (16) (17) (18)
2) Second strategy This strategy is in fact a method for enhancing dc bus utilization by increasing the maximum limit of modulation index. For this purpose, offsetU and offsetL are determined according to upper and lower modulation indices by α which is called dc bus utilization factor and is defined in (29). This factor specifies the upper output utilization of dc link voltage.
(19)
III. OPERATION MODES Two modes of operation are defined for the proposed inverter. Each mode employs two different strategies for eliminating dc component from output voltage; the first strategy results in constant dc link voltages and the second makes them vary according to upper and lower output modulation indices. These modes and their particular strategies are described in the following and pros and cons of each one are discussed. A. VF mode of operation Inverter outputs can have different frequencies and amplitude in this mode independent from each other. To eliminate dc component and to obtain balanced outputs, two strategies are suggested: 1) First strategy To prevent upper and lower modulating waves interference and also to avoid over-modulation, upper and lower offsets should always fulfill the following criteria: (20) 0 ≤ offsetU ≤ 1 (21) −1 ≤ offset L ≤ 0 (22) offset L = −offsetU In general, for preventing the interference of modulation waveforms, the modulation indices should satisfy (23) to (25). mU + mL ≤ offsetU + offset L (23) mU ≤ 1 − offsetU
(24)
mL ≤ 1 − offset L
(25)
α=
0.5
0.4
0.2 a, c b 0
0
0.1
0.2 0.3 Upper Offset
0.4
0.5
Fig. 4. DC link voltage coefficient versus upper offset, first strategy
(27)
L
0.7 0.6
U
(28)
Fig. 4 illustrates the dc link voltage coefficient values versus offset variation in the first strategy. This figure clearly shows one of the unique features of the proposed dual-output topology which is the ability of producing balanced three-phase voltages using dc sources of unequal voltage levels by choosing the appropriate offset values. Another point to be mentioned from the figure is that if the upper offset is 1/3, dc link voltage coefficient will be equal and each dc source will be Vdc/3. Fig. 5 displays the maximum modulation indices for upper (mU) and lower (mL) outputs for different offset values. It should
0.3
0.1
Maximum of modulation indexes(m and m )
c = (1 − offsetU ) 2
(29)
B. CF mode of operation In CF mode, the voltage amplitudes of the two outputs can change independently though they must have similar frequency and phase difference. Again, to eliminate dc component from output voltages, two strategies are employed. Operation details of these strategies in CF mode are tabulated in Table III. Maximum modulation indices and phase voltage amplitudes are compared using both strategies in CF mode and the results are listed in Table IV. No constraint is imposed on simultaneous modulation indices of the two outputs in this mode.
Furthermore, considering (7) to (12) and (22), to eliminate output dc component without using extra capacitors, dc link voltage coefficients are determined by (26) to (28). a = (1 − offsetU ) 2 (26) b = offsetU
mU mU + mL
Limits of offsetU, offsetL, mU and mL and also dc link voltage coefficients are tabulated in Table I for both strategies. As it is apparent in Table I, the drawback of the second strategy is that two of three dc source voltage levels are dependent on modulation indices. A comparison is made in Table II regarding maximum modulation indices and phase voltage amplitudes as well as maximum simultaneous modulation indices and simultaneous phase voltage amplitudes using both strategies in VF mode.
coefficients of DC link
3 mU Vdc sin(ωt − 30D ) 6 3 vBS = mU Vdc sin(ωt + 90D ) 6 3 vCS = mU Vdc sin(ωt + 210D ) 6 3 v A′S ′ = mLVdc sin(ωt − 30D ) 6 3 vB ′S ′ = mLVdc sin(ωt + 90D ) 6 3 vC ′S ′ = mLVdc sin(ωt + 210D ) 6 v AS =
be noticed that the sum of upper and lower modulation indices should fulfill (23). As it can be seen in the figure, the maximum modulation index happens in offsetU=1/3 and is equal to 2/3. However, according to (23), if one modulation index would be 2/3, the other one should be zero. Hence, 2/3 cannot be used for both modulation indices simultaneously.
0.5 0.4 0.3 0.2 0.1 0
0
0.2
0.4 0.6 upper offset
0.8
1
Fig. 5. Maximum modulation indices of upper and lower outputs versus different offset values, first strategy, VF mode
1111
Dc link voltage coefficients
Second strategy
a = (1 − offsetU ) 2
1 mL a = (1 − ) 2 mL + mU
b = offsetU
b=
1 2
c = (1 − offsetU ) 2
1 mU c = (1 − ) 2 mL + mU
0 ≤ offsetU ≤ 1 −1 ≤ offset L ≤ 0 offset L = − offsetU
offsetU + offsetL ≤ 1 offsetU = 1 − α offset L = −α
mU + mL ≤ offsetU + offset L
mU + mL ≤ 1
Upper and lower offset limits Modulation indices limits
First strategy
mU ≤ 1 − offsetU mL ≤ 1 − offsetL
mU ≤ 1
mL ≤ 1
TABLE II MAXIMUM MODULATION INDICES AND PHASE VOLTAGES USING BOTH STRATEGIES, VF MODE
Maximum modulation indices
Maximum phase voltage amplitude
First strategy
Second Strategy
mU = 2 3 if mL = 0
mU = 1 if mL = 0
mL = 2 3 if mU = 0
mL = 1 if mU = 0
mU = 0.5
mU = 0.5
mL = 0.5
mL = 0.5
Not simultaneous
0.385Vdc 2
0.577 Vdc 2
Simultaneous
0.2887 Vdc 2
0.2887 Vdc 2
Not simultaneous Simultaneous
TABLE III OPERATION DETAILS USING TWO STRATEGIES OF DC COMPONENT ELIMINATION, CF MODE First strategy Dc link voltage coefficients
a = (1 − offsetU ) 2
a = mU 2
b = offsetU
b = 1 − mU 2 − mL 2
c = (1 − offsetU ) 2
c = mL 2
0 ≤ offsetU ≤ 1 −1 ≤ offset L ≤ 0 offset L = − offsetU
offsetU = 1 − mU offset L = m L − 1
mU − mL ≤ offsetU + offset L
mU ≤ 1
Upper and lower offset limits Modulation indices limits
Second strategy
mU ≤ 1 − offsetU mL ≤ 1 − offsetL
mL ≤ 1
TABLE IV MAXIMUM MODULATION INDICES AND PHASE VOLTAGES USING BOTH STRATEGIES, CF MODE First Strategy Maximum modulation indices Maximum phase voltage amplitude
mU = 1 , mL = 1 0.577 Vdc 2
in CF mode is its capability to produce balanced three-phase voltages using sources of different voltage levels. IV. REPLACING DC SOURCES WITH CAPACITORS In practice, instead of using several dc sources, one dc source in parallel with series combination of capacitors should be used at the dc link of the proposed configuration. Doing so, the values of the dc link capacitors could be selected regardless of the chosen strategy of determining offsets working either in CF or DF mode and irrespective of the final offset values. This is because the dc link capacitors will be automatically charged at the required level so as the ac outputs are without dc component. In other words, the dc link capacitor voltages will be set according to the a, b and c coefficients calculated in Table I and Table III, in the absence of any specific control strategy. V. LOSS ANALYSIS OF THE PROPOSED TOPOLOGY Switching loss and conduction loss of the novel dual-output configuration are investigated and the results are compared with nine-switch inverter and B4 inverter in this section. Switch parameters are the same as those analyzed in [13]. The analysis is carried out for two modes of operation, VF and CF modes. For both modes, the load is a series three-phase RL load of 25Ω and 25mH and the switching frequency is 10 kHz. A.
Semiconductor loss in CF mode Table V shows the simulation parameters in this mode. The dc bus voltage level is chosen for the three inverter types so that the amplitude of the output current is the same. Since B4 is capable of supplying one load, the obtained results for it are multiplied by two. Fig. 7(a) displays the conduction loss of the three inverters. As it is can be seen in the figure, due to employing less number of active switches and diodes, the proposed inverter has less conduction loss in higher modulation indices compared to two other topologies. Inverters’ switching loss versus modulation indices are shown in Fig. 7(b). Higher switching loss of the proposed inverter and B4 inverter is because of their higher dc bus voltages compared to nine-switch inverter. Fig. 7(c) illustrates the efficiency of the three inverters. As it can be seen in the figure, the proposed inverter efficiency is comparable to other two inverters. B.
Semiconductor loss in VF mode VF mode is not defined for B4 inverter; hence the inverter loss is not discussed for it in this section. Since in VF mode the maximum modulation index is limited to 0.5, dc bus voltage is Maximum of modulation indexes(mU and mL)
TABLE I OPERATION DETAILS USING TWO STRATEGIES OF DC COMPONENT ELIMINATION, VF MODE
Second Strategy
mU = 1
,
mL = 1
0.577 Vdc 2
Using the first strategy in CF mode, variation of a, b and c coefficients versus offset value are depicted in Fig. 4. Fig. 6 illustrates the maximum modulation index of upper and lower outputs for different offset values. It should be noticed that when the first strategy is applied, the modulation indices should satisfy |mU-mL| ≤ |offsetU| +|offsetL|. For example, if offsetU=0 , then both modulation indices should simultaneously be one. The advantage of using the first strategy
1
0.8
0.6
0.4
0.2
0
0
0.2
0.4 0.6 Upper offset
0.8
1
Fig. 6. Maximum modulation indices of upper and lower outputs versus different offset values, first strategy, CF mode
1112
(a)
(c)
(b)
(e) (f) (d) Fig. 7. CF mode, (a) Inverters’ conduction loss, (b) Inverters' switching loss, (c) Inverters’ efficiency; VF mode, (d) Inverters’ conduction loss, (e) Inverters' switching loss, (f) Inverters’ efficiency TABLE V SIMULATION PARAMETERS FOR LOSS CALCULATION, CF MODE Parameter Value fU 50 Hz fL 50 Hz Vdc (6sw) 1000 V Vdc (9sw) 577 V Vdc (B4) 1000 V TABLE VI SIMULATION PARAMETERS FOR LOSS CALCULATION, VF MODE Parameter Value fU 50 Hz fL 80Hz Vdc (6sw) 2000 V Vdc (9sw) 1154 V
doubled to provide output power equal to CF mode in both nineswitch and six-switch configurations. Simulation parameters are tabulated in Table VI for this mode. As it could previously be inferred from CF mode, when the modulation index is low, both conduction and switching loss of the proposed topology are higher compared to nine-switch inverter. This can be seen in Fig. 7(d) and Fig. 7(e), respectively. Fig. 7(f) displays the inverters’ efficiency for this mode which are still very close together. VI. SIMULATION AND EXPERIMENTAL RESULTS Having the loss analysis of the proposed inverter topology concluded, the validity of its performance is also verified by both simulation and experimental results. The operation of proposed topology is investigated for its two formerly defined modes of operation. It should be mentioned that two three-phase RL loads are directly connected to the inverter outputs without any conditioning or output filter. A.
CF mode of operation Simulation and experimental parameters of this mode are listed in Table VII. Fig. 8 shows the line voltages and currents of the lower output in CF mode. Since in this operation mode the frequencies are equal, the upper output has the similar shape and is not depicted.
TABLE VII SIMULATION AND EXPERIMENTAL PARAMETERS,VF AND CF MODES Parameter
CF Mode
VF Mode
Switching Frequency fU fL Rload-H Lload-H Rload-L Lload-L mU mL Vdc
6 kH 60 Hz 60 Hz 5 Ohm 6 mH 7 Ohm 5 mH 1 0.75 104 V
6 kH 50 Hz 60 Hz 5 Ohm 6 mH 7 Ohm 5 mH 0.5 0.375 208 V
Similar to B4 configuration, the line voltages of the proposed inverter outputs are different for the three phases. Presuming that the dc sources are placed in the leg C, VAB has a unipolar waveform of three levels (Vdc, 0 and -Vdc ) while VBC and VCA are bipolar waveforms with two levels of ±Vdc/2. From the Total Harmonic Distortion (THD) point of view, the line voltage THD is similar to B4 inverter. It is also apparent in Fig. 8 that i'C is more distorted than the other two phase currents. It is because that i'C is produced by vC'S' which has higher THD than vA'S’ and vB'S'. B.
VF mode of operation Simulation and experimental parameters of this mode are listed in Table VII. The upper and lower load currents are shown in Fig. 9. It can be seen that the outputs have different frequencies and amplitudes independent from each other in this mode so that the proposed inverter is able to independently supply and control two three- phase loads. Similar to CF mode, the current distortion of the third phase is higher than the other two phases due to its different phase voltage waveform. VII. CONCLUSIONS A novel reduced switch count multi-output inverter named “dual-output six-switch three-phase inverter” was proposed in this paper. The proposed inverter topology was introduced; its modulation scheme was developed; two modes of operation were defined for it and loss analysis was carried out along with the comparison of the results with counterpart topologies. The
1113
V
AB
200
0
-200
50 V/div- 5ms/div 0.62
0.63
0.64
0.65
0.66
V
BC
200 0
50 V/div- 5ms/div
-200
0.62
0.63
0.64
0.65
0.66
V
CA
200 0
Lower currents (A)
-200
50 V/div- 5ms/div 0.61
0.62
i'B
i'A
5
0.63
0.64
0.65
i'C
i'A
i'C
i'B
0
2 V/div- 5ms/div
-5 0.61
0.62
0.63 Time (s)
0.64
0.65
(a) (b) Fig. 8. CF operation mode waveforms of lower output of proposed inverter. (a) Simulation waveforms. (b) Experimental waveforms 10
iA
iB
i'A
i'B
iA
iC
iB
iC
5 0 -5
2 V/div- 5ms/div
-10
5
i'C
i'A
i'B
i'C
0 -5
2 V/div- 5ms/div 0.1 0.11 0.12 (b) (a) Fig. 9. VF operation mode waveforms of lower and upper output currents of proposed inverter. (a) Simulation waveforms. (b) Experimental waveforms 0.08
0.09
advantages of the proposed six-switch topology over nine-switch inverter are: - The number of switches and hence drive circuits is reduced by 33%. Despite higher voltage stress, manufacture cost is still lower especially in low voltage designs. - Higher reliability - Higher efficiency in higher modulation indices - Less conduction loss - Less size and weight Two strategies were employed for obtaining balanced output voltages without dc component. In the first strategy, the dc source voltage levels are constant and it is possible to use voltage sources of unequal levels in the dc link. In the second strategy, dc bus voltage levels vary according to output modulation indices but the dc bus utilization is enhanced. The effective operation of the proposed converter and its ability to independently supply two three-phase loads in both CF and VF modes was demonstrated by simulation and confirmed through experimental implementation.
[4]
[5]
[6] [7] [8]
[9] [10]
REFERENCES [1] [2]
[3]
J. F. Eastham, A. R. Daniels, and R. T. Lipcynski , “A novel power inverter configuration,” IEEE Industry Applications Society, pp. 748– 751,1980. H. W. Van Der Broeck, and J. D. Van Wyk, “A comparative investigation of a three-phase induction machine drive with a component minimized voltage- fed inverter under different control options,” IEEE Trans. on Industry applications, Vol. IA-20, No. 2, pp. 309–320, 1984. H. W. Van Der Broeck, H. C. Skudelny, “Analytical analysis of the harmonic effects of a PWM ac drive,” IEEE Trans. on Power
[11] [12] [13]
1114
Powered by TCPDF (www.tcpdf.org)
Electronics, Vol. 3, No. 2, pp. 216–223, 1988. P. N. Enjeti, and A. Rahman, “A new single phase to three phase converter with active input current saring for low cost ac motor drives,” IEEE Trans. on Industry Applications,Vol. 29, pp. 806–813, 1993. P. N. Enjeti, A. Rahman, and R. Jakkli, “Economic single-phase to three phase converter topologies for fixed and variable frequency output,” IEEE Trans. on Power Electronics, Vol. 8, No. 3, pp. 329– 335, 1993. B. Francois. and A.Bouscayrol, “Control of Two Induction Motors Fed by a Five-Phase Voltage-Source Inverter”, ELECTRIMACS’ 99, Lisboan, Portugal, Vol. 3, pp.313-318, 1999. T. Kominami, and Y. Fujimoto, “A Novel Nine-Switch Inverter for Independent Control of Two Three-phase Loads”, IEEE Industry Applications Society Annual Conference (IAS), pp. 2346-2350, 2007. M.Hizume, S.Yokomizo, and K.Matsuse., “Independent Vector Control of Parallel-Connected Two Induction Motors by a Five- Leg Inverter”, Papers of Joint Technical Meeting on Semiconductor Power Converter, IEE Japan, Vol.SPC-03, pp.5-10, 2003. C. Liu, B. Wu, N. Zargari, D. Xu, and J. Wang, ‘‘A novel three-phase three leg AC/AC converter using nine IGBTs,’’ IEEE Trans. on Power Electronics, Vol. 24, No. 5, pp. 1151---1160, 2009. L. Congwei, W. Bin, N. Zargari, and D. Xu, ‘‘A novel nine-switch PWM rectifier-inverter topology for three-phase UPS applications,’’ EPE Journal, Vol. 19, No. 2, pp. 1---9, 2009. S. M. Dehghan, M. Mohamadian, A. Yazdian, and F. Ashrafzadeh, “Space Vector Modulation for Nine-Switch Converters,” IEEE Trans. on Power Electronics, Vol. 25, pp. 1488–1496, 2010. S. M. Dehghan, M. Mohamadian, and A. Yazdian, “Current-Type Nine-Switch Inverters,” Journal of Power Electronics, Vol. 10, No. 2, pp. 146-154, March 2010. S. M. Dehghan, M. Mohamadian, A. Yazdian, “Hybrid Electric Vehicle Based on Bidirectional Z-Source Nine-Switch Inverter”, EEE Trans Vehicular Technology, vol. 59, no. 6, pp. 2641-2653, 2010.
