A Novel Yield Optimization Technique for Digital CMOS ... - IEEE Xplore

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 5, MAY 2005

A Novel Yield Optimization Technique for Digital CMOS Circuits Design by Means of Process Parameters Run-Time Estimation and Body Bias Active Control Mauro Olivieri, Member, IEEE, Giuseppe Scotti, and Alessandro Trifiletti

Abstract—This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13- m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die. Index Terms—Active body bias, digital CMOS circuits design, process parameters estimation, yield.

I. INTRODUCTION

T

RADITIONALLY, the goal of digital circuit designers has been to obtain the best tradeoff between speed (in terms of achievable clock frequency) and power consumption. Recently, the requirement of low power dissipation has become an overriding constraint for microprocessors design in mobile environments. Moreover, as technologies continue to scale following the international technology roadmap for semiconductors (ITRS), power density has become an even more significant concern due to its impact on packaging costs. At circuit level, the most important components of power dissipation are dynamic power—due to CMOS switching activity—and leakage power—due to parasitic currents in switched-off CMOS devices—and it is expected that leakage power will become comparable to dynamic power consumption in the very next future [1]. Process parameter variations at the different production levels (i.e., die, wafer, lot, and run) can have a strong impact on circuit performance—in terms of speed, dynamic power and leakage power—possibly compromising the production of most innovative digital integrated circuits (ICs) design due to a too low yield. To achieve an acceptable yield, the designer often refers to process corner values for assessing expected performance figures. Since actual performance figures of merit can thus vary by Manuscript received October 18, 2003; revised September 13, 2004. The authors are with the Electronic Engineering Department, University of Rome “La Sapienza,” 00184 Rome, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2005.844290

more than 100% in the extreme cases, it can be necessary to design the circuit with much better performance figures than required in the nominal case, to guarantee that all fabricated circuits meet the expected requirements. A better trade-off between performance and yield can be obtained if a design approach based on statistical tools—such as Monte Carlo analysis—is used, instead of a corner analysis based one. The yield optimization problem has been addressed and analytically formulated from a statistical point of view in [2], and various approaches, such as design centering [2] or design of experiment (DOE) [3], have been proposed to find computer-aided design (CAD)-oriented solutions. The essential process parameters affecting a CMOS circuit performance are the threshold , the transconductance parameter , and the transivoltage tion frequency . Both performance and yield of a digital IC would dramatically benefit from having the circuit optimized for the actual CMOS process parameters. Previous research works have targeted the control of body bias voltage to maximize specific system level macro parameters, such as the sustainable clock frequency, or minimize the leakage power. In [4], the effectiveness of using reverse body bias to reduce leakage power during active operation, burn-in and stand-by has been discussed. In [5], the authors analyze the effects of using adaptative body bias to reduce the impact variations on within-die of die-to-die threshold voltage variations. In [6], forward body bias is used for a communication router design in 150-nm CMOS to obtain 1-GHz operation at 1.1-V supply. In [7], the authors propose the simultaneous use of adaptative body bias and dynamic voltage scaling to reduce power consumption in high performance processors. Analytical models of the leakage current, dynamic power and frequency as functions of body bias are also derived. In [8], adaptative body bias is used to compensate for die-to-die parameter variations by applying the body bias that maximizes the die frequency subject to a power constraint. and body bias are jointly used Finally, in [9], adaptative to reduce the impact of parameter variations on frequency, dynamic power, and leakage power of microprocessors. In many cases, it is assumed that within-die parameter variations are much lower than die-to-die parameter variations [10], and the effects of within-die fluctuations are neglected by following a worst-case approach [10], [11]. However, as pointed out in [12], the effects of within-die fluctuations increase as the channel

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OLIVIERI et al.: A NOVEL YIELD OPTIMIZATION TECHNIQUE FOR DIGITAL CMOS CIRCUITS

length is shortened, so that circuit design methodologies aimed at suppressing the effects of both die-to-die and within-die parameter variations are required for the future technology generations. In this work, we propose a novel architecture scheme based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The proposed design flow allows to statistically predict the expected yield with and without the introduction of the body bias control circuitry, therefore, a priori quantifying the yield improvement allowed by the introduction of the novel control architecture in a specific design. In previous approaches, based on run time performance measurement [8], [9], the on chip circuitry generates the body bias that minimizes leakage power for a given target clock frequency; the process is done at high temperature (110 ) since this is a worst-case condition for both clock frequency and leakage power. In our approach, given a set of constraints for clock frequency, dynamic power and leakage power, the goal is to optimize circuit parametric yield. Our a priori method provides a prediction of the optimized yield at different temperatures in the design phase, so that not only the optimal design of the controller but also the optimal nominal sizing of circuit elements can be achieved. In the following, Section II introduces the novel control architecture, while Section III outlines the analytical methodology to obtain the body bias controlling function to be implemented in the controller. The design of the process parameter variations estimation circuits is discussed in Section IV and new estimator topologies are proposed. Section V reports the application of the proposed approach to a circuit block extracted from a microprocessor critical path, meant to model the effect of our control scheme and design flow on a real microprocessor design: a strong yield improvement with respect to the design without control circuits is shown. A comparison with the results obtained by previous approaches is also discussed in Section V. II. PROPOSED APPROACH In our approach, the effects of die-to-die parameter variations are corrected by estimating the actual values of die-to-die process parameter variations (by means of estimation circuits placed very close to the critical part of the circuit) and using active control of body bias and/or of supply voltage in order to control circuit figures of merit as will be detailed in the following. The proposed control architecture is depicted in Fig. 1. A set of sensing circuits allows us to estimate the actual values of critical process parameters from the die-to-die distribution; the estimated variables are sent to the analog-to-digital converter (ADC) and then to the digital controller. For a given ciris stored into the controller procuit, a matrix grammable read only memory (PROM), containing the values of the optimal body bias and/or of supply voltage that maximize performance for a given set of estimated values for large-scale . The parameter esti(i.e., die-to-die) parameter variations mation and bias correction is performed during circuit operation. The methodology to find the values of the optimal body bias and/or of supply voltage requires a statistical model able to simulate die-to-die process parameter dispersion. The effects of

Fig. 1.

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Block scheme of the proposed control architecture.

within-die parameter variations on circuit performance have to be taken into account by means of a statistical model of devicesmismatch: this issue will be discussed in Section V-B. It has to be pointed out that the practical implementation of statistical models of MOS devices able to account both for die-to-die and within-die process parameter variations has been demonstrated [13]–[15]. A very good fitting with measured data is reported in [13] not only for mean values and standard deviations but also for correlation between data of NMOS and PMOS; in [15], the reported curves of measured and predicted show a practically perfect fitting. Such statistical models are nowadays available in the design kits provided by many silicon foundries. III. DESIGN METHODOLOGY OF THE CONTROLLER From a statistical point of view, a general definition of the parametric yield is the probability that a fabricated circuit shows , comprised in an a performance vector -dimensional acceptability region , where are specific figures of merit. Since in digital VLSI design figures of merit typically include clock frequency and power defined as consumption, we address a performance vector (namely clock frequency, dynamic consumption and leakage consumption). Here we show a general solution to the yield optimization problem with the view of possible extensions of the interesting figures of merit included in . In a full custom design approach, is a function of circuit parameters , where is a vector of design-independent parameters (e.g., threshold voltage, minimal gate delay or operating temperature) which account for process spread, and is a vector of design parameters whose nominal value can be chosen in the design phase (e.g., transistor sizes or supply voltage). Due to the random variation of design-independent for any chosen by factors , there is a variability region of the design parameters the designer. The nominal values have to be set so that is contained in an acceptability region . Assuming no control is imposed on the design-independent factors , yield is maximized by solving the following optimization problem (standard design centering): (1) where is the joint probability density function of . the performance vector

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Fig. 3. Splitting the variability range of the estimated design independent or V ). factors (such as V

yield optimization problem reported in (3) (single-loop yield optimization)

(3) Fig. 2. Flow diagram of the proposed design methodology.

Referring to our approach, the flow diagram for the optimal design of the digital controller is shown in Fig. 2. The design procedure is outlined as follows. 1) The set of figures of merit G to be optimized is defined. In full custom VLSI design, typical figures of merit to be optimized are clock frequency and power consumption. in G, a set of yield goals is For all the figures of merit provided as: (2)

2) 3)

4)

5)

These inequalities defines the acceptability region for circuit performance. Single sided constraints (e.g., , or ) represent a special case of such general form. A partition of vector into design-independent factors vector ( ) and design factors vector ( ) is identified. A subset of design-independent factors to be estimated is selected. We denote the subset of the estimated design-independent factors as the vector and the subset of nonestimated design-independent factors as the vector . The selection of the subset of design-independent factors to be estimated can be made on the basis of a preliminary of the difanalysis of both the standard deviation ferent factors in , and the sensitivity of circuit performances with respect to design-independent factors variations. The estimation circuits for the selected variables have to be provided in this step. to be used as controlling variables The set of voltages is chosen, as well as the range of variability of the controlling voltages. The yield optimization problem is defined and solved. The variability range of each of the estimated variables is partitioned into intervals as shown in Fig. 3 for the simple case of two estimated design-independent factors. In each -dimensional obtained regions we can solve the of the

or the one reported in (4) (double-loop yield optimization)

(4) In both of the optimization problems, the estimated factors are not considered as random variables and the estimated value is used in the yield computation. During the single-loop optimization problem, the vector of nominal values of the design voltages are opparameters is kept unchanged and only timized, while, in the double-loop optimization problem, the opis found for different values of the timal value of voltages vector whose value is chosen only at the end of the optimization. Double loop allows us to avoid suboptimal solutions at the expense of higher computational load (in the design phase). Each of the discussed optimization problems can be solved within a CAD environment providing the optimal values of the controlling variables to be inserted into the digital controller memory. Yield problem formulations in (3) and (4) highlight the advantages of the proposed design methodology. First, the is reduced (no dispersion is considered variability region for estimated random variables); furthermore, new degrees of freedom (the controlling body biases) are introduced in the optimization problem thus allowing a better coverage of variability region and acceptability region. IV. ESTIMATION CIRCUITS A. Estimation Circuits for Process Parameter Variations Here we describe some circuits for the estimation of process parameter variations, specifically die-to-die variations of the of n-channel devices and of the threshold threshold voltage of p-channel devices. The circuits which allow voltage and are reported in Figs. 4 and 5, the estimation of respectively. Circuit in Fig. 4 is made up of a minimum area


Fig. 4. Circuit diagram of the estimator for the threshold voltage NMOS devices.

V

of

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Fig. 6. Output of the estimation circuit in Fig. 4 as a function of the threshold voltage V .

the variations of voltages Denoting with our relations we can write

involved in

(7) from which we obtain

(8)

Fig. 5. Circuit diagram of the estimator for the threshold voltage PMOS devices.

V

of

(9) PMOS device which acts as a current source and of a diode-connected NMOS; circuit in Fig. 5 is made up of a minimum area NMOS device which acts as a current source and of a diode denotes a bandgap reference voltage. connected PMOS; By using the -power law MOSFET model [16] and equating the DC current of the PMOS and NMOS transitors we obtain in the following expressions for the voltage at the node in Fig. 5, respectively, (the same Fig. 4 and at the node has been assumed for n-channel and p-channel devices [16])

Observing that and are of the same order of magcan be designed to be much lower than nitude and that , from (8) and under the hypothesis we obtain: (10) from (9), under the hypothesis we obtain glecting

and ne-

(11) (5)

(6) where and respectively, and

are the gate width of NMOS and PMOS, are fitting parameters.

Hypotheses

for the circuit in Fig. 4 and for the circuit in Fig. 5 can be easily fulfilled by a proper sizing of MOS devices. The estimation circuits discussed in this section require a stable bandgap reference voltage: we have used the CMOS compatible bandgap reference topology reported in [17]. as a function of threshold voltage , Fig. 6 reports as a function of . Figs. 6 and 7 whereas Fig. 7 reports have been obtained by spice simulations of the proposed circuits

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Fig. 9. Fig. 7. Output of the estimation circuit in Fig. 5 as a function of the threshold voltage V .

Output of the PTAT temperature sensor as a function of temperature.

Equation (12) shows that the sensitivity of the circuit depends ratio and is, therefore, insensitive to die-to-die on the process resistance value variations. The simulated sensor response in the 10 C–120 C temperature range is depicted in Fig. 9. V. DESIGN CASE STUDY A. Die-to-Die Parameter Variation Compensation

Fig. 8. Circuit diagram of the PTAT temperature sensor.

in which the parameter “Vth0” of the BSIM3v3 model has been swept. Spice simulation results with a 0.13- m CMOS technology reported in Figs. 6 and 7 are in good agreement with theoretical behavior, showing that the proposed estimation circuits are effective in deep submicron technologies. B. Temperature Sensor The temperature sensor is based on a proportional to absolute temperature (PTAT) current reference generator; the adopted -based current source topology is reported in Fig. 8. The performs the temperature sensing and the output resistor converts the current into a voltage which can be sent to the ADC. for the circuit in Fig. 8 can be The voltage at the node expressed as

(12)

To verify the effectiveness of the proposed approach, we have applied it to a circuit block extracted from a microprocessor critical path, meant to model the effect of the proposed control scheme and design flow on the yield of a real microprocessor design. Our circuit-under-test (CUT) consists of 15 CMOS gates; similar test circuits have been used in [8]. The figures of merit considered in the experiment were the oscillation and the dynamic power consumption frequency of the CUT configured as a ring oscillator, and the leakage of the CUT in static conditions. power consumption The circuit was implemented in a 0.13- m CMOS process with a 1.3-V maximum supply voltage. A 0.8-V supply voltage was assumed with the view of a low power consumption design; equivalent supply voltage sizing have been used in [4], [8], and [18]. We used the control architecture described in Section II and the design flow outlined in Section III has been followed. Process parameter variations of MOS devices and operating temperature variations were the design-independent factors addressed by this case study. In order to perform yield estimation and optimization, we used the statistical model of MOS devices provided by the foundry’s design kit. This model is able to take into account both die-to-die and within-die process parameter variations at the different operating temperatures and is declared by the foundry as silicon verified. Since the threshold voltage is a critical parameter because of its impact on both frequency and power we chose as estimated and design-independent factors the threshold voltages of n-channel and p-channel MOSFETs, respectively. As an additional estimated design-independent factor we chose the operating temperature because of its strong impact on leakage power. The estimation circuits used for this case study were the ones and temperature. discussed in Section IV for and As controlling variables we chose the body bias of n-channel and p-channel devices, respectively. Reverse body bias is applied to reduce power consumption (and the


TABLE I YIELD SPECIFICATIONS

oscillation frequency), while forward body bias is applied to increase oscillation frequency (and the power consumption); therefore, in this case study the digital controller takes as inputs , and of the sensing circuits the outputs for , and temperature and provides the optimal body and for n-channel and p-channel devices. bias The maximum allowed reverse body bias voltage in the target technology is limited by breakdown considerations and is set to be 0.5 V. Maximum allowed forward body bias voltage is limited by the forward biasing of the drain-bulk junction and is set to 0.25 V in our design. The yield specifications assumed for the yield optimization are reported in Table I. The operating frequency target has been set according to system specifications, while the power constraints have been derived by assuming the power density limit of 10 W/cm and a standby leakage power of 0.5 W/cm which are typical values for low power microprocessors in mobile systems [9]. The circuit was designed in the Cadence IC 4.4.6 environment: transistor level simulations backannotated with parasitic capacitances extracted from the layout were used to compute variability range of and the desired figures of merit. The has been divided into five bins according to the process corners of the technology; the variability range for operating junction temperature has been assumed to be 0 C–120 C and the yield optimization has been performed at 0 , 60 , and 120 C. The optimal couple of values for body biases and for each of the 75 obtained regions has been found by solving the optimization problem reported in (3). Circuit yield was estimated and optimized by means of Monte Carlo simulations taking into account, as a first step, only die-to-die parameter variations. It has to be pointed out that by following our approach the estimators outputs are used as inputs for the controller ROM and the optimization is carried out by using the estimated values of parameter variations; in this way any estimation error is taken into account in the design phase. , In Table II, the partial yield for for clock frequency , leakage power and dynamic power are reported for the circuits dethe cumulative yield signed without (NBB) and with (ABB) the proposed approach 0 C, 60 C, 120 C, respectively. These yield at numbers have been computed by means of 500 Monte Carlo iterations: a yield estimation with less than 3% error with a 95% confidence level for a 80% yield is, therefore, guaranteed. and of the controller as Fig. 10 reports the outputs a function of the threshold voltage estimation circuits outputs and (normalized to their nominal value) at 120 C. Fig. 11 reports the outputs and of the controller as a function of the temperature estimation circuit (normalized to its value at 60 C) in typical output process conditions.

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TABLE II PARTIAL YIELD FOR CLOCK FREQUENCY (Y F ), DYNAMIC POWER (Y P ), LEAKAGE POWER (Y P ) AND THE CUMULATIVE YIELD (Y TOT) WITHOUT CONTROLLER (NBB) AND WITH CONTROLLER (ABB) AT 0 C, 60 C, 120 C AND CONSIDERING ONLY DIE-TO-DIE PARAMETER VARIATIONS

Fig. 10. Outputs V circuits outputs V 120 C.

and V and V

Fig. 11. Outputs V and temperature sensor output V process conditions.

of the controller as a function of the estimation (normalized to the nominal value) at T =

V

of the controller as a function of the (normalized to the value at 60 C) in typical

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TABLE III PARTIAL YIELD FOR CLOCK FREQUENCY (Y FCK ), DYNAMIC POWER (Y PDY N ), LEAKAGE POWER (Y PLEAK ) AND THE CUMULATIVE YIELD (Y TOT) WITHOUT CONTROLLER (NBB) AND WITH CONTROLLER (ABB) AT 0 C, 60 C, 120 C AND CONSIDERING DIE-TO-DIE AND WITHIN-DIE PARAMETER VARIATIONS

Fig. 12. Scatter plot of P versus F at T = 120 C with and without the use of the controller and considering only die-to-die parameter variations.

Fig. 13. Scatter plot of P versus F at T = 120 C with and without the use of the controller and considering only die-to-die parameter variations.

Fig. 12 reports the scatter plot of leakage power as a function of operating frequency for the circuit with no body bias control (without controller) and for the circuit designed with the proposed approach (with controller). Fig. 13 reports the scatter plot of dynamic power as a function of operating frequency for the circuit with no body bias control (without controller) and for the circuit designed with the proposed approach (with controller) Both figures are referred to a 120 C operating temperature. The use of a sensor to estimate temperature introduces an imprecision due to spatial gradients. In order to study this limitation we performed an analysis of the effects of temperature estimation error on the yield simulating the circuit at a temperature different from the one in which optimization was carried out: a less than 2% yield lowering for a 10% temperature estimation error around 60 C has been found, which demonstrates the practical validity of the technique. B. Effects of Within-Die Parameter Variations The relative impact of die-to-die and within-die parameter variations depends on the number of critical paths per die and on the number of gate stages in the critical path [8]. If a controller and a set of estimation circuits are used for each critical path, the effects of within-die parameter variations are minimized and

Fig. 14. Scatter plot of P versus F at T = 120 C with and without the use of the controller and considering both die-to-die and within die parameter variations.

the results reported in Section V-A are a good approximation of the effective yield enhancement. If only one controller and only one set of estimation circuits per die are used, the effects of within-die parameter variations have to be taken into account. In order to provide validation of the control architecture in which only one set of estimation circuits and one controller are used, we present the results of the yield analysis taking into account both die-to-die and within-die parameter variations. In Table III, the partial yield for for clock frequency , dynamic power , leakage power , and the cumulative yield are reported for the circuits designed without and with the proposed 0 C, 60 C, 120 C, respectively, approach at by taking into account die-to-die and within-die parameter variations. Fig. 14 reports the scatter plot of leakage power as a function of operating frequency for the circuit with no body bias control (without controller) and for the circuit designed with the proposed approach (with controller). Fig. 15 reports the scatter plot of dynamic power as a function of operating frequency for the circuit with no body bias control (without controller) and for the circuit designed with the proposed approach (with controller). Figs. 14 and 15 are referred to a 120 C operating temperature and to the case in which both die-to-die and within-die parameter variations are considered.


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and . The optimized yield with no constraints on has resulted to be 100%. In this case, forward body bias is applied both to NMOS and PMOS devices and this results in high leakage at 120 C. A constraint on leakage power has been W) and the optimized cumulative yield added ( and constraints) has resulted to be (i.e., referring to 90%. Fig. 16 reports scatter plots of leakage power as a function of operating frequency for the circuit with no body bias control (without controller) and for the circuit designed with the proposed approach (with controller). It is interesting to note that in this latter case our optimization strategy results in forward body bias for PMOS devices and reverse body bias for NMOS devices.

=

Fig. 15. Scatter plot of P versus F at T 120 C with and without the use of the controller and considering both die-to-die and within die parameter variations.

=

Fig. 16. Scatter plot of P versus F at T 120 C with and without the use of the controller and considering both die-to-die and within die parameter variationsfor the circuit considered in the second case study.

Though a direct comparison with previous approaches is not viable because of the different technology and different goal in yield optimization, the following considerations can be done: in [8], experimental results on 62 dies show a 50% initial yield constraint only) improved to (computed referring to the 100% with the application of simple ABB, reducing frequency , but still with a significant number of dies which variation fail to meet the leakage constraint.1Those results were obtained at 110 temperature which is a worst-case condition for both clock frequency and leakage power, and is the only one considered in [8]. In our first case study, the cumulative yield (com, and constraints) has been puted referring to improved from 13% to 86% at 120 C, from 48% to 97% at 60 C and from 36% to 95% at 0 C. In order to make a more direct comparison with S-ABB in [8] an additional case study has been performed by setting the so to have an initial yield (i.e., comsupply voltage constraint only) of 50% at puted referring to the 120 C, and then applying our approach to maximize 1According

to the scatter plot reported in [8, Fig, 6].

VI. CONCLUSION A bias control architecture and a design flow have been proposed which allow to enhance the yield of CMOS digital integrated circuits. The method is based on the use of specific circuits to sense die-to-die process parameter and operating temperature variations, and of a digital controller which is able to set the body bias of MOS devices as a function of sensing circuits outputs. The body bias is, therefore, a function of the actual values of process parameters and operating temperature, allowing to optimize the tradeoff between speed and power consumption imposed by yield specifications. For its inehrent characteristics the approach is more flexible than previously proposed techniques for body bias control and/or yield optimization. The proposed method, applied to a circuit block meant to model the effect of our control scheme and design flow on a real microprocessor design has shown a strong yield improvement with respect to the noncontrolled design.

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Mauro Olivieri (M’05) received the M.S. degree in electronic engineering (cum laude) and the Ph.D. degree in electronic and computer engineering from the University of Genoa, Genoa, Italy, in 1991 and 1994, respectively, where he also worked as an Assistant Professor. In 1998, he joined the University of Rome “La Sapienza,” Rome, Italy, where he is currently Associate Professor of Electronics. His research interests are digital system-on-chips and microprocessor core design. He supervises several research projects supported by private and public funding in the field of VLSI system design.

Giuseppe Scotti was born in Cagliari, Italy, in 1975. He received the M.S. and Ph.D. degrees in electronic engineering from the University of Rome “La Sapienza,” Rome, Italy, in 1999 and 2003, respectively. He is currently doing postdoctoral work with the Electronic Engineering Department, University of Rome “La Sapienza.” His research interests include the design methodologies of high-yield analog and digital integrated circuits, the design techniques of high-speed circuits for optical communication systems, and the design of integrated active filters. Since 1998, he has been involved in the design of integrated circuits both for low-frequency and high-frequency applications at the Electronic Engineering Department, University of Rome “La Sapienza.”

Alessandro Trifiletti was born in Rome, Italy, in 1959. In 1991, he joined the Electronic Engineering Department, University of Rome “La Sapienza,” Rome, Italy, as a Research Assistant and is currently an Assistant Professor. His research interests include high-speed circuit design techniques and III–V device modeling.