2010 Second International Conference on Computational Intelligence, Communication Systems and Networks
A Particle Swarm Optimization Approach for Routing in VLSI M. Nasir Ayob, Zulkifli Md Yusof, Asrul Adam, Amar Faiz Zainal Abidin, Ismail Ibrahim, Zuwairie Ibrahim, Shahdan Sudin, N. Shaikh-Husin and M. Khalil Hani Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor, Malaysia
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[email protected] wire are not allowed will be referred later in this paper as wire obstacle and the region in which buffer is not allowed as buffer obstacle. This condition will limit the possibilities to add buffer for further minimized the interconnect delay. However, an effective approach for reducing the interconnect delay is to simultaneously do the routing and buffer insertion at proper location. With this method, the shortest path now, no longer can be assumed to have minimum delay instead non-minimal distance of the path with appropriate buffer insertion may provide the optimal solution (minimum interconnect delay). In order to simultaneously search the routing path and at the same time find the proper buffer location on wire routing will be significantly complex compare to traditional approach (shortest path problem). This method has been introduced by Zhou et. al [2] using dynamic programming and later the algorithm is improved by Look-Ahead Concept [3]. PSO approach in VLSI routing was first implemented by Chen Dong [4]. The algorithm was targeting to have shortest path in MRST problem. The problem does not include any buffer and obstacle in VLSI grid graph. Thus this paper is introducing PSO to solve the VLSI routing with buffer insertion simultaneously.
Abstract The performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path. Hence, this paper proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). PSO is a robust stochastic optimization technique based on the movement and information sharing of swarms. In this study, location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The proposed approach has a good potential in VLSI routing and can be further extended in future. Keywords Routing, buffer insertion, interconnect, particle swarm optimization
I.
INTRODUCTION
Interconnect in the size of deep submicron and nanometre design has become dominating factor in circuit performance and reliability. Thus the performance of the VLSI circuit is very much depends on wire routing and buffer insertion along the path. Without using any optimization technique or algorithm, the mathematical equation become complexes and many number of parameter will be used to solve this routing problem. To solve the complexity problem, Particle Swarm Optimization (PSO) is an optimization technique which is an evolutionary computational technique developed by Australian Scientist, James Kennedy and Russell Eberhart in 1995 [1]. PSO is a robust optimization technique based on movement and intelligent of swarm. The main objective of this problem is to obtain the optimal path which is having the minimum value of interconnect delay from source to sink in VLSI using Grid Graph model. Traditionally, the routing path is obtained and then the buffer is inserted to minimize the delay. This technique will have the path with the shortest distance from source to sink whereas the shortest path is considered to have minimum delay. In practical, there are region in the VLSI area where the wire are permitted to route through but the buffer placement is not allowed. The region in which
978-0-7695-4158-7/10 $26.00 © 2010 IEEE DOI 10.1109/CICSyN.2010.42
II.
PARTICLE SWARM OPTIMIZATION
Basically, a swarm is represented by population and a particle is represented by an individual. Each particle is treated as a point in multi-dimensional space and changes its location according to its own experience and other particles experience. Each one of these particles will produce two parameters which are velocity of particle and the position of the particle. Both parameters are communicating each other. The next iteration position of the particle, ( ) is mathematically defined as (1) From Eq. (1), the next position of particle ( ) is depends to its current position ( ) and the velocity for the next placement ( ). This velocity is calculated as -
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(2)
using distributed RC network as interconnect model and applying the Elmore Delay formulation to calculate the interconnect delay from source to sink. Elmore delay has simpler analytical closed form, which is based on the first order impulse response of resistivecapacitive delay. In PSO parameter, Elmore delay is used to calculate the fitness function of the particle which is the interconnect delay. In Elmore delay formulation, each of wire segments is represented by a π-model RC circuit. As shown in Figure 1, one wire segment in VLSI may be represent as π-model where r and c represent resistance and capacitance of the wire respectively .The interconnect delay of the wire segment may be further improved when adding buffer at the proper location along the wire. After add the buffer, a segment with a buffer will be represent as Figure 2, where , and are intrinsic buffer delay, buffer output resistance and buffer input capacitance respectively. A complete pulse will also have source resistance, connected serially to the first wire segment resistor and load capacitance, connected parallel to the last wire segment capacitor. In distributed RC network the delay can be calculated iteratively through programming. The dynamic programming algorithm to determine Elmore delay either by starting the iteration from the source node and progressing towards the sink or by starting the iteration from the sink and ending at the source [1]. In this paper we determine the delay using the first method which is calculating from source to sink.
where is particle i velocity at k iteration and is particle i position at k iteration. and are (cognitive and social component) are learning factors usually = 1.4. and are random number [0,1]. The personal best ( ) is the best solution found by the particle i meanwhile the global best ( ) is best solution among the . Noted that all the particle will try to be the best by converging around and . Eventually all the particle will converge at the same best solution which is after certain generation. The inertia weight, used in this application is the type of decrease inertia weight as shown in Eq. (3). (3)
wmax and wmin represent maximum and minimum value of inertia weight respectively, while k represents the where
current generation at the time the inertia weight,
is
k max is the maximum generation set for this application. Value for inertia weight used are wmax =0.9 and calculated.
wmin =0.4. In this application, the swarm search space is similar to the VLSI area and the particle is similar to the path routing from source to the sink. The fitness function in this problem is the interconnect delay from source to sink. The optimal path is the path with the minimum interconnects delay.
B. Elmore Delay Calculation from Source to Sink For computation delay where the iterative calculation starts from source then advance to the sink, each node in the wire is labeled with a resistance-delay pair (r, t) where r is resistance of wire and t is delay time accumulated up to that node, respectively [2]. When the pair (r, t) is known, the subsequence delay pair (r’, t’) may be calculated using Elmore delay formula. If the subsequent segment is wire then, (r’, t’) is defined as: (4)
Global Best PSO Algorithm 1: initialize all particle by randomizing position 2: for each particle do 3: calculate fitness for particle 4: if fitness better than previous pbest then 5: set fitness value as new pbest 6: end if 7: end for 8: Choose particle with the best pbest as gbest 9: for each particle do 10: calculate particle velocity according to (2) 11: update the particle position according to (1) 12: end for 13: repeat 14: goto procedure 2 15: until maximum iteration or stop by user
(5) where and are the resistance and capacitance of the wire segment. If the segment consists of wire with buffer then the formula for next the subsequent of pair (r’, t’) is
A. Delay Model As the fabrication technology go into deep submicron in sizing, the size of wire become smaller and thus significantly increase the resistance of the wire. Resistance of the wire no longer be ignore because it effects the interconnect delay. Lumped delay model is therefore obsolete and cannot be used anymore [3]. For VLSI routing tools interconnect normally modeled as a distributed RC network [5-6]. Thus, in this paper we are
(6) (7)
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Figure 1: Wire model
Figure 2: Wire with buffer model Figure 4. PSO VLSI routing mapping
where is the vertex value of at the column and row . The value of z is set to 1 in wire which the wire routing cannot go through, such at wire obstacle. Value z = 2 is set when buffer cannot be placed onto this region (buffer obstacle area). Value z = 0 is when the area are possible for routing path and for buffer placement location. III.
There are several parameters of VLSI routing need to be applied in PSO algorithm. Each of the solution of path routing in each iteration is represented by one particle of PSO. In each particle there exist seven vector of position which is until . This variable is chose so that the will represent the location of a node in grid graph; is a location in grid graph measured from origin along x-axis and is the location in grid graph measured from origin along y-axis. These consecutive nodes if connected together will form a complete path from source to sink. A path in this Grid graph is actually a particle, s in PSO algorithm. The position of this PSO particle will be updated after iterations as mention in Eq. (2). Figure 4 shows the orientation of the routing path from source to sink or a PSO particle. Refer to Figure 4, we used a maximum number of 8 dogleg. Thus it is why we have seven position vectors in a particle to completely represent a path (particle). As shown in Figure 4, the value of may be varies according to PSO algorithm. For example, refer to Figure 4, the location of point A will be denote by coordinate vector ( in the form of (column, row). Thus refer to the same figure, the complete routing location from source to sink in form position vector is
(a)
0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0
0 2 2 2 2 2 2 0 0
0 2 2 1 1 2 2 0 0
0 2 2 1 1 2 2 0 0
0 0 0 1 1 0 0 0 0
0 0 0 0 0 0 0 0 0
MODELLING IN PSO
0 0 0 0 1 0 0 0 0
(b) Figure 3: (a) Location of obstacle (b) Corresponding vertex value
C. Determine the value in grid-graph Refer to Figure 4, in order to differentiate the location of source and sink (dark), buffer obstacle (gray) and wire obstacle (dark) the corresponding value of each vertex location is represented as in Figure 3(b). The detail of the value set for the VLSI routing area is
and in the form of coordinate (column, row), the location of a complete path is
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algorithm can be compared to benchmark test graph size 22x17. For the test graph shown in the Figure 5, the model parameters are: source resistance is 140 , load capacitance at the sink is 0.002 pF, resistance and capacitance of the wire segment are 58 and 0.042 pF respectively. We used one type of buffer with input capacitance, output resistance and intrinsic delay of 0.002pF, 140 and 40 ps respectively. The areas in the test graph are as explained in Figure 3. As a validation test, this algorithm finds the optimal path with simultaneous buffer placement as shown in Figure 5(b) which agrees with the solution provided by Zhou et al [2]. The algorithm return value of interconnect delay equal to 521.73 ps. This result verifies that this algorithm is correct in finding the optimal end-to-end delay. The graph in figure 6 shows that the entire particle is converged at the iteration number equal to 26. Even though we set the maximum iteration is 400 and the run time until maximum iteration is 1 minute 17 seconds but convergence at iteration 26 shows that this algorithm can find the optimal solution in short time.
where , are the coordinate of source and sink respectively. Notice that from (1), the position of a particle is presented by vector position in the VLSI grid graph. This vector is also applies to all particle velocity. Thus a particle i with the position and velocity are presented as
(8)
D. Fitness function calculation
V.
The fitness function for the algorithm is the delay time calculated accumulatively from source to sink. This calculation might include both wire segment and wire segment terminated with buffer. After a complete path is obtain in PSO algorithm as explained previously, then to make the algorithm become simultaneous routing, thus the proper buffer location need to be determined before the fitness function (in this case the interconnect delay) can be calculated. For a path distance with number of vertex is from source to sink, the fitness function can be referred to following equation:
CONCLUSION
This study has introduced a new approach of simultaneous routing and buffer insertion with the existence of obstacles in VLSI. The proposed novel algorithm in PSO model is heuristic technique. Thus the solution given from proposed algorithm might not the exact best solution but this algorithm assured to be simpler in term of calculation and in getting optimized solution. However, in PSO it is normal to have the solution which is not the optimal because of local minima case. But this phenomenon is considered minority case. The simplicity and the ability to model the problem into PSO parameter makes this algorithm is easier to be further improve. For the future work, extension from this finding is to apply binary PSO in the algorithm and also integrate PSO solution for buffer placement.
(9)
ACKNOWLEDGMENT This work is financially supported the Ministry of Science, Technology, and Innovation (MOSTI) by ScienceFund (Vote 79361), and the Ministry of Higher Education (MOHE) by the Fundamental Research Grant Scheme (FRGS) (Vote 78536).
For buffer placement, after value p is obtained then it is divided into 6 segments. This segment is made to have at most 1 buffer for minimizing the interconnect delay. However the buffer allocation in a complete path is placed randomly thus we make the looping for 200 times and get the best fitness time. From the value of and the corresponding buffer location, the delay time can be determined using Elmore delay within iterative calculation starts from vertex no 1 until vertex . IV.
REFERENCES [1] [2]
SIMULATION
This section discusses simulation result to verify the proposed algorithm. We used a case study for graph size 22x17 used in [2]. In order to verify the proposed technique, we used all the parameter for wire, buffer, source and sink to be same as in [2], thus the validation of this PSO
[3]
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A.P. Engelbrecht, 2005 “Fundamental of Computational Swarm Intelligence”, Wiley. Zhou. H et al. 2000. Simultaneous Routing and Buffer Insertion With Restrictions on Buffer Location. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 19:819-824 N. Shaikh-Husin and M. Khalil Hani, “Optimal Routing Algorithm for Minimizing Interconnect Delay”, in proceeding of the 2007 International Conference on Robotics, Vision, Information, and Signal Processing (ROVISP ’07), pp. 345-349, Nov 2007
[4]
[5] [6]
(a)
(b) Figure 5: (a) Test graph 22 x 17 (b) Solution for test graph
Figure 6: PSO convergence curve
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