A robust contactless capacitive communication link for high power battery systems M.M. Wenger, R. Filimon, V.R.H. Lorentz, M. März Department of Power Electronics Fraunhofer IISB D-91058 Erlangen, Germany
[email protected] Abstract—Large Li-ion battery systems are being used in a growing number of applications. Due to lack of standards and various requirements, the battery systems have to be specifically designed for each application. This need for a specific design also affects the battery monitoring circuit. In order to reduce design effort, distributed battery monitoring systems integrated into the cells were proposed. Economies of scale allow these circuits to be produced at low cost per unit as they will be needed in every single battery cell. One of the major challenges of the distributed battery monitoring concept is the communication link for the monitoring circuits: it has to be robust, reliable, and easy to install. As a possible solution, a capacitively coupled data transmission link for a battery system consisting of up to 100 smart battery cells is investigated by simulation and experiment. Relevant influence factors of the physical implementation on a capacitive voltage divider determining the transmitted data signal are identified and evaluated, considering application specific constraints. As a result, a suitable signal conditioning circuit using frequency shift keying (FSK) modulation is proposed and experimental results obtained with a prototype implementation of the proposed circuit are presented. Keywords— battery management; BMS; battery monitoring; data transmission; smart battery cell; AC coupling; frequency shift keying; FSK
I.
INTRODUCTION
In spite of existing standards and ongoing standardization activities in the field of battery cell form factors [1] this trend is still not reflected in the broad market. Other than in form of battery company buyout or merging, currently no reduction of different form factors can be observed. Only some cylindrical cell formats, preferably used in the consumer electronics field, such as the 18650 format, can be identified as industry wide standards. Consequently, engineers working on battery systems face a situation where there are many form factors for battery cells and several integrated circuits for cell monitoring on the one hand, and a growing number of different applications they have to provide a battery solution for on the other. A possible approach to reduce the complexity of this design challenge might be found: the concept of the smart battery cell. With smart battery cells, there is no need to design a specific monitoring circuit for every application. The monitoring circuit is integrated in the cell and comes as part of the cell.
II.
STATE OF THE ART
In large state of the art battery systems the, series connection of battery cells is often divided in modules, commonly consisting of 5 to 18 or even more cells. These battery systems often rely on specialized integrated circuits (IC) for battery monitoring [2]. Meanwhile, several of these monitoring ICs are commercially available; some of them having already reached their 3rd or 4th generation. These ICs are able to monitor a series connection of up to 18 battery cells each. Often they also provide a propriety communication interface in a daisy chain or bus configuration. Great improvements were achieved in measurement accuracy, current consumption, and communication robustness. Despite all these improvements, a reasonable amount of effort is still necessary to design the circuit around the monitoring ICs. This circuit has to be adopted for every new design where either cells with a different form factor, or just a different number of cells are used. An alternative concept is the smart battery cell concept with electronics for monitoring and communication integrated into the cells. Several approaches in this direction have been presented in the past. In [3] a distributed battery monitoring system is described that is able to track the entire life of the cell and thereby obtaining valuable information on the battery’s state of health. The circuit uses an isolated interface to communicate with the higher level battery management system. As an alternative wireless communication interfaces were suggested. In the EC funded research project SmartLIC a communication interface based on RFID was developed [4]. In another research project, funded by the German Ministry of Education and Research (BMBF), called BATSEN, a similar approach based on radio transmission was chosen [5]. Another possibility to transfer data between the single cell monitoring units and the battery management system without additional wiring is based on power line communication (PLC) [6]. But, especially in automotive related applications, a lot of noise from inverters and DC/DC converters is expected so that reliable data transmission will become quite challenging. An alternative concept presented in [7] proposes the use of a differential capacitively coupled data interface. It eliminates the need for connectors as well as a dedicated galvanic isolation element at every cell, and therefore helps to increase system reliability. Reviewing literature on capacitively coupled communication links shows that they are often used for high data rate, point-to-point communication between ICs. In some
cases these ICs are in very close proximity to each other like in a System in Package (SiP) and no dedicated bus structure is necessary as in [8] and [9]. There are also cases of point-topoint communication between ICs on a printed circuit board (PCB) with rather short bus lengths up to 30cm as in [10]. In [11] and [12] a capacitively coupled, multidrop bus system connecting several ICs on a PCB is described. The bus length is also in the range of about 30cm. In this paper, the focus will be on the capacitively coupled interface for the smart battery cell. After a brief system overview, first some basic requirements and boundary conditions for the communication link in a battery system will be gathered. Next, a simplified equivalent circuit of the communication line will be established. Measurements on an experimental setup are used to parameterize the circuit components and to verify the relevance of the considered influence factors. Considering simulation results for a complete system a suitable signal conditioning method is proposed and tested. III.
CAPACITVELY COUPLED DATA LINK
A smart battery system with a bus structure as shown in Figure 1 will be investigated. The battery management system (BMS) acts as a master in this system; the smart cells act as slaves allowing bidirectional data transmission on a single bus without collision detection. The advantage of the bus topology over a daisy chain topology is that, in case of a faulty smart cell, the communication to the other cells is not compromised. Further, this topology allows synchronizing the voltage measurement by transmitting a trigger signal from the BMS to the smart cells. The BMS is directly connected to the bus lines, which carry a differential signal. Differential signaling makes the signal transmission less sensitive to common mode errors. By directly connecting the bus to the battery management unit, they both have the same reference potential, otherwise the bus potential would be floating and an additional capacitive coupling unit would add another barrier to the signal path. The smart battery cells are all parallel connected to the bus via capacitive coupling areas. Figure 2 shows a block diagram schematic of the communication bus topology. There is a receiver and transmitter unit on the master as well as on the slaves to enable bidirectional communication.
The required communication data rate depends, of course on the number of series connected cells. In order to determine the required data rate, a voltage measurement resolution of 12bit sampled 10 times per second will be assumed. For the temperature, an 8bit measurement once per second seems sufficient. Considering a master slave communication protocol using identifiers and CRC and assuming a tolerable bus load of about 20% a data rate of about 5kbit/sec per cell should be sufficient. In a series connection of about 100 smart cells, the data rate adds up to 500kbit/sec. Further assuming a maximum width of 5cm per cell when using prismatic cells [1] and considering a safety margin of 100%, the bus length will not exceed 10m. B. The capacitive interface The capacitive interface consists of two flat conductor bus lines and two corresponding conductive areas on the battery in close proximity, but not galvanically connected thereby, forming the two coupling capacitors. Figure 3 shows a cross section of the coupling area. On top, the two isolated flat wires of the bus can be seen. They are in close proximity to the conductive areas on the cell surface that are covered by an isolation layer. The isolation layers act as a dielectric in the coupling capacitor. The coupling capacitance CC depends on the distance d between the conducting areas and the flat conductors of the bus, the relative permittivity εr of the isolation material, and the overlapping area A as given in Equation 1. A CC ε ε · (1) d The distance d is ideally equal to the sum of the thickness of the isolation cover layers. In order to compensate for misalignment of the flat conductor bus, the coupling area sections on the cell are slightly wider than the flat conductors on the bus as shown in Figure 3. Feasible values for the coupling capacitance lay in the area of several tens of picofarads.
A. Requirements In order to reach sufficient voltage levels to power the drive train of an electric vehicle (EV) in an efficient manner, a series connection of about 100 Li-ion cells is necessary. The exact number depends on the cell chemistry and the requirements of the drive train. For the investigations in this paper 100 will be the maximum number of cells connected by one bus.
Figure 2: Block diagram schematic of the proposed communication bus topology
Figure 1: Proposed topology of a battery system using smart battery cells and a capacitvely coupled data transmission link
Figure 3: Cross section, top view and 3D view of the capacitive interface
Considering a velocity factor of about 0.5,the resulting length of 30m is well above the maximum expected bus length of 10m. However, the mutual capacitance between the conductor pair is of importance and will be considered in the equivalent circuit as the lumped capacitance CMUT. The exact value for the capacitance per cable length CMUT will be obtained by measurement in the experimental section of this paper. Typical values for CMUT lay in the range of several tens of picofarads per meter cable consequently adding up to several hundred picofarads in a system with 10m cable length. Another important capacitance is the capacitance between the bus wires and ground CGND. When no shielding layer is used as in Figure 4a), the capacitance cannot be determined easily as it depends on the surrounding and the exact bus routing. Figure 4b) shows a cross section with added shielding. In the equivalent circuit the two capacitances CGND1 and CGND2 can be combined to a single capacitance CGND located between the bus wires in parallel to CMUT. In consideration of the requirements, the bus does not have to be treated as a transmission line and the properties of the bus can be represented by lumped components. This is especially important, as a change of line impedance, which would cause adverse reflection of the signal without additional measures, is to be expected at each coupling area. D. AC Coupling The equivalent circuit for a simple master slave configuration is shown in Figure 5. CC represents the coupling capacitors; CIN and RIN are the input capacitance and input resistance of the receivers (RX). The transmitters (TX) generate a differential signal that will be transmitted on the bus. When they are not used, the transmitters are set to tri-state mode in order to reduce their effect on the bus. When the master sends a data signal to the slave (Figure 6, orange trace), the differentiating behavior of the coupling capacitances will cause the signal received by the slave to look like the blue trace in Figure 6. A positive peak can be observed for every rising edge and a negative peak for every falling edge. The height of the peak depends on the rise and fall time of the data signal, especially for low dV/dt, but mainly also on the data signal swing reduced by a capacitive voltage divider, consisting of the coupling capacitances CC and the input capacitance CIN at the receiver. The decay pattern of the peak signal mainly depends on the input resistance RIN in parallel of the input capacitance. With higher RIN, the decrease is slower and the peak becomes broader. In case of only one master and one slave, the communication link is symmetrical and the same dependencies apply for a signal sent from the slave to the master.
Figure 4: Flat conductor cable cross section and equivalent circuit
C. The flat conductor bus cable As a simplification, the flat conductor cable may be seen as ideal, in the sense that it has no influence on the transmission. This assumption is true for low signal frequencies and short lengths. A first indication of what that means in this application is given by the rule of thumb stating a cable should be seen as a transmission line if its length is greater than 1/10th of the signal wavelength λ. In case of 500kHz, 1/10th λ is about 60m.
Figure 5: Simple equivalent circuit of a single master single slave configuration
Figure 8: Uplink communikation path
F. Slave to master communication (uplink) If one of the slaves sends a signal to the master, all the other slaves add to the capacitive voltage divider. Figure 8 shows the situation for uplink communication. Equation 3 gives the ratio of the received signal VRX to the sent signal VTX.
Figure 6: Signal before (orange trace, bottom) and after (blue trace, top) capacitive interface
VRX VTX
Figure 7: Single master, multi slave system (downlink)
The situation is different when there are multiple slaves in the system, as shown in Figure 7. The receivers in the slaves are represented only by their input capacitances and input resistance for simplicity reasons. With one master and several slaves, the direction of the data flow becomes important. The master to slave communication shall be called downlink, whereas the slave to master communication will be referred to as uplink. E. Master to slave communication (downlink) The slaves are connected in parallel, so when the master transmits to the slaves, the situation is similar to the case where there is only one master and one slave, except that the capacitive load seen by the master transmitting unit is higher. In case of a complete battery system with 100 slaves and 10m bus length, the output driver has to work with an expected capacitive load of several hundred picofarads. The signal is determined by a capacitive voltage divider consisting of the coupling capacitances CC and the input capacitance CIN as in Equation 2. VRX VTX
CC 2 · CIN
CC
(2)
When CIN is small compared to ½ CC, the signal at the slaves will be hardly damped. A signal conditioning circuit as proposed in [7] can be used to regain the signal easily. The cable capacitances CMUT and CGND do not have influence on the signal because they are in parallel to the signal source. They do, however, have direct influence on the capacitive load seen by the output driver.
· CC · CC
CIN
n·
CC ·CIN ·CIN CC
l · CMUT
(3)
In order to obtain a large signal at the receiver, the ratio in Equation 3 has to be maximized, which can be achieved by minimizing terms 2, 3, and 4 in the denominator. The second term, representing the input capacitance of the master, has to be as small as possible. The third term represents the other n slaves in the system. It is n times the series connection of the two coupling capacitances and the input capacitance of a slave. Obviously, the resulting capacitance of term 3 is always smaller than the smallest capacitance in the series connection. Therefore, if the input capacitance is chosen as small as possible, the effect of the additional slaves in the system can be reduced significantly. The fourth term in the denominator represents the mutual capacitance of the flat conductor cable where l is the cable length. CGND would also contribute to the capacitive voltage divider of Equation 3 as a summand in the denominator and therefore would further decrease the signal. In a first approach, an unshielded cable with negligible CGND will be assumed. However, it does make sense to use a shielding layer in order to have a defined capacity to ground that is not dependent on the way the cable is routed in the application. It has to be evaluated if the advantage outweighs the signal reduction. For this paper, CGND will not be considered. In conclusion, the coupling capacitance should be as big as possible whereas the input capacitance and the capacitance added by the cable should be as small as possible. Still, a damping factor of several tens i.e. 20…40dB is expected for a complete system. G. Experiment In order to reduce complexity, a mockup of a 15 cell battery module is used for experiments. The measured voltage levels will of course be different for the full system consisting of 100 cells, but the module with 15 cells will already allow verifying the simulation results and will give a strong indication for the trustworthiness of the simulations on system level.
Figure 9: Battery module mockup (left); Detail on the flat conductor bus (middle); Detail on the capacitive coupling areas (right);
Figure 9 shows a picture of the experimental set up. 4 PCBs emulating 4 slaves each are mounted onto the battery module frame. The coupling area in the upper left is left unused. On top of the interfacing areas, the flat conductors of the bus can be seen. For the experiment, the flat conductor is pressed onto the PCB with a foam cushion (not seen in the photo) in order to ensure it is in close proximity to the coupling areas. With an Agilent 4294A impedance analyzer, the coupling capacitance CC in this set up is measured as 25pF and CMUT as 68pF for 1044mm bus length. The signals are generated by an Agilent 33522A wave form generator feeding a prototype transmitter IC. In order to investigate the uplink communication, the transmitting slave is located on the upper right at the end of the bus. The input capacitances of the other slaves are emulated by adding a resistor of 3kΩ and a capacitor of 1pF at every slave. On the receiving side, an oscilloscope (LeCroy HRO66Zi) is used to record the incoming signals. The probe has an input resistance of 10MΩ and an input capacitance of 9.5pF. In order to get conditions similar to the real application, a 3kΩ resistor is put in parallel to the input. The input capacitance that is higher than in the application will cause a slightly lower signal at the receiver. This is considered in the simulations used for verification. Figure 10 shows the result of an uplink data transmission with 500kbit/sec (TX Signal – orange trace). The signal at the receiver (RX Signal – blue trace) conforms with the simulated signal (RX Simulation – pink trace). It shows that the relevant influence factors are correctly identified and may be used as a basis to predict the system level behavior by simulation.
H. Simulations A circuit simulation considering all aspects mentioned previously will give an estimation of what the signal received by the master in a system consisting of 100 smart battery cells might look like. Table 1 gives the values of the components in the equivalent circuit and how they were obtained. Table 1: Input parameters for the system simulation
No. of Slaves CC CIN RIN CMUT CGND Line length l fSIG
100 25pF (experimental) 1pF [13] 3kΩ [13] 65pF/m (experimental) Not considered 10m 250kHz
In the previous investigation, the uplink was identified as more troublesome due to adverse ratio in the governing voltage divider described in equation 3. Therefore, the system level simulations will focus on the uplink data path. Here the calculated ratio of the capacitive voltage divider is about 1/60, which means that only a very weak signal can be detected at the master. A look at the result of an AC analysis in form of a Bode plot in Figure 11 reveals the high pass behavior of the system. It shows that the calculated value of 1/60 (-35dBV) is only true for very high frequencies. In the relevant range of 250kHz the ratio is only about 1/140 (-43dBV). Additionally, on the lower frequency end noise from DC/DC converters or inverters connected to the battery system is to be expected in the range of 100kHz and the according harmonics.
Figure 11: AC Analysis of the uplink data transmission path (1V Signal amplitude)
Figure 10: Uplink communication on 15 cell module mockup: RX signal measurement (blue trace – top); TX signal measurement (orange trace – middle); RX signal simulation (pink trace – bottom)
Figure 14: Receiver circuit on the master side
Figure 12: Signal at the receiver using FSK modulation with 3MHz mark and 2MHz space frequency
I. Improved signal conditioning A very simple solution would be using Manchester Coding in combination with a higher data rate. This allows the signal to be shifted out of the noisy low frequency regions. Unfortunately, this also increases the used bandwidth unnecessarily. In order to reach higher frequency ranges without increasing signal bandwidth some kind of modulation is required, such as amplitude shift keying (ASK) or frequency shift keying (FSK). Considering the line length of 10m, the 1/10th λ thumb rule would limit the maximum frequency to about 3MHz. Therefore, a possible approach would be using a FSK modulated signal in the frequency range from 2 to 3MHz. Figure 12 shows a simulation of how such a FSK modulated data signal might look at the receiver. The implementation on the master side requires an amplifier at the input followed by a band pass filter and a FSK decoding block as shown in Figure 13. On the slave side, a FSK modulation circuit has to be added. For prototyping purposes, it can be easily implemented in complex programmable logic device (CPLD). The modulated signal is then directly connected to the output line driver. The receiver circuit on the master side shown in Figure 14 is a bit more sophisticated. As discussed before, the input signal will be strongly damped by the capacitive voltage divider described in Equation 3. Therefore, an instrumentation amplifier with a low input capacitance is used at the input of the receiver. It also converts the differential signal to a single ended signal. The circuit uses only a single supply voltage, so the signal at the output of the instrumentation amplifier has an offset of 1/2 supply voltage.
Figure 13: Block diagram of FSK signal conditioning circuit
In order to increase the signal to noise ratio (SNR), a band pass filter is added. In this case, a filter IC comprising 2 matched operational amplifiers is used. The filter provides a differential signal at its output. The filtered signal then passes a differential amplifier with a very high gain. It removes the offset from the signal and makes it suitable for further digital processing in the CPLD running the FSK de-modulator program. After the CPLD, the restored signal is passed on to the microcontroller for further processing.
Figure 15: Signal Recovery
Figure 15 shows how the original signal is recovered in the experimental setup simulating a 15 cell module. A data signal with 500kbit/s (TX Signal – blue trace) is transmitted. After the band pass and the differential amplifier (Digital Input – orange trace), the signal is finally recovered by the demodulator on the CPLD (Recovered Signal – pink trace). IV.
CONCLUSION
The capacitively coupled data transmission link of the smart battery cell was characterized and relevant parameters were identified and verified in an experimental set up. Considering the application specific constraints for battery systems consisting of up to 100 smart battery cells, a signal conditioning circuit using a FSK modulation with a mark frequency of 3MHz and a space frequency of 2MHz was proposed. A prototype implementation was used to demonstrate that the signal conditioning is suitable for data transmission in the given application.
ACKNOWLEDGMENTS The research leading to these results has received funding from the European Union as part of the ENIAC JU under grant agreement n° 270693-2 (“MotorBrain”).
[6]
[7]
REFERENCES [1] [2]
[3]
[4]
[5]
DIN SPEC 91252 Brandl, M.; Gall, H.; Wenger, M.; Lorentz, V.; Giegerich, M.; Baronti, F.; Fantechi, G.; Fanucci, L.; Roncella, R.; Saletti, R.; Saponara, S.; Thaler, A.; Cifrain, M.; Prochazka, W., "Batteries and battery management systems for electric vehicles," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 , vol., no., pp.971,976, 12-16 March 2012 doi: 10.1109/DATE.2012.6176637 Baronti, F.; Fantechi, G.; Roncella, R.; Saletti, R., "Intelligent cell gauge for a hierarchical battery management system," Transportation Electrification Conference and Expo (ITEC), 2012 IEEE , vol., no., pp.1,5, 18-20 June 2012 doi: 10.1109/ITEC.2012.6243471 Otto, A.; Rzepka, S.; Mager, T.; Michel, B.; Lanciotti, C.; Günther, T.s; Kanoun, O., “Battery Management Network for Fully Electrical Vehicles Featuring Smart Systems at Cell and Pack Level,” 2012 – Advanced Microsystems for Automotive Applications, pp. 3,14, 2012 doi: 10.1007/978-3-642-29673-4_1 Schneider, M.; Ilgin, S.; Jegenhorst, N.; Kube, R.; Puttjer, S.; Riemschneider, K.; Vollmer, J., "Automotive battery monitoring by wireless cell sensors," Instrumentation and Measurement Technology Conference (I2MTC), 2012 IEEE International , vol., no., pp.816,820, 13-16 May 2012 doi: 10.1109/I2MTC.2012.6229439
[8]
[9]
[10]
[11]
[12]
[13]
Gouret, W.; Nouvel, F.; El-Zein, G., "Powerline Communication on Automotive Network," Vehicular Technology Conference, 2007. VTC2007-Spring. IEEE 65th , vol., no., pp.2545,2549, 22-25 April 2007 doi: 10.1109/VETECS.2007.524 Lorentz, V. R H; Wenger, M. M.; Grosch, J. L.; Giegerich, M.; Jank, M. P M; März, M.; Frey, L., "Novel cost-efficient contactless distributed monitoring concept for smart battery cells," Industrial Electronics (ISIE), 2012 IEEE International Symposium on , vol., no., pp.1342,1347, 28-31 May 2012 Culurciello, E.; Andreou, A.G., "Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.53, no.12, pp.1348,1352, Dec. 2006 doi: 10.1109/TCSII.2006.885073 Yu-Shiang Lin; Sylvester, D; Blaauw, D., "Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling," Solid-State Circuits, IEEE Journal of , vol.44, no.4, pp.1156,1166, April 2009 doi: 10.1109/JSSC.2009.2014024 Lei Luo; Wilson, J.; Mick, S.; Jian Xu; Liang Zhang; Erickson, E.; Franzon, P., "A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver," Custom Integrated Circuits Conference, 2006. CICC '06. IEEE , vol., no., pp.773,776, 10-13 Sept. 2006 doi: 10.1109/CICC.2006.320976 Jongsun Kim; Verbauwhede, I.; Chang, M.-C.F., "A 5.6-mW 1Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus," Solid-State Circuits, IEEE Journal of , vol.40, no.6, pp.1331,1340, June 2005 doi: 10.1109/JSSC.2005.848030 Kosuge, A.; Mizuhara, W.; Miura, N.; Taguchi, M.; Ishikuro, H.; Kuroda, T., "A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partialresponse channel transceivers," Design Automation Conference (ASPDAC), 2013 18th Asia and South Pacific , vol., no., pp.91,92, 22-25 Jan. 2013 doi: 10.1109/ASPDAC.2013.6509571 LTC6406 data sheet; Linear Technology Corporation
