Active High Power Conversion Efficiency Rectifier With Built-In Dual ...

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 2, NO. 3, SEPTEMBER 2008

Active High Power Conversion Efficiency Rectifier With Built-In Dual-Mode Back Telemetry in Standard CMOS Technology Gaurav Bawa, Student Member, IEEE, and Maysam Ghovanloo, Member, IEEE

Abstract—In this paper, we present an active rectifier with high power conversion efficiency (PCE) implemented in a 0.5- m 5 V standard CMOS technology with two modes of built-in back telemetry; short- and open-circuit. As a rectifier, it ensures a , taking advantage of active synchronous rectification technique in the frequency range of 0.125–1 MHz. The built-in complementary back telemetry feature can be utilized in implantable microelectronic devices (IMD), wireless sensors, and radio frequency identification (RFID) applications to reduce the silicon area, increase the data rate, and improve the reading range and robustness in load shift keying (LSK).

PCE

80%

Index Terms—Back telemetry, CMOS, full-wave rectifier, implantable microelectronic devices, inductive link, radio frequency identification (RFID), wireless.

I. INTRODUCTION

S

IZE-CONSTRAINED high power implantable microelectronic devices (IMD) such as retinal and cochlear implants, low-cost passive radio frequency identification (RFID) tags, and many wireless sensors cannot accommodate any internal energy sources in the form of batteries due to their low energy density, high cost, and limited lifetime [1]–[5]. There is also a need for data to be transferred from such systems to the outside world which may include the status of the implant, a feedback loop, or other stored or collected information [4], [5]–[12]. In applications where high data rates are not necessary, wireless power and bidirectional data transmission can occur by modulating a single 20 MHz and using load-shift keying (LSK) carrier at through an inductive link, as shown in Fig. 1. LSK requires either a good coupling between the transponder and reader coils or large variations in the impedance seen across the transponder coil [5], [13]. With the size of the transponder being limited, the small coupling, , between the coils forms a bottleneck in power and Manuscript received November 07, 2007; revised February 11, 2008 and April 04, 2008. Current version published October 24, 2008. This work was supported in part by the College of Engineering at North Carolina State University (NCSU), Raleigh. This paper was recommended by Associate Editor M. Sawan. G. Bawa is with the NC-Bionics Laboratory, Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695, USA (e-mail: [email protected]). M. Ghovanloo is with the GT-Bionics Laboratory, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TBCAS.2008.924444

Fig. 1. Block diagram of a generic system for wireless power and data transmission across an inductive link. Our focus, here, is on the gray box.

data transmission. On the power front, it is imperative for the rectifier to be extremely efficient to convert the small received ac power to dc and present it to the load with minimum dissipation. A more efficient rectifier can deliver a given amount of power for a lesser voltage induced across the secondary coil. Thus, it requires a smaller coupling coefficient, , and allows for a greater relative distance between the coils. Active rectifiers have been proven to be more efficient compared to their diode-connected passive counterparts in several prior designs [14]–[17]. They also generate less heat for the same amount of power being delivered to the load, keeping the IMD and its surrounding tissue cooler [18]. On the data front, it is important to maximize the changes in transponder impedance variations to compensate for the small coupling coefficient and overcome noise and interference on the reader [5]. Most traditional LSK methods rely on the nominal loading of the transponder to induce the impedance change. If the loading varies over time, which is the case especially in more complex systems, the reading range will be adversely affected because one should always consider the worst-case loading in designing the back telemetry link. We hereby present a high power conversion efficiency (PCE) active back telemetry rectifier (ABTR), which has built-in dualmode LSK capability, both open- and short-circuit, enabling transfer of data back to the reader at higher rates or over further distances, while accommodating varying load conditions. This is an improvement over an earlier diode-connected version of this rectifier described in [19]. II. CIRCUIT DESCRIPTION The complete circuit schematic of the ABTR is shown in Fig. 2, and simulated waveforms at some of the important nodes

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BAWA AND GHOVANLOO: ACTIVE HIGH PCE RECTIFIER

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Fig. 2. Complete active back-telemetry rectifier (ABTR) schematic for forward power and reverse data transmission over an inductive link.

TABLE I ACTIVE BACK TELEMETRY RECTIFIER MODES OF OPERATION

Fig. 3. Simulation results showing the coil voltages (V ), gate and bulk voltages for P (V V voltage (V ). f = 1 MHz. tively), and the dc output voltage (V

and V and V

), divided , respec-

are shown in Fig. 3. The rectifier has three modes of operation namely, Rectifier, short-coil (SC) , and open-coil (OC), which are summarized in Table I. When the two ABTR logic inputs , the circuit operates as a full-wave are low rectifier providing an unregulated dc supply to the load. The basic architecture of the rectifier is similar to [19], wherein the , while the main rectifying elements are the pMOS pair, provide the current path back to the coil. In nMOS pair,

the positive half-cycle when , as a result of recto via tifier switch activation, current flows from , from to Ground (i.e., p-type substrate) via , via . Therefore, during rectifier and from Ground to conduction, and V by the load current times the channel resistance of the switching elements or the voltage across drain-substrate parasitic diode, whichever is smaller. These effects are visible in Fig. 3. is given by , which is dyThe bulk potential of and namically controlled to be connected to the higher of , at all times. This helps minimizing latch-up, body effect, and substrate leakage problems as explained in [20]. However,

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instead of diode-connecting for rectification, as we did in [19], leading to dropout voltages across each pMOS above the , here we actively drive the gates of threshold voltage, via a pair of high speed comparators, , to bias in the deep triode region during conduction. This would result in a significant reduction in the MOS channel resistance and consequently the rectifier dropout voltage [21], [22]. compare the coil voltages and the output dc . If , the gates of are pulled voltage to ground, pushing them deep into the triode region. If , the gates of are connected to their dynamically controlled body potential, , forcing them to cut off. Since at steady state the switching occurs almost at the peak of the input coil voltage, depending on the output ripple, the cross-connected also stay in deep triode while conduction takes place, thus providing maximum conductance to the current path and minimizing the ABTR dropout voltage. To ensure proper rectifier operation as described above, we have employed a pair of comparators with hysteresis, shown in box-2 of Fig. 2 [21]. Each comparator has a folded cascode input stage to perform signal comparison even above the rail with some power dissipation overhead (see Table III). It is followed by an output stage to ensure rail-to-rail swing. The middle stage is essentially a high-speed latch, which provides noise reduring the conduction jection and immunity to dips in phase. This dip, which can be seen in Fig. 3, is due to the curand , when rent passing through the rectifying elements , causing to become slightly negative and hence . lowering , when The comparators delay at the onset of switches are expected to be open, can lead to flow of current from the ripple rejection capacitor, , back to the coil. This reverse current can cause coil voltage distortions, increased due to power dissipation in the switches, and decrease . To account for the comparators delay, a loss of charge from lossless capacitive divider is employed which , at the generates a reduced version of the coil voltage, comparator inputs. This would expedite comparators’ toggling, and has a phase lead effect, which reduces the reverse currents. A side effect of the capacitive divider is, however, an additional firing to close when (see delay in F and Fig. 3). At nominal loading conditions with k , the dip in was observed to be 101 mV in simulations and correspondingly lowered by 94 mV for an input division ratio set to 93%. The hysteresis window was, therefore, set to be 100 mV, as a safe margin. , is too low and the comAt startup, the output voltage, parator outputs are unpredictable. Thus, we employed a small , similar to [19], in pardiode-connected startup rectifier allel to the main rectifier to generate a temporary stable supply, , just for the comparators and the bias-generation circuitry. Once stabilizes by charging up to a certain level ( 3.5 V), a voltage monitor circuit, shown in box-5 of and together via , turning the Fig. 2, connects startup rectifier off due to its larger dropout. The voltage monitor has no static power dissipation. , the secondary In the SC mode of operation tank is shorted by pulling the gates of up to the

Fig. 4. Die photo of the active back telemetry rectifier chip fabricated in AMI 0.5-m standard CMOS process (0:45 0:9 mm ).

2

highest on-chip voltage, . This is accomplished through a pair of on-chip level-shifting multiplexers, (box-3, Fig. 2), which can convert any on-chip logic level to reduces Ground. The small resistance presented across , thereby decreasing the voltage across its quality factor, and the current through it. Since in this mode, pull the gates of high and keep them off. This would from being discharged through . eliminate , In the OC mode of operation is opened by connecting the gates of in the main and startup rectifiers to their respective bulk potentials using . This would increase of tank, increasing and the current through . the voltage across Drastic changes in during SC and OC modes with respect to its nominal value in the rectifier mode, which is de, result in similar changes in and currents pendant on [5]. These changes when due to their mutual inductance, captured by a small resistor or a current-sense transformer on the primary side, as shown in Fig. 1, can be used to demodulate the power carrier amplitude variations and recover the back telemetry data. Dual-mode back telemetry feature of the proand posed rectifier can, therefore, provide more variations in enhance the reading range especially in complex systems where is variable. III. MEASUREMENT RESULTS We have developed a prototype chip for the proposed ABTR architecture in the AMI 0.5- m 3M/2P n-well 5-V standard CMOS process. The die photo is shown in Fig. 4, which active area, excluding the pad frame, is 0.4 mm . The rectifier was powered by an HP-8111A function generator through a pair of planar spiral coils fabricated on PCB [23]. The values for the primary and secondary coils were mea, 2.24 ; and , , sured , 1.56 , using a high precision LCR meter (Instek-LCR819). and were adjusted to resonate at each desired carrier frequency in 2 MHz range, while the rectifier was k and F. The current flowing loaded with into the rectifier was differentially measured across a 10 reand the ABTR input. sistor connected in series between The connection between and Ground was passed through a , ), current sense transformer ( as shown in Fig. 1, and the transformer isolated output voltage,



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Fig. 6. Measured ABTR waveforms showing consecutive OC , Rectifier, and and R SC modes of operation at f k . MHz, C

=1

Fig. 5. Measured rectifier PCE and output dc voltage versus (a) carrier frek , and (b) loading R when f : MHz. quency when and R V V, C F.

(peak) = 5

=1

=1

( )

= 05

called , was directly connected to one of the oscilloscope current. channels to monitor the changes in Fig. 5(a) shows the measured performance of the ABTR at when it is different frequencies in terms of the PCE and in the Rectifier mode and is adjusted at 5 V. We observed that there exists a fine balance between the input capacitive voltage divider ratio, delay, and hysteresis voltage of the comparators (see Section IV). In the present design, we oband V around tained the peak MHz, while was measured in the fre–1 MHz. Fig. 5(b) illustrates the efquency range of fects of on the PCE and for the present ABTR architecture, which also depend on the size of the rectifying elements. k , PCE decreases due to the increased voltage For and , while the switching duty cycle also drop across increases. For k , the output power becomes comparable to the ABTR losses, hence decreasing the PCE. Fig. 6 shows the measured transient waveforms when the MHz and switched between OC, ABTR is operated at rectification, and SC modes, consecutively, by changing its digital inputs at 33 kHz. Even though the SC input is not shown, the effect of each rectifier operating mode and changes in are quite obvious on and . It can also be seen, from , that exponentially discharges in during OC and SC, and recharges during the normal rectifier operation. and Another observation was that the changes in during OC were smaller than those during SC. This was because of the presence of electrostatic discharge protection cir-

= 144 nF

=1

cuitry, shown in box-1 of Fig. 2, as part of the pad-frame structure. These circuits are off during SC mode and normal recincreases tifier operation. However during OC mode, when and go beyond the supply rail, turn on and form a rail and eventually leakage path across the rectifier to the . This leakage path clamps at a diode-drop to the load, and does not allow to increase as much as it above should. In order to demonstrate the ABTR back telemetry operation through SC and OC inputs, and evaluate the effect of dualmode operation on the reading range and bit-error rate (BER), we generated a 200 kb/s Manchester-encoded serial data bit stream using a digital I/O card. A sample segment of the original data stream at 100 kb/s and its Manchester-encoded version are shown on traces 1 and 2 of Fig. 7, respectively. In this experiment, the nominal coils separation, loading, and carrier mm, k , and MHz, frequency were respectively. Data recovery on the primary side involved digi(trace-3 in Fig. 7) at 250 MHz using a digital tization of oscilloscope (Tektronix DPO4034) and processing it offline in were detected to indicate the MATLAB. Zero crossings of carrier signal period and reconstruct the received carrier envelope. There were two types of amplitude variations at the primary; one at high frequency (200 kb/s) due to the rectifier LSK, and the other at low frequency due to fluctuations in the power amplifier output voltage, coils separation, and other sources of interference. The undesirable low frequency interference was elimi, and subtracting it nated by running a moving average on from the carrier envelope information. Thereafter, binarization that were above was performed by checking the peaks of or below the moving threshold. Comparing the resulting waveform, which is shown on trace-4 of Fig. 7, with trace-2 demonstrates the accuracy of the demodulated serial data bits. Finally, the original symbols were recovered by Manchester decoding trace-4 via edge detection and retrieval of pulsewidth information (trace 5). With this setup in place, the BER was measured by comparing the back scattered and received data bit streams for a total of


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Fig. 7. Waveforms showing (from top) the original and Manchester-encoded data bit streams, primary sensed current, carrier envelope, and recovered back telemetry data, which was sent through the ABTR OC input at 200 kHz with f MHz, R k and d mm.

=1

2048 bits (256-bit frames in 8 trials). However, no errors were detected. Considering the facts that a dedicated reader was not utilized and the coil dimensions were not optimized, we simply , that could maindefined the maximum coil separation, as the reading range in our test setup. For tain k , was 28 and 25 mm for SC and OC modes, reto 300 , for SC was respectively. When we reduced for OC was increased to 26 mm, deduced to 23 mm, while spite its subdued operation due to the ESD circuitry. This result was expected because as mentioned in Section I, maximizing the transponder impedance variations can improve the reading range in inductively powered devices. Thus, we could conclude was variable, a combination of SC and OC modes that when increased the reading range in our experimental setup by 12% compared to using only one of these modes similar to the traditional LSK scheme.

=1

= 20

measured differentially in order not to disturb the transponder isolation from the reader. and , To find the relationship between we have further simplified the schematic diagram of Fig. 2 to the is defined equivalent circuit model in Fig. 8. Here is how (1) (2) (3) where is the load -factor and is the unloaded -factor of . It is also possible to find the voltage transfer function , which across the inductive link, derivation is given in the appendix, assuming [24]

IV. DISCUSSION In this section we take a closer look at some of the specific characteristics of the proposed ABTR, which can potentially affect its PCE and performance in back telemetry. A. Variations in Loaded

from measured or simulated If we calculate to give the above equation can be solved for

(5)

in Different Modes of Operation

We talked about variations in the secondary -factor when tank loading in its 3 modes of the ABTR changes the (loaded operation. Here we would like to understand how ) changes and in what range. This in turn depends on the linearized equivalent resistance, , seen through the rectifier and during ABTR input port. Direct measurement of operation is not feasible. Therefore, we calculated them indirectly from other measurable parameters in the setup shown in Figs. 1 and 2. A straight forward set of measurable values could and , which are named and , be the voltages across respectively, when other variable parameters such as , , and are held constant. Obviously, needs to be

(4) , then

We combined the realistic off-chip component and parasitic values from the test setup described in Section III with postat layout extracted ABTR model in SPICE to simulate and MHz. Table II summarizes the and variations in different modes of ABTR operation. changes in a wide range and It can be seen that assumption holds true with k in the Rectifier and OC modes, where (4) and (5) will be valid, but not the SC mode. and when the With this setup, we have also simulated ESD protection circuits are not present and there are no undein the OC mode (in a high voltage sired leakage currents to



189

Fig. 8. Simplified and linearized equivalent circuit description for the inductive wireless link shown in Fig. 2.

Q

AND

R

TABLE II VARIATIONS IN VARIOUS MODES OF RECTIFIER OPERATION FOR

K = 0:1

Z

Fig. 9. Imaginary, real, and magnitude of the transponder impedance, , and its loaded quality factor, , versus the linearized resistance seen through in Fig. 8. ABTR input port

R

process for example). It can be seen that in this case is inwith respect to the Rectifier mode creased and extended even further. This would results in easier back telemetry data demodulation and extended reading range. It should also be noted , tends to decrease that with heavier loading, i.e., lower in the Rectifier mode, while it stays the same in the OC mode, . thereby increasing for the SC or the Rectifier modes with small cannot be computed using (4) and (5) since . In this case Fig. 8 should be analyzed or simulated without the simplifications discussed in the Appendix. According to the simulations using the typical model in the AMI 0.5- m CMOS process, the effective resistance of across is 3 for a gate voltage of is 0.03 for this mode of opera3 V. Hence, the resulting if k compared to tion, which results in a larger the OC mode.

Z

Fig. 10. Reflected impedance ( ) at the primary shown in the complex plane as a function of equivalent loading at the secondary ( ), with ascending from left to right in the range 1 1 k [5].

0

B. Reflected Impedance in Back Telemetry The reflected impedance on to the primary side, , is the key parameter in back telemetry and a function of the impedance at in Fig. 8. It is given by the secondary, (6) (7) (8) Using (1),

Q

in (7) can be converted to a more useful form

(9) change Fig. 9 shows how the imaginary and real parts of as varies from short to 1 k in our setup at MHz. and change with . It can be Fig. 9 also shows how , which corresponds observed that when , the imaginary part of will be negligible to at resonance. In this region, which includes the Rectifier and

R

R

OC modes of operation according to Table II, an increase in (e.g., when switching from Rectifier to OC) results in a , and a reduction in . This is reduction in , an increase in evident in Fig. 6 waveforms. On the other hand, when (e.g., switching from Rectifier to SC), is highly inductive and largely contributed by the inductance of . Similarly, will be highly reactive and therefore, results in both amplitude and phase modulation on the primary side. It can also be inferred from Fig. 9 that for very small values there is a complete dominance of and any changes of would produce little change in . The real part of in peaks at , which corresponds to . Therefore, for heavily loaded transponders that result in , the existence of the OC mode in the proposed ABTR seems to be an effective way in extending the reading range. It is also instructive to look at the locus curve of the reflected impedance in different ABTR modes of operation, which are shown in Fig. 10 for our experimental setup. Reducing


190


Fig. 11. Pie-chart showing the simulation results of the ABTR distribution of input power in the Rectifier mode at maximum efficiency (90.4%) and nominal loading of R k .V V, f : MHz, and C F.

=1

=5

=05

=1

TABLE III ACTIVE BACK TELEMETRY RECTIFIER SPECIFICATIONS

Fig. 12. Simulated rectifier PCE and output dc voltage versus R when ideal are used in the ABTR of Fig. 2 (compare with Fig. (5b). comparators A Operating conditions: V V, f : MHz, C F.

(

)

(peak) = 5

=05

=1

consumed mainly in the buffers employed after the comparator switches (see Fig. 2). The dissipablocks to drive large and ON-resistance tion in the main rectifying elements (P_SWITCHES) is 7.4%, i.e., the bottleneck to a highest achievable PCE. This is despite operating these switches in deep triode region. Even though it is possible to reduce P_SWITCHES by increasing the size of the rectifying elements, it comes at the expense of silicon area and increased parasitic capacitance of these switches. Hence, there needs to be a compromise between the rectifier size, comparator drive capability, and carrier frequency, which is out of the scope of this paper. A detailed theoretical analysis and optimization of the active integrated CMOS rectifiers can be found in [25]. D. Limits to Rectifier Output Voltage reduces the resistive component of (moving from right to left), resulting in load modulation [5]. C. Power Distribution in Rectifier Mode A post-layout simulation of the ABTR circuit in Fig. 2 was performed to analyze the power distribution in various power dissipating elements in the Rectifier mode when it provides the V, maximum PCE based on Section III measurements ( MHz, F, and k ). Fig. 11 shows the result of this simulation in a pie-chart. The rectifier PCE, obtained by dividing the power delivered to the load by the total input power, was 90.4%, which is 5.6% higher than the measured value in Fig. 4. We believe that this discrepancy was resulted from the additional parasitic components, which were not included in the rectifier model, especially those from interconnects and measurement instrumentation. In a real application, such as in Interestim-2B [2], since the rectifier block is going to be part of a system-on-a-chip (SoC), its efficiency is likely to be closer to the higher simulated value. in driver The static dissipation comparators) and bias generator is the quiescent circuitry ( current supplied from (see Table III). The dynamic power in the rectifier is caldissipation culated by subtracting the static power from the total dissipation in the driver circuitry when operating the rectifier. This is

As mentioned in Section II, we have introduced a phase-lead when is being switched OFF to account for the comparator delay and eliminate reverse currents [15], [19]. On the other hand, the loss-less capacitive divider also introduces a phase-lag is being switched ON. The comparator delay also adds when to this lag and results in a notable reduction in the switching duty cycle. In the present design, for example, the input capacitive divider has a ratio of 0.93, which corresponds to a 350 mV dropout voltage at 5-V input. Thus, a lower dropout can be achieved in this architecture by employing a faster comparator and reducing the phase-lead accordingly. E. Limits to Rectifier Efficiency In active rectifiers the comparator characteristics such as delay, power consumption, and output drive capability have a significant effect on the maximum achievable efficiency. To observe the effect of comparator delay on efficiency, we ran simulations on the ABTR post-layout extraction in the same with ideal conditions as in Section IV-C, while replacing comparators that had zero delay, unlimited drive capability, and was swept in Fig. 12 from 10 to no power dissipation. 100 k similar to the measured results described in Fig. 5. The same trend can be observed with the PCE reaching 96.2% for 10 k . This shows that there is only 3.8% power dissipation in the rectifying elements, which is almost half of



191

the amount shown in Fig. 11 with realistic comparators that have 33 ns delay. The reduced power dissipation in the rectifying elements can , be attributed to the increased rectifier switching duty cycle, as a result of eliminating the phase-lead capacitive voltage diand in Fig. 2). This in turn reduces the vider ( and to replenish the average current passing through charge in that is delivered to in every carrier cycle. also depends on the and affects the ripple. Hence, the RC load can also affect the amount of power that is dissipated in the switching elements as can be seen in Fig. 12.

and that the primary and secondary tanks Assuming are often tuned at the carrier frequency, we can substitute (8) in (14) and reach at (15)

Using this in (10) and (11) leads to (16) (17)

V. CONCLUSION An integrated active full-wave rectifier with dual-mode back telemetry has been implemented in a 0.5- m 5-V standard CMOS process and successfully tested. Being able to both short- and open-circuit the transponder LC tank, results in changing the secondary loaded -factor in a wide range, and potentially improves the system reading range. It can also improve the back telemetry data bandwidth in inductively powered devices such as biomedical implants and RFID tags by adding more symbols. The rectifier employs dynamic body voltage regulation, synchronous gate control, and active switches to minimize the dropout voltage across the rectifying elements and increase the ac–dc PCE. Wide-range high speed hysteresis comparators are used with phase-lead to block the reverse current from load to LC-tank, and improve the rectifier efficiency. Most of the rectifier internal power is dissipated in the ON resistance of the switching elements. Faster comparators can potentially reduce the dropout voltage and improve the ABTR efficiency. Table III summarizes some of the ABTR specifications.

Using (14)–(17), we can write the voltage transfer function as (18)

(19) Taking the magnitude of the above equation

(20) Substituting (8) and rearranging (20),

(21) Since

, (21) can be simplified further to give

APPENDIX In this section, we have derived the voltage transfer func, in Fig. 9 which was used in tion across the inductive link, Section IV. We can write the KVL equations for the currents in and , shown as and , respectively (10) (11)

(22) ACKNOWLEDGMENT The authors would like to thank U.-M. Jow from GT-Bionics Lab for helping with the test setup. They also appreciate the free fabrication opportunity provided to them by the MOSIS educational program (MEP). REFERENCES

where

is the reflected impedance on to the primary [24] (12) (13)

The secondary coil voltage is related to its current by (14)

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Gaurav Bawa (S’07) was born in Punjab, India, in 1981. He received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Delhi, India, in 2003. He is currently working towards the M.S. degree in electrical engineering at North Carolina State University, Raleigh. In the summer of 2002, he was an Intern in the Microelectronics Group at University of Udine, Italy, and in fall 2003, at National Instruments, India, in the Motion Control Group. From 2003 to 2006, he worked as a Design Engineer at ST Microelectronics, India. During this period, he was involved in the design and validation of Flash Memory test vehicles in submicron NVM technology, for which he received corporate recognition, and subsequently in the design of analog-to-digital converters for the product division. His current research interests include low-power RF, analog and digital circuit design for biomedical applications. Mr. Bawa is a member of Phi Kappa Phi and Tau Beta Pi.

Maysam Ghovanloo (S’00–M’04) was born in 1973. He received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1994, the M.S. (hons.) degree in biomedical engineering from the Amirkabir University of Technology, Tehran, Iran, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2003 and 2004, respectively. His Ph.D. research was on developing a wireless microsystem for Micromachined neural stimulating microprobes. From 1994 to 1998, he worked part-time at IDEA Inc., Tehran, Iran, where he participated in the developing a modular patient care monitoring system. In December 1998, he founded Sabz-Negar Rayaneh Co. Ltd., Tehran, Iran, to manufacture physiology and pharmacology research laboratory instruments. In the summer of 2002, he was with the Advanced Bionics Inc., Sylmar, CA, working on the design of spinal-cord stimulators. From 2004 to 2007, he was an Assistant Professor at the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, where he founded and directed the NC Bionics Laboratory. In June 2007, he joined the faculty of Georgia Institute of Technology, Atlanta, where he is currently an Assistant Professor in the Department of Electrical and Computer Engineering. Dr. Ghovanloo is an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS. He has been a member of the technical program committee for the IEEE Midwest Circuits and Systems (MWSCAS), International Symposium on Circuits and Systems (ISCAS), and Biomedical Circuits and Systems (BioCAS) conferences. He has received awards in the operational category of the 40th and 41st DAC/ISSCC student design contest in 2003 and 2004, respectively. He has served as a Technical Reviewer for major IEEE and IoP journals in the areas of circuits, systems, and biomedical engineering. He is a member of Tau Beta Pi, Sigma Xi, and IEEE Solid-State Circuits, IEEE Circuits and Systems, and IEEE Engineering in Medicine and Biology Societies.
