Advanced cleaning for the growth of ultrathin gate oxide. P.W. Mertens, T. Beaxda, M. Houssa, L.M. Loewenstein, I. Cornelissen, S. De Gendt, K. Kenis, I.
Microelectronic Engineering 48 (1999) 199-206
ELSEVIER
www.elsevier.nl/locate/ mee
Advanced cleaning for the growth of ultrathin gate oxide P.W. Mertens, T. Beaxda, M. Houssa, L.M. Loewenstein, I. Cornelissen, S. De Gendt, K. Kenis, I. Teerlinck, R. Vos, M. Meuris, and M.M. Heyns a • aImec, Kapeldreef 75, B-3001 Leuven, Belgium
1. I N T R O D U C T I O N For decades cleaning processes in IC manufacturing were very poorly characterized and specified. Cleaning recipes, such the RCA-recipe [1], have been taken for granted. In order to meet the stringent future gate-oxide defect density requirements [2], cleaning strategies with a higher performance have to be developed. Today wet cleaning takes up a significant fraction of the production cost and generates large amounts of waste. Improving the pre-gate cleaning intrinsic quality and at the same time reduce the consumption of chemicals and water urges us to drastically review the cleaning processes. The development of a better understanding of the basic mechanisms involved is believed to be mandatory. In this overview, at first the effect of the chemical state of the surface prior to gate oxidation is studied. Then the detrimental effects of metallic contamination will be highlighted. This provides a basis for the specifications for new cleaning recipes. Pdnsing is re-examined. It will be shown t h a t the final rinsing has a definite impact on the residual metallic contamination. Finally a new process for the in-situ use of organic precursors for C1 in dry cleaning during gate oxidation is proposed. 2. E F F E C T TION
OF
SURFACE
PASSIVA-
It is commonly assumed that in order to obtain good thickness control for ultra thin oxides, the initial silicon surface should not have any chem*This work was partially supported by Esprit LTR ASPYR No. 20182, BMBF (Large Wafers) and IMECs Industrial Affiliation Program on Ultra Clean Processing.
ical oxide but should be hydrogen-passivated as obtained after a proper HF-immersion and rinse. Experiments [3] have shown however, t h a t the thermal oxide grown on chemical oxide passivated silicon (100) surfaces is less t h a n 0.1 nm thicker than on HF-last treated surfaces, as shown in Fig. 1. In fact the oxide passivated surface is preferred as it results in slightly lower oxide thickness nonuniformity. In addition the oxide passivated surface is thermodynamically more stable and less vulnerable to particle contamination.
2.5 E 2I 09
1.5
[] chemox. [] HF errorbar:3*st.d.
cw'
"-
/~/i/,
,///// //,////
/////~
I
ID X 0
"///XA /////~
Y///;
0.5
i/////
YY/? 0
//////
650 / 0
650 / 10
oxidation condition:
800 / 30
Temp(°C) / time(min)
Figure 1. Ellipsometric oxide thickness and 3-a non-uniformity (= error bars) for three different oxidation conditions (10% 02 and 90% N2) in the case of chemical-oxide passivation and of hydrogen passiration of the initial silicon surface.
3. E F F E C T
OF CONTAMINATION
3.1. R e d i s t r i b u t i o n During thermal oxidation (or treatment) the initial surface contamination will be redistributed
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00370-6
200
P. Mertens et al. / Microelectronic Engineering 48 (1999) 199-206 gas phase transport (X-contamination)
initial surface
in oxide or
contamination
at interfaces
silicon bulk. In general the metals that diffuse more into the bulk yielded the largest carrier lifetime degradation.
diffusion into bulk
Figure 2. Schematic representation of the redistribution of metallic contamination that is initially present on the wafer surface upon thermal oxidation [4,5].
• 100% -g_
:
F I
I
I
x
o 80%
==
60%
"--i
oE_ E
a 40% in three different parts, as indicated in Fig. 2 [4,5]. The surface contamination can either diffuse into the bulk silicon, be incorporated into the oxide or be transported through the gas phase and eventually cause cross-contamination. Each of these three components of material transport have been studied with an appropriate method. The concentration in the oxide and at the interfaces can be measured with vapour phase decomposition - droplet collection (VPD-DC) [6] in combination with either total-reflectance X-ray fluorescence (TXRF) or AAS. The bulk concentration, in the case of Fe has been measured with the SPV method. The "longitudinal out-diffusion" of a box-shaped longitudinal contamination profile in the furnace (i.e. the cross-contamination) gives an indication of the gas phase transport [7]. In this section the redistribution of metallic contamination in the absence of C1 is treated. Fe is not volatilized during typical oxidation process. The redistribution of Fe upon oxidation is relatively complex as it changes significantly with changes in the oxidation process [4,8]. The more oxygen is present in the furnace ambient in an early stage of the heating cycle the smaller the fraction of Fe diffuses into the silicon. The Fe that diffuses in the wafer results in enhanced carrier recombination. More recent tests have been done with (1012 at./cm 2) metallic contamination applied prior to the growth of 4.5 nm gate oxide at 800°C in a dry ambient (Fig. 3) [9]. Only Pb, Na and Zn showed significant volatilization. In general metals with a strong tendency for oxide or silicate formation tend to be incorporated in the oxide. Metals with sufficiently high diffusion constant and solubility tend to diffuse in to the
E 20% 0%
Mg Ca Sr Ba Ti Fe V M n C r C o NI Pt P b N a Z n
Figure 3. Fraction of the total metal contamination (approximately 10i2 at./cm 2) that is incorporated into the oxide 4.5 nm oxide grown at 800°C in dry ambient or at one of its two interfaces [9].
3.2. E f f e c t o n p o l y - s i l i c o n
Metallic contaminants have also been reported to affect the growth of poly silicon [10]. In case of Fe contamination prior to gate oxidation, an increase of thickness and surface roughness of the poly silicon gate layer has been observed [4,8]. In more recent tests [9] with (1012 at./cm 2) metallic contamination applied prior to the growth of gate oxide, mentioned earlier, the light scattering haze on 450 nm polysilicon layers deposited on top of the oxides was measured using a Censor ANS100, as shown in Fig. 4. From all the elements under study only Cr contamination had a major effect on the poly-Si haze. 3.3. E f f e c t o n o x i d e i n t e g r i t y
In general, metallic contamination is expected to degrade device performance. Over the past years, it has been demonstrated that metallic contamination on the wafer surface prior to gate oxidation has a distinct negative effect on the dielectric integrity of thin gate oxides [11,12]. Particularly Ca has been identified as one of the most detrimental metals in that respect [11,12]. Also Fe contamination present on the wafer sur-
P. Mertens et al. / Microelectronic Engineering 48 (1999) 199-206 10
4
---",---,'------,'-'--7-'-- --7
~ i ---r--v---T--i-T--f-~
-!
-4..
7 10 3
--4
201
[12,14]. Metals are reported to act as catalyst for the SiO2 decomposition reaction during heat treatment in an ambient with a very low oxygen concentration [15]. Another mechanism for degradation could be the formation of stable silicates [14].
e-
//
10 2
i ref N a
i
i TI
4. I M E C C L E A N A N D F I N A L R I N S I N G
/
12 V
4.1. Imec clean
Cr Mn Co
Ni C u Z n S r R u B a
Pt Pb
Figure 4. Light scattering haze (Censor ANS100) measured on 450 nm LPCVD poly-silicon layers deposited on 4.5 nm oxide grown at 800°C in dry ambient on wafers that were metal contaminated with approximately 1012 at./cm 2 [9].
face prior to the gate oxidation has been correlated with gate oxide integrity (GOI) degradation [8,12,13]. GOI degradation obtained in case of Fe contamination has been found to depend on the silicon crystal growth process as well [13]. A recent evaluation, shown in Fig. 5, shows that the column II metals are most detrimental for gate oxide dielectric strength, followed by V and Co [9]. Metal contamination can also introduce fur-
1o' ,ODL
The RCA-recipe [1] has been commonly used to clean wafers. Today wet cleaning takes up a significant fraction of the production cost and generates large amounts of waste. A strong reduction in chemical and UP-water consumption can be obtained by using simplified cleaning schemes, such as the imec cleanTM [16,17]. A typical implementation is presented in table 1.
Table 1 Overview of different steps of a typical implementation of the imec cleanTM in an immersion tank system [16,17]. description temp. time (°C) (min) H2SO4/O3 90 5 3-fold quick-dump rinse 60, 20 8 dHF (0.5%) + dHC1 (0.5M) 22 2 rinse, reduced pH (+ 03) 20 10 Marangoni dry, reduced pH 20 8
103
10`
ux
t 1~ m ] 10-t 10"~
IMEC
HNOj .
V
C.r I ~
Co
NI
Zn RU PI Pb
-
MO Ca Sr I~
Figure 5. E b d defect density of 4.5 nm gate oxides at 11 MV/cm obtained from ramped voltage stress for different conditions of intentional metal contamination [9].
ther degradation during post oxidation anneals
In the first step the organic contamination is oxidized. In the same step a well controlled thin chemical oxides is obtained on the silicon surface by a self-limiting growth. From an environmental perspective it is desirable to perform this oxidation step using ozone - water mixtures [18], without sulphuric acid. In the latter case further savings in rinsing can be realized. The HF/HCl-mixture etches off the chemical oxide very selectively, thereby under cutting particles. This optimized mixture provides protection against noble metal outplating from the solution [19].
202
P. Mertens et al. / Microelectronic Engineering 48 (1999) 199-206
Then rinsing is performed at reduced pH in order to avoid redeposition of metallic contamination, as will be explained below (section 4.2). If allowed for the application, a reoxidation is performed during this rinsing step by injecting O3 in the rinsing solution. The hydrophilic surface thus obtained is less sensitive to particle contamination and allows for easier drying without the generation of water marks. As mentioned in section 2 the reoxidized surface is preferred for gate oxidation. During this reoxidation step, care must be taken to avoid gas bubble formation in this mixture, since bubbles introduce particle deposition. Drying is preferably performed using the Marangoni technique [20]. The pH of the water used during Marangoni drying is also reduced by spiking small amounts of acid. 4.2. final r i n s i n g
It has been recently reported that rinsing clean wafers in ultra pure water results in a built up of metallic surface contamination [21,22] on hydrophilic wafers, particularly of Ca [23-25]. Even after state of the art wet cleaning the surface concentration of Ca ranges typically from 1 x 10 l° to 5 X 1 0 1 0 a t . / c m 2 [23]. Fig. 6 shows the results of a first order model of a designed experiment in which the rinse water in the Marangoni drier was intentionally spiked with 2 w-ppb of Ca and varying amounts of HNO3 [23,26]. These final rinses were performed directly after immersion of clean wafers in either an SC1 or an SC2 mixture. It was found that the metal surface concentration drastically increases with decreasing HNO3 spiking. The higher concentration found on SCl-last cleaned wafers with respect to SC2-1ast cleaned wafers was attributed to the carry over of basic SC1 chemical into the final rinse and dry tank. Another set of designed experiments was performed. Also in these experiments higher [H+] results in lower metal surface concentration, a M The time dependence of deposition was negligible for most elements. Only Cr, Fe, and A1 surface concentrations showed time dependence at pH > 5 only. This time dependence is attributed to transport (typically diffusion) limited deposition [24].
1014
. . . .
i
.
.
.
.
i
.
.
.
.
upper limit imposed by diffusion transport :~0 mln
~t= 1013
/
6mi~~
1012
/
SC
d ¢.
i
a
.
.
.
. /
/ /
///
''
~e
SC2/
8 1011 ",1 ffl /
C~ 101°
/ ~
.~
-
"
J~xpear.en~lra.g~
10 9 3
4
5
6
7
qog([HN031 ! (rr~gl)) Figure 6. Dependence of the final Ca surface concentration (equilibrium values) as a function of pH of the final rinse solution and of the last cleaning step prior to the rinsing [23,26]. The rinse water was spiked with approximately 2 w-ppb of Ca.
A model for the adsorption of metallic ions onto hydrophilic surfaces resulting from wafer cleaning has been developed. The acid-base behavior of Si-OH groups act as weakly acidic ion exchangers [27-30]. The chemical oxide undergoes reactions with H + and other cations (e.g., metal ions), M +, in solution [25]: _= SiO-(s) + H+(aq) ~:~ SiOH(s)
(1)
- SiO-(s) + Mn+(aq) ~
(2)
SiOM(n-1)+(s)
KH and KM are the constants describing the attraction of H + and M n+ to the surface, respectively. It is assumed that multiple cationic species can adsorb to a limited number of surface sites with concentration, a0 [32]. Cations, M n+, attach singly to these surface sites. This results in the following surface concentration balance: O"0 = O'SiOM + O'SiOH + O'siO -
(3)
where o'SiOM is the surface concentration of the metal on the wafer surface. Combining the equilibrium expressions corresponding to reactions (1) and (2) with equation (3) yields the following expression for the metal surface concentration:
KM[M +] GSiOM
=
1 + KH[H+] + KM[M+]"aO
(4)
203
P. Mertens et al. I Microelectronic Engineering 48 (1999) 199-206 The values of KH, KM and a0 can then be obtained as fit parameters. Fig. 7 shows the agreement between experimental data [31] and the model of eq. (4) in a conventional deposition plot. This plot also shows why for the range of experimental conditions a sublinear relationship was obtained from the DOE-model. Fig. 8 illustrates the model given by eq. (4) for different p H values. These curves can be used to design an optimal rinsing process in terms of the level of acidification required and purity specification for the UPW. For example at p H 2 the CaZ+-weight concentration should be below 10 ppt in order to keep the Ca surface concentration below 5 x 109 at/cm 2. This model has also been expanded
1013 1012
~
........
I
........
i
........
i
........
i
. . . . . . . .
p
1011
~E 0
........ ,
........ ,
........ ~ ........ ,
.......
I adsorption site density
::
......................................
:
8 101° / 103
/
/
KH= 1.0 x 10
/
I/mol e
Kc== 1 . 2 5 x 1 0 I l m o l 107 ..,.C . . . . . . . . . . . . , ........ , . . . . . . . . . . . . . . . . . . . . . . . . . i0-12 10 "11 10"I0 I 0 "e 10 4 10 a
1 0 .6
[Ca z*] w-conc.
Figure 8. Ca-surface concentration as a function of [Ca 2+] weight-concentration for pH = 0 - 7 according to eq. (4).
strated to yield excellent results in a production line over an extended period of operation.
\ m e a s
~o 101° "E o
1012
........ ,
. . . . . .
__de nsi!y o f s!tes . . . . . . . .
d
to
i
1013
10 ~
5. C1 F O R T H I N O X I D E S i/
meas @pH5.6 KH= 103 I/mol
10 e
Kca= 1.25 x 10e I/mol
i i , , ,,..I . . . . . . . . i . . . . . . . . i 10 7 10 "11 10-1o 10 "12
........ L ........ i
10-o 10"e [Ca2÷]w-conc.
.....
10.7
10"e
Figure 7. Experimental results [31] and the model of eq. (4) for ac, as a function of [Ca2+] weightconcentration.
to describe more realistic situations with different metallic contaminants being present simultaneously [32]:
KM, [Mi+ ] GSIOM, = 1 + KH[H+] + KM, [Mi +] a0
(5)
This work contributes to the design of an optimal rinsing processes and helps to specify the required metallic purity of ultra pure water systems. This optimized rinsing has been implemented in the imec clean T M and has demon-
Historically Cl has been introduced in the oxidation ambient mainly in order to reduce the electronic instabilities attributed to the presence of mobile ions, mainly from Na but also to reduce of the density of dielectric breakdown defects [33,34] The beneficial effect on dielectric integrity of thin gate oxides is attributed to the removal of residual metallic contamination (Fig. 9), in particular Ca originating from the wet clean (see above) or from the quartz furnace walls in particular, [35]. In order to meet the stringent future gate-oxide defect density requirements, a well optimized (wet) cleaning process should be used in combination with the in situ use of a small amount of C1 during oxidation. Because of corrosion problems, associated with the direct use of HC1 [5,37] and C12, volatile organic chlorocarbon precursors such as 1,1,1-trichloroethane (TCA) C2HsCls, trans-l,2dichloroethylene (DCE) C2H2C12 and oxalyl chloride (OC) C2C1202 were introduced. The use of organic Cl-precursors becomes more difficult for the growth of ultra thin gate oxides with a thickness in the range of 2 to 6 nm. In order to obtain good thickness control, the oxi-
204
P. Mertens et al.
/
Microelectronic Engineering 48 (1999) 199-206 1000
o
0 .c::
250
"d 200
...:.:..
......
,
. . . . . . . . . . . . . . . .
100 TC~ ~ ' ~
150 ~' 100
10 rcO K
Ca
Ti
Fe
Ni
Cu
W
E
¢9
AI
Figure 9. The concentration of metals remaining at the surface or in the grown oxide was measured with VPD - DC - TXRF/GFAAS, directly after contamination as well as after growth of 8 nm oxide at 850°C in Cl-free O2 or O2 with DCE or OC at a CCl-eq. of 1% [36,35].
dation time cannot be too short. Therefore, usually the oxidation is performed at relatively low temperature (e.g. 650 to 800 °C) using an ambient consisting of 2 to 10 % 02 in an inert filler gas, such as N2. These processes could pose difficulties for the use of chlorocarbon precursors, namely incomplete combustion. Under such cases TCA and particularly DCE are known to result in soot formation. Moreover the combustion of those two precursors should preferably take place well above 700°C. The overall combustion chemistry equilibrium of TCA and DCE is very similar since for both molecules the number of hydrogen atoms equals the number of C1 atoms. Under oxidizing ambient, such as used in typical gate oxidation processes, TCA and DCE can be seen as direct precursors for HC1. Only a fraction of the HC1 is (further) oxidized to form C12 and H20, according to the equilibrium of the reaction [33]: HC1 + 02 ~-- C12 + H20
(6)
In case of OC, all C1 is transformed into C12 under oxidizing ambient [38]. C12 and not HC1 is believed the active species [35]. Therefore OC is preferred over TCA and DCE for ultra thin oxide growth as it will require less oxygen to generate a given concentration of C12 (see Fig. 10). A process has been demonstrated for growing oxides in the range of 3nm based on OC making use of a conventional oxidation furnace. Using OC at a C C ] - e q . of only 0.05 to 0.3 % yields the
HCI
1
OC
>~ 0 0.1 0,001
........
)
........
0.01
i
0.1
CI2-efficiency
Figure 10. The stoichiometric oxygen demand of the Cl-precursor reactions under consideration as a function of the fraction of the number of C1 atoms transformed into el2 over the total number of C1 atoms in the system [35].
same performance as with 3 % C C l _ e q "
HC1 (Table
2). 6. C O N C L U S I O N S A chemical oxide passivated initial surface is preferred because of its higher stability, more robust particle performance and good thickness control for the growth of ultra thin oxides. Column II metals were found to be most detrimental with respect to the dielectric quality of the gate oxide. Also in case of contamination with Fe, V or Co significant degradation was observed. The imec clean results in very good cleaning performance at low chemical and water consumption. The deposition of metals such as Ca on hydrophilic wafer surfaces, during the final rinse can be suppressed by spiking minute amounts of acid into the rinse water. For growth of ultra thin gate oxides or for in situ C1 anneal, the process is performed with reduced oxygen concentration and at reduced temperature, severely limiting the use of common organic Cl-containing precursor such as TCA or DCE. It is demonstrated that under such circumstances the use of small amounts of oxalyl chloride results in successful removal of metallic contamination.
P. Mertens et al. I Microelectronic Engineering 48 (1999) 199-206
205
Table 2 Overview of experimental conditions and results of the 30 min 650°C furnace processes [35]. The experimental conditions include the Cl-source gas, the O2 concentration the Cl-eq. concentration of the Cl-source and the O/C1 ratio. The measured responses are: the thickness of the grown thermal oxide, the average haze lightscattering-fraction, the total amount of carbon present in the thin oxide layer and the reduction of the Ca and Fe surface concentration. source O2 CCl-eq. fox haze C incorp. Ca Fc reduc, reduc. (%) (%) (nm) (ppm) (10 x3 at./c m2) (%) (%) 2 0 1.5 0.067 0.016 < 14 < 21 2 0 1.86 0.066 1.3 0 < 23 HC1 2 3 1.7 0.067 0.075 85 49 HC1 2 3 2.1 0.066 0.24 > 98 61 OC 2 0.3 3.6 0.080 2 > 98 5/ OC 2 0.05 2.3 0.067 0.2 > 98 55
REFERENCES 1. W. Kern, D. Puotinen, RCA Review 31, 18%206 (1970). 2. The National Technology Roadmap for Semiconductors, (Semiconductor Industry Association, San Jose, 1994), p. 113, 116. 3. M. Depas, T. Nigam, K, Kenis, M.M. Heyns, H. Sprey and R. Wilhelm, in Proceedings of the Third International Symposium on Ultra-Clean Processing of Silicon Surfaces (Acco, Leuven, 1996), p. 291. 4. P.W. Mertens, A.L.P. Rotondaro, M. Meuris, H.F. Schmidt, M.M. Heyns and D. Gr~f, in Institute of Environmental Science 40~h Annual Technical Meeting 1994 Proceedings Vol. 1 (IES, Mount Prospect, Illinois, 1994), p. 325. 5. P.W. Mertens, T.Q. Hurd, D. Gr~f, M. Meuris, H.F. Schmidt, M.M. Heyns, L. Kwakman, M. Hendriks and M. Kubota, in Proceedings of the Symposium on Contamination Control and Defect Reduction in Semiconductor Manufacturing III (The Electrochemical Society, Pennington, NJ), 9 4 - 9 , p . 241. 6. SEMI Doc. 2468: Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF) (Semiconductor Equipment and Materials International, Mountain View, CA, 1997). 7. P.W. Mertens, M. Meuris, H.F. Schmidt, S. Verhaverbeke, M.M. Heyns, P. Carr, D. Gr~f, A. Schnegg, M. Kubota, K. Dillenbeck and R. de Blank in Crystalline Defects and Contamination:
Their Impact and Control in Device Manufacturing, ECS-Proc. Vol. 93-15 (The Electrochemical Society, Pennington, NJ, 1993), p. 87. 8. P.W. Mertens, S. De Gendt, M. Depas, K. Kenis, A. Opdebeeck, P. Snee, D. Grail, G. Brown and M.M. Heyns, in same as [3], p. 33. 9. T. Bearda, S. de Gendt, L. Loewenstein, M. Knotter, P. Mertens and M. Heyns, in Proceedings of the Fourth International Symposium on UltraClean Processing of Silicon Surfaces (Scitec Publications Ltd, Zuerich-Uetikon, Switzerland, 1999), p. 11. 10. W.A. Syverson and P.J. Schubring, in Proceedings of the Second International Symposium on Cleaning Technology in Semiconductor Device Manufacturing, 180 th Electrochemical Society Meeting, PV 92-12, (The Electrochemical Society, Pennington, NJ, 1992), p. 204. 11. P.W. Mertens, M. Meuris, S. Verhaverbeke, M.M. Heyns, A. Schnegg, D. Gr~f and A. Philipossian, in IES 38th Annual Technical Meeting 1992 Proceedings Vol. 1, (IES, Mount Prospect, Illinois, 1992), p. 475. 12. M. Takiyama, S. Ohtsuka, S. Hayashi and M. Tachimori, in Proc. of 1ff h Workshop on ULSI Ultra Clean Technology; Advanced Silicon Wafer Qualities for ULSI, (Ultra Clean Sot., 1992), p. 96. 13. P.W. Mertens, M. Meuris, H.F. Schmidt, S. Verhaverbeke, M.M. Heyns, D. Gr~, A. Schnegg, M. Kubota, K. Dillenbeck and A. Philipossian, in IES 39th Annual Technical Meeting 1993 Proceedings Vol. 1, (IES, Mount Prospect, Illinois, 1993), p. 231.
206
1). Mertens et al. / Microelectronic Engineering 48 (1999) 199-206
14. M. Takiyama, S. Ohtsuka, S. Hayashi and M. Tachimori, in Proceedings of the Third International Symposium on Silicon Materials Science and Technology, 185th Electrochemical Society Meeting, P V 94-10, (The Electrochemical Society, Pennington, NJ, 1994), p. 346. 15. M. Kobayashi, Y. Ogawa and K. Wada, Extended Abstracts of the Electrochemical Society Spring Meeting 1985 Vol. 85-1 (The Electrochemical Society, Penning~on, N J, 19985), p. 94; M. Liehr, H. Dallaporta and J.E. Lewis, Appl. Phys. Lett. 53, 7 (1988). 16. M. Meuris, P.W. Mertens, A. Opdebeeck, H.F. Schmidt, M. Depas, G. Vereecke, M.M. Heyns and A. Philipossian, Solid State Technology, July 1995, p. 109. 17. M. Meuris et al. in 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (IEEE, Piscataway, N J, 1999) to be published. 18. S. De Gendt, P. Snee, I. Cornelissen, M. Lux, R. Vos, P.W. Mertens, D.M. Knotter and M.M. Heyns, 1998 Symposium on VLSI Technology Digest of Technical Papers, 168 (1998). 19. W. Krusell et al, Electrochemical Society Meeting, P V 90-9 (The Electrochemical Society, Pennington, N J, 1990); I. Teerlinck, P.W. Mertens, R.. Vos, M. Meuris and M.M. Heyns, in same as [3], p. 21. 20. A.F.M. Leenaars, J.A.M. Huethorst and J.J. van Oekel, Langmuir 6, 1701 (1990). 21. I. Lampert and L. Fabry, German patent DE 42 09 865 C2 (30 June 94). 22. L. Fabry, S. Pahlke, L. Kotz, P. Blfchl, T. Ehmann and K. B~ichmann, in same as [3], p. 163. 23. L.M. Loewenstein and P.W. Mertens in Proceedings of the Fifth International Symposium on Cleaning Technology in Semiconductor Device Manufacturing, 192nd Electrochemical Society Meeting, P V 97-35, (The Electrochemical Society, Pennington, N J, 1998) p. 89. 24. P.W. Mertens, L.M. Loewenstein, R. Vos, S. De Gendt, T. Bearcla and M.M. Heyns, in Proceedings of the Eighth International Symposium on Silicon Materials Science and Technology, 193rd Electrochemical Society Meeting, P V 98-1 Vol. 1 (The Electrochemical Society, Pennington, N J, 1998), p. 592. 25. L.M. Loewenstein and P.W. Mertens, J. Electrochem. Soc. 145, 2841 (1998). 26. P.W. Mextens, T. Bearda, L.M. Loewenstein,
A.R. Martin, W. Hub, B.O. Kolbesen, I. Teerlinck, R. Vos, M. Baeyens, S. De Gendt, K. Kenis and M.M. Heyns, in Proceedings of the Third International Symposium on defects in Silicon, 195th Electrochemical Society Meeting, P V 991 (The Electrochemical Society, Pennington, NJ, 1999), p. 401. 27. M. Grundner and H. Jacob, Appl. Phys. A39, 73 (1986). 28. T.Q. Hurd, H.F. Schmidt, A.L.P. Rotondaro, P.W. Mertens, L.H. Hall and M.M. Heyns, in Proceedings of the Fourth International Symposium on Cleaning Technology in Semiconductor Device Manufacturing, 188th Electrochemical Society Meeting, P V 95-20, (The Electrochemical Society, Pennington, N J, 1996), p. 277. 29. R.K. Iler, The Chemistry of Silica: Solubility Polymerization, Colloid and Surface Properties, and Biochemistry, (Wiley, New York, 1979), p. 180-189 and 663-676. 30. B.A. Krishna and J.R. Regalbuto, J. Colloid and Interf. Science 185, 174 (1997). 31. A. Misra, B. Schmidt, L. Hall, J. Sees and T. Hurd, Semiconductor Fabtech, Winter 1998/1999, 9th ed. p. 173 (1999). 32. L.M. Loewenstein, F. Charpin and P.W. Mertens, J. Electrochem. Soc. 148, 719 (1999). 33. R.E. Tressler, J. Stach and D.M. Metz, J. Electrochem. Soc. 19.4, 607 (1977). 34. J. Monkowski, Solid State Technology July 1979, p. 58; and refs in Ref. [35]. 35. P.W. Mertens, M.J. McGeary, M. Schaekers, H. Sprey, B. Vermeire, M. Depas, M. Meuris and M.M. Heyns; in Mater. Res. Soc. Proc. (Mater. Res. Soc., Pittsburgh, PA, 1997) Vol. 473, p. 149; or in Vol. 477 , p. 89. 36. B. Vermeire, P.W. Mertens, M.J. McGeary, K. Kenis, M.M. Heyns, M. Schaekers and A. Lubbers, in Proceedings of the Second International Symposium on Ultra-Clean Processing of Silicon Surfaces (Acco, Leuven, 1994), p. 143. 37. G. Vereecke, N. Anderson, C. Elsmore, P. Espitalier-Noel and M.M. I-Ieyns, in same as [3], p. 69. 38. M.J. McGeary, P.W. Mertens, B. Vermeire, M. I-Ieyns, H. Sprey, A. Lubbers and M. Schaekers, in Mater. Res. Soc. Proc. (Mater. Res. Soc., Pittsburgh, PA, 1997) Vol. 447, p. 115.
