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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 4, NOVEMBER 2003

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Modeling and Design for Electrical Performance of Wideband Flip-Chip Transition Chun-Long Wang and Ruey-Beei Wu, Senior Member, IEEE

Abstract—A locally matching technique is proposed in this paper to improve the wideband performance of the flip-chip transition. The gap width of the coplanar waveguide (CPW) line in the bump pad region of both the chip and board is enlarged for achieving larger inductance to compensate the capacitance at the transition, making the approximate impedance close to 50 . An equivalent circuit is derived from the frequency response of the transition simulated by Sonnet and is used to control the zero frequency of the structure. With a properly chosen value of the enlarged width, the zero frequency can be controlled to achieve an optimal transition performance over an as wide as possible bandwidth. A systematic design procedure is established and employed to design a transition over a band from dc to 60 GHz. The design and simulation results are also compared with the measured data of a scaled structure as well as a realization of an optimized flip-chip transition design ranging from dc to Ka band. The measured data show a good agreement with the simulation results, if under a careful calibration procedure. Both demonstrate that the present transition design can achieve better than 25 dB in return loss and 0.2 dB in insertion loss over dc to 35 GHz.



Index Terms—Coplanar waveguide, flip-chip transition, locally matching.

I. INTRODUCTION

F

LIP-CHIP transition has become a promising technique over bond-wire in the microwave and millimeter wave frequency, due to its features of short and stable electrical interconnection, low cost, and high reliability. As frequency goes higher, the parasitic effects of the flip-chip transition may result in performance degradation. This should be considered carefully in order to achieve good transitions from dc to millimeter wave spectrum. For flip-chips of typical dimensions, the frequency response has been examined to yield an accurate equivalent circuit model, which shows an overall capacitive property [1]. It was thus suggested that the bump pad be kept as short as possible to lessen the capacitance at initial design [2], [3]. This usually causes great concern in the fabrication. Another approach was a staggered design [4] or a dual bump design [5] in the central line of coplanar waveguide (CPW). The return loss was improved, but with the increase in the chip areas as trade off.

Manuscript received February 2, 2003; revised August 30, 2003. This work was supported in part under Grant 89-E-FA06-2 from the Ministry of Education and Grant NSC 90-2219-E002-005 from the National Science Council, Taiwan, R.O.C. The authors are with the Department of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, 106 R.O.C. Digital Object Identifier 10.1109/TADVP.2003.821086

Recently, some investigators suggested a high impedance line or matching circuits on the board to compensate the excessive capacitance of the transition [6]–[9]. These techniques are satisfactory to optimize the transition over certain frequency band, but difficult to cover a wide band from dc to millimeter wave spectrums. One way to enhance the transition bandwidth is to miniaturize the size of the compensation or the matching circuits. Based on this concept, a locally matching technique is proposed in this paper by designing the transition transversely rather than longitudinally [10], [11]. Both the simulation and measurement are performed and compared to validate the design concept. II. COMPENSATION ON BOARD ONLY A. Hi-Impedance Compensation Consider the structure of a traditional flip-chip transition shown in Fig. 1(a). Fig. 1(b) shows its top view together with the equivalent circuit which resembles a low pass filter of . The element values can be determined from order the comparison with the frequency response of the transition simulated by Sonnet. It is found that the series resistance and shunt conductance are small and can be neglected. Consider a typical flip-chip structure with the geometric dimensions given in Fig. 1. The series inductance is found to be 68.67 pH and the shunt capacitance is 34.91 fF extracted by the least squares method [12]. Since the effective bump impedance is much smaller than the system characteristic impedance , the transition shows an overall capacitive property. The effective excess capacitance can be roughly given by [8] (1) With the dimensions mentioned above, the value of the tradi. tional flip-chip is calculated to be To compensate the capacitive effect of the traditional flip-chip transition, a high impedance transmission line, which exhibits an inductive effect, is adopted [7]–[9]. The top view of the hi-impedance compensation as shown on the left side of Fig. 2 is constructed by adding a high impedance transmission line on the board in front of the transition. By neglecting the effect of the step discontinuity, its equivalent circuit is shown denotes the on the right side of the same figure where the capacitance per unit inductance per unit length, length, and the length of the high impedance transmission line. The idea of this compensation technique is to make the overall effect of the high impedance transmission line and the

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Fig. 2. Upper view and its equivalent circuit of hi-compensation structure. W = 30 m, S = 155 m, l = 185 m.

Fig. 1. Structure of the traditional flip-chip transition: (a) 3-D view and (b) upper view and its equivalent circuit. W = W = 200 m, S = S = 70 m, G = G = 600 m, H = H = H = 127 m, D = 160 m, L = 200 m, " = 10:2.

matched to a system impedance of 50 . The relation can be given by (2) With some manipulation, (2) can be rewritten as (3) is the characteristic impedance of the high impedance Here, the propagation constant, and the optransmission line, erating frequency. , which is dependent on the cross secGiven the value of tion dimensions of the high impedance transmission line and usually subject to the constraints of the fabrication, the length of the high impedance transmission line can be determined via (3). One thing worth mentioning is that matching at which freis of less concern because the CPW structure has quency low dispersion. For the example in Fig. 2, the high impedance . The value transmission line is designed to have is calculated to be 15.048 at for this of section of high impedance transmission line. Fig. 3 compares the calculated results of return loss (RL) for the traditional flip-chip transition by a commercial field solver Sonnet and those by the equivalent circuit in Fig. 1(b). The

Fig. 3. Return loss versus frequency of the traditional flip-chip transition and hi-impedance compensation structures.

agreement verifies the correctness of such an equivalent circuit over dc to 60 GHz. The comparison results for the transition with hi-impedance compensation are also shown in this figure. Good agreement between the simulation results by Sonnet and the simple equivalent circuit model in Fig. 2 justifies that the effect of the step discontinuity is not severe. It is also noted that the return loss is improved at low frequency band only. The improvement by the high impedance transmission line deteriorates at higher frequencies. For the present example, the effect , for which the of the compensation reverses at is 17.556 corresponding to a length . value of From an equivalent circuit point of view, the addition of the high impedance line contributes a large series inductance to form a , which has better low frequency low pass filter with order characteristics but degrades the high frequency performance. In addition, the overall effect of the high impedance line is no more a lumped inductance when its length reaches one-twentieth of a guided wavelength at high frequencies. B. Increasing the Gap Width on Board An alternative to improve the transition is to reduce the shunt or so as to make the associated impedance capacitance close to 50 . Subject to the constraints of the wiring rule in the fabrication process that the length and aspect ratio of bump is maintained, the idea can be

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WANG AND WU: MODELING AND DESIGN FOR ELECTRICAL PERFORMANCE OF WIDEBAND FLIP-CHIP TRANSITION

Fig. 4. Return loss versus frequency for the structure with the ground retreat on the board as a parameter.

implemented by increasing the distance between the center and ground planes on the board at the discontinuity and thus the distance between the center and ground bumps on both sides. The reason for enforcing a lateral ground retreat on both sides is to avoid the excitation of the odd mode of the CPW. As shown in the inset of Fig. 4, this implies an increase in the series inand reduction in the shunt capacitance on the ductance board side. Fig. 4 shows the simulation results of return loss with the increase in the gap width on the board as a parameter. It can be seen that the return loss is improved by choosing a larger . Furthermore, it deserves mentioning that the improvement covers a wide frequency band since the overall size of the transition remains much smaller than a wavelength even at 60 GHz. and the shunt capaciThe values of the series inductance are extracted to verify the design idea mentioned tance above and are shown in Fig. 5. From this figure, it can be seen increases versus , and reduces as expected. It is that is worthy of note that the value of the shunt capacitance hardly disturbed and consequently the compensation is not com, the effective bump plete. Even with a very large of 200 is still smaller than the desired value of impedance 50 and exhibits overall capacitive properties. III. COMPENSATION ON BOTH SIDES It will be more effective to employ the idea of locally matching on both the board and chip sides. As is shown in the inset of Fig. 6, both the ground conductors on the board and chip are retreated by a distance . The frequency response of return loss is simulated by Sonnet with ground retreat as a parameter. By properly choosing the parameter, say , the return loss can be greatly improved over a wide band covering dc up to 60 GHz or more. The design is satisfactory and simple, but with some areas occupied in the transverse direction of the chip as trade off. The equivalent circuit of the locally matching structure can be well represented as Fig. 1(b), in which the effect of the step discontinuity has been well accounted for since the size of the

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Fig. 5. Extracted series inductance L and shunt capacitance C , C versus the ground retreat for the structure in Fig. 4.

1

Fig. 6. Return loss versus frequency for the structure of the locally matching structure with ground retreat on both the chip and board sides as a parameter.

1

discontinuity is smaller than one-twentieth of the guided wavelength. Although not shown here, the return loss of the equivalent circuit versus frequency has been simulated and found to be in excellent agreement with those in Fig. 6. Fig. 7 shows the and shunt capacitance extracted series inductance versus the ground retreat . As increases, the capacitance decreases as expected while the inductance increases. Comparand a ison with those in Fig. 5 reveals a further increase in . Actually, has a more significant significant reduction in influence on the series inductance than on the shunt capacitance. , this represents a two-fold inAs increases from 0 to 200 and only a 30% decrease in . crease in It is interesting to note the occurrence of the dip in the return in Fig. 6. Similar loss versus the frequency for , situation happens for the case with smaller , say . The but disappears if becomes too large, say zero frequency, which corresponds to the dip of return loss, can

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(a)

Fig. 7. Extracted series inductance L and shunt capacitance C ground retreat for the structure in Fig. 6.

1

versus the

(b) Fig. 9. (a) Photograph of a 10Xs scaled up back-to-back transition and (b) the simulated and measured return loss and insertion loss versus frequency.

Fig. 8. Zero frequency and level of return loss versus the reduced width the structure in Fig. 6.

1 for

be derived from the equivalent circuit of Fig. 1(b). There are two and the other is solutions, one is (4) is shown in Fig. 8. It is Its value versus the ground retreat now evident that the value by (4) may not be real for larger , , because the effective bump impedance say is larger than 50 . Also shown in this figure is the level of return loss, which is defined as the worst return loss over dc for a given value of in Fig. 6. Based on this figure, to the ground retreat can be chosen properly to determine the for the best transition performance over zero frequency the desired bandwidth. For experimental verification, two single locally matching structures are fabricated using PCB with ten times scale up in all the geometric dimensions. They are connected back to back for measurement as shown in Fig. 9(a). The separation between

the two single transitions is 22 mm, which will exhibit an additive multiple reflections at about 3.16 GHz. The circuit is fabricated on the board of RT/Duroid 6010 and bump is formed with copper. The measurements are done on the Vector Network Analyzer HP8510C with the TRL calibration. Fig. 9(b) shows the frequency response of the back-to-back transitions obtained by the simulation and measurement under ten times model. Good agreements between simulation and measurement can be seen from the figure except for a small shift in the resonance frequency. This may be contributed to the abrupt cut of the dielectric of the chip near the discontinuity or the misalignment of solder bumps in fabrication. The measured insertion loss shows the same tendency as the simulation result, with the slight discrepancy owing to the negligence in the conductor and dielectric loss. IV. REALIZATION AND VERIFICATION UP TO KA-BAND For the purpose of realization and high frequency verification, two kinds of transition structures, one with ground retreat on the board side and the other with ground retreat on both sides, are back to back designed and fabricated. The structures of the

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WANG AND WU: MODELING AND DESIGN FOR ELECTRICAL PERFORMANCE OF WIDEBAND FLIP-CHIP TRANSITION

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(a) Fig. 11. Measured frequency response based on 50 transmission line system for the transition design with ground retreat on the board.

layout. For simplicity, the transition is designed and simulated with conductors of zero thickness. In order to achieve the charwhen fabricating with the acteristic impedance of , the impedance of the transmisconductor thickness of 5 when sion lines should be purposely chosen as simulating the structure with zero conductor thickness. As a result, the flip-chip transitions, which are back to back connected, should be simulated under the system impedance of 52 . The results are comparable to those measured under the system impedance of 50 . A. Increasing the Gap Width on Board (b) Fig. 10. Test structure with four back-to-back flip-chip transitions: (a) the photograph of the structure and (b) its associated TRL layout.

single transitions for the two kinds of transitions are similar but with some differences in the transition region as shown in the insets of Figs. 4 and 6. The transmission line on the board is substrate a grounded coplanar waveguide (GCPW) in and relative dielectric conwith thickness . On the chip is a conventional CPW in GaAs stant and relative dielectric constant with thickness . The dummy CPW runs a length of 700 to the bump pad area, which corresponds to an additive multiple reflections at 82.35 GHz. The bumps have the dimensions of diand height . All the conducameter substrate, GaAs chip, and bumps are made of tors on the gold. Fig. 10(a) shows the photograph of a typical test structure, which includes four back-to back flip-chip transitions. It deserves special design consideration for the transmission substrate and GaAs chip. In fabrication, lines on the the conductor is of several microns thickness, but the simulation software could not accurately account for the effect of the conductor thickness. Even if it could, the large computation time and memory become prohibitive. Another disadvantage is that the computation result may be erroneous because the conductor thickness is too thin with respective to the plain

, the Based on the characteristic impedance of , the slot , and the ground widths of the center conductor are 100, 50, and 200 , respectively, for the GCPW plane substrate. The ground retreat on the board is 50 . on , the slot , and Also, the widths of the center conductor on the GaAs chip are 100, 50, and 200 , the ground plane respectively. Three different chips are fabricated and measured to check for the repeatability and congruence. Measurements are done on the wafer calibrated with the TRL calibration under the characteristic impedance of 50 , which is predicted from the simulation when considering the conductor thickness. The TRL calibration kit is shown in Fig. 10(b). Measured data for the frequency response from dc up to 40 GHz of the three chips are shown in Fig. 11 and compared with the prediction from the simulation. The simulation and measurement data show noticeable dips near 39 GHz but have 4 5 dB difference in the return loss. The difference may occur from the measurement when doing the TRL calibration under the erroneous characteristic impedance. In order to obtain the correct characteristic impedance of the feedline, the probes calibrated with the standard SOLT (Short Open Load Through) procedure are used to measure the response of the through line of the TRL layout and the results are shown in Fig. 12(a). An ideal transmission line with the length and effective dielectric constant of 5.87, which is obof 800 tained from Sonnet, is used to match the measured data as shown in Fig. 12(b). The best-fit characteristic impedance is estimated

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(a)

Fig. 13. Measured frequency response based on 54 transmission line system for the transition design with ground retreat on the board.

(b) Fig. 12. (a) Measured and simulated responses of the through line in TRL layout and (b) the ideal transmission line model to determine the best-fit characteristic impedance for the through line.

to be , which yields the dash line in Fig. 12(a) as simulated by the commercial software Microwave Office. Hence, the measurement is calibrated with the TRL calibration under the characteristic impedance of 54 . The measurement and the simulation results now are in good agreements as shown in Fig. 13. In general, the measurement shows better than 15 dB in return loss and 0.5 dB in insertion loss from dc to 35 GHz.

(a)

B. Compensation on Both Sides This design has been focused to achieve the best transition performance over the frequency range from dc to 32 GHz required in the local multipoint distribution system (LMDS). Here, the lateral dimension of the ground plane is increased for the reason of further ground retreating. Based on the , the widths , , characteristic impedance of are now 100, 55, and 295 , respectively, for the and substrate. On the other hand, the widths , GCPW on , and for the CPW GaAs chip are 100, 80, and 270 , respectively. The ground retreats on the board and chip are , respectively. 75 and 50 Once again, the measurement is done with the TRL calibration under the characteristic impedance of 50 as shown in Fig. 14(a). It can be seen that the difference between the simulation and measurement results is 10 dB, which is more severe than the above case, because the return loss level is higher. On the other hand, Fig. 14(b) shows the measured frequency response, which is calibrated under the characteristic impedance . From the figure, it can be seen that the return loss of of the simulation and measurement data match well at low frequency but show a larger difference near the dips. For the desired

(b) Fig. 14. Measured frequency response for the transition design with ground retreat on both sides based on: (a) 50 and (b) 54 transmission line systems.

frequency range from dc to Ka band, the measured data show the same tendency with the simulation results. Both the simulation and measurement demonstrate that the present transition designed by locally matching can achieve better than 25 dB in return loss and 0.2 dB in insertion loss over dc to 35 GHz. It

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WANG AND WU: MODELING AND DESIGN FOR ELECTRICAL PERFORMANCE OF WIDEBAND FLIP-CHIP TRANSITION

deserves mentioning that this optimization can be applied to a wider bandwidth, but with deteriorated level in return loss as tradeoff. V. CONCLUSION The hi-compensation structure can improve the performance of the flip-chip transition only in a limited frequency range due to its comparatively large size in the longitudinal direction. The locally matching technique with ground retreat on board can have similar improvements in return loss over a wider frequency range due to its much smaller size. However, its effectiveness may be restricted by the significant excess capacitance due to the discontinuity on the chip side. The idea of locally matching is also extended to both the board and chip sides in this paper. By properly choosing a suitable ground retreat to control the zero frequency, the flip-chip transition can be designed to achieve an optimal performance over a wide frequency band of interest with some occupied area on the transverse direction of the chip as trade off. The design idea has been strongly supported by not only the simulation results but also the measurement data in a scaled structure and a realization of an optimal transition over dc to Ka band. One thing worth mentioning is that the correct is required in order to have an value of feedline impedance accurate calibration of the measurement data. This value can be suitably deduced from the measurement data of the trough line in TRL layout after a simple best-fit procedure. If the impedance is carelessly chosen in the measurement, there would be 4 5 dB difference between the measurement and simulation for the case with ground retreat on the board and 10 dB difference for the one with retreats on both sides. ACKNOWLEDGMENT The authors would like to thank S.-C. Yen and S.-J. Yang, for their help on the circuit board fabrication, W.-H. Tu, for the suggestions in measurements, the Staff of Airwave Inc., for the flip-chip fabrication, and K.-Y. Lin and P.-Y. Chen, for doing the on-wafer measurement. REFERENCES [1] H. H. M. Ghouz and E. El-Aharawy, “An accurate equivalent circuit model of flip chip and via interconnects,” IEEE Trans. Microwave Theory Tech., vol. 44, pp. 2543–2554, Dec. 1996. [2] M. Szymanowski and S. Safavi-Naeini, “Characterization of a flip-chip interconnect at frequencies up to 30 GHz,” in Proc. Canadian Conf. Elect. Comp. Eng., vol. 2, 2000, pp. 784–787. [3] D. Staiculescu, J. Laskar, and E. M. Tentzeris, “Design rule development for microwave flip-chip applications,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 1476–1481, Sept. 2000. [4] H. H. M. Ghouz and E. El-Aharawy, “Finite-difference time-domain analysis of flip-chip interconnects with staggered bumps,” IEEE Trans. Microwave Theory Tech., vol. 44, pp. 960–963, June 1996. [5] C. L. Wang, C. T. Hwang, R. B. Wu, and C. H. Chen, “A resonant flip-chip design with controllable transition band,” in Proc. IEEE MTTSymp. Dig., 1999, pp. 1342–1345.

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[6] N. Iwasaki, F. Ishitsuka, and K. Kato, “High performance flip-chip technique for wide-band modules,” in Proc. IEEE 5th Topical Meeting Elect. Performance Electron. Packag., 1996, pp. 207–209. [7] W. Heinrich, A. Jentzsch, and G. Baumann, “Millimeterwave characteristics of flip-chip interconnects for multi-chip modules,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 2264–2268, Dec. 1998. [8] W. Heinrich and A. Jentzsch, “Optimization of flip-chip interconnects for millimeter-wave frequencies,” in Proc. IEEE MTT-Symp. Dig., 1999, pp. 637–640. [9] A. Jentzsch and W. Heinrich, “Theory and measurement of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 871–877, May 2001. [10] C. L. Wang and R. B. Wu, “Locally matching design for flip-chip transition,” in Proc. Asia-Pacific Microwave Conf., 2001, pp. 547–549. , “A locally matching technique for broadband flip-chip transition [11] design,” in Proc. IEEE MTT-Symp. Dig., 2002, pp. 1397–1400. [12] B. Noble and J. W. Daniel, Applied Linear Algebra. Englewood Cliffs, NJ: Prentice-Hall, 1988.

Chun-Long Wang was born in Taichung, Taiwan, R.O.C., in 1972. He received the B.S. and M.S. degrees in communication engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1995 and 1997, respectively, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, in 2003. His areas of interest include flip-chip transitions, filter designs, and planar circuit to waveguide transitions.

Ruey-Beei Wu (M’91–SM’97) was born in Tainan, Taiwan, R.O.C., on October 27, 1957. He received the B.S.E.E. and Ph.D. degrees from National Taiwan University, Taipei, in 1979 and 1985, respectively. In 1982, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, where he is currently a Professor. He is also with the Graduate Institute of Communications Engineering established in 1997. From March 1986 to February 1987, he was a Visiting Scholar at IBM, East Fishkill, NY. From August 1994 to July 1995, he was with the Electrical Engineering Department, University of California at Los Angeles. From May 1998 to April 2000, he was appointed Director of the National Center for High-Performance Networking and Computing. Since November 2002, he has also been working for the government as Director of the Planning and Evaluation Division, National Science Council. His areas of interest include computational electromagnetics, transmission line and waveguide discontinuities, microwave and millimeter wave planar circuits, and interconnection modeling for computer packaging. He has authored or co-authored more than 130 papers on international journals or conferences. Dr. Wu received the Youth of Scientific Talent Award by National Culture Renaissance Association in 1975, the Distinguished Research Awards by National Science Council in 1990, 1993, 1995, and 1997, the Outstanding Young Scientist Fellowship by URSI in 1990, the Outstanding Young Engineer Award by Chinese Institute of Engineers in 1992, and the Outstanding Electrical Engineering Professor Award by Chinese Institute of Electrical Engineers in 1999. He is a member the Phi Tau Phi, the Chinese Institute of Engineers, the Chinese Institute of Electrical Engineers, and the International Union of Radio Science (URSI). He was an Associate Editor of the Journal of Chinese Institute of Electrical Engineering in 1996 and has been a member of the Editorial boards of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES since 1992.

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