AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect ...

AlGaN / GaN metal-oxide-semiconductor heterostructure field-effect transistors using barium strontium titanate P. J. Hansen,a) L. Shen,b) Y. Wu,a) A. Stonas,b) Y. Terao,a) S. Heikman,b) D. Buttari,b) T. R. Taylor,a) S. P. DenBaars,a),b) U. K. Mishra,b) R. A. York,b) and J. S. Specka) College of Engineering, University of California, Santa Barbara, California 93106

(Received 6 May 2004; accepted 9 August 2004; published 13 October 2004) Use of high-k gate dielectrics in AlGaN / GaN heterostructure field-effect transistors (HFETs) may reduce gate leakage and improve device reliability without adversely impacting transconductance and pinchoff voltage. To achieve this, AlGaN / GaN metal-oxide-semiconductor heterostructure field-effect transistors have been formed by incorporating barium strontium titanate (BST) deposited by rf magnetron sputtering as the gate dielectric. The maximum current achieved was slightly lower than realized in standard devices without BST, while the gate leakage of the devices was reduced by ⬃5 orders of magnitude compared to a conventional HFET for the as-deposited devices and 4 orders of magnitude for films annealed in N2. The transconductance and pinchoff voltage were found to vary with different dielectric constants of the BST films, being reduced by ⬃25% for a 40 nm film with a dielectric constant of 20, and by 14% upon annealing in N2 (dielectric constant ⬃66) when compared to a baseline device with no oxide. It was found that the BST deposition temperature greatly affected mobility in the AlGaN / GaN structure, with higher temperatures significantly reducing the HFET mobility. © 2004 American Vacuum Society. [DOI: 10.1116/1.1800352]

I. INTRODUCTION GaN-based transistors are promising for future generation microwave power electronics. Field-effect transistors (FETs) will require low gate leakage both for low noise and reliability. Incorporation of an insulator into GaN-based transistors to make metal-oxide-semiconductor field-effect transistors or metal-insulator field-effect transistors (MISFETs) results in reduced gate leakage and increased device reliability compared to metal-semiconductor field-effect transistors with a Schottky gate. To achieve these metal-insulator or metaloxide-semiconductor structures, there have recently been studies of various insulators on GaN, including SiO2,1–8 Si3N4,3,8,9 AlN,9–12 Ga2O3共Gd2O3兲,11,13–15 Ta2O5,16 thermally grown Ga2O3,17 SiO2 / Si3N4 / SiO2,18 and Sc2O3.15 These works have investigated the insulator/GaN interface through fabrication of MIS structures and have shown improved device performance by incorporating the insulators into MISFETs. A SiO2 layer under the gate has been shown to reduce gate leakage current in AlGaN / GaN heterostructure field-effect transistors (HFETs) by six orders of magnitude compared to that of a conventional HFET.4,5 Ideally the gate leakage current should be suppressed without affecting the transconductance gm or pinchoff voltage V p of the device. The disadvantage of using SiO2 as a gate insulator is its low dielectric constant of 3.9. This low k results in a substantial increase in threshold voltage and decrease in transconductance of the device. High transconductance can be achieved by maintaining a high gate capacitance Cgs, which can be provided by using a high-k dielectric as the a)

Materials Department. Electrical and Computer Engineering Department.

b)

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gate insulator material or by decreasing the dielectric thickness. In the latter case of very thin dielectrics, tunneling may occur, resulting in increased leakage. Due to its large dielectric constant, barium strontium titanate [Ba1−xSrxTiO3, (BST)] has been under investigation as a leading candidate material as the capacitor dielectric for future-generation dynamic random access memory19,20 and more recently for use in variable capacitors (varactors) for microwave applications.21,22 The use of the end-member phases (barium titanate and strontium titanate) under the gate in electronic devices has received recent attention.23 Strontium titanate 共SrTiO3兲 has been demonstrated as a viable gate dielectric for Si-based devices.24–26 Gate leakage was greatly suppressed and an equivalent oxide thickness of less than 10 Å was achieved. We propose using BST as a gate dielectric in AlGaN / GaN HFETs. The BST solid solution is in the paraelectric state at room temperature and can display a large field-dependent permittivity. The high dielectric constant of BST thin films (␧ = 20– 500, dependent upon growth conditions, composition, and film thickness) should allow for a thin equivalent oxide thickness while maintaining a low gate leakage current. These properties make BST an attractive high-k dielectric for application in AlGaN / GaN metaloxide-semiconductor heterostructure field-effect transistors (MOSHFETs). This report investigates the incorporation of BST with AlGaN / GaN devices. The initial results demonstrate that incorporating a high-k dielectric as the gate insulator in MOSHFETS is a promising and feasible approach to highperformance microwave devices. II. EXPERIMENTAL PROCEDURE AlGaN / GaN HFET structures were prepared by metalorganic chemical vapor deposition (MOCVD) on sapphire sub-

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strates. The structure consisted of a 2.6 ␮m thick semiinsulating GaN base layer, followed by a 0.5 nm AlN interfacial layer,27 and a 30 nm Al0.3Ga0.7N cap layer. The base layer was rendered semi-insulating by Fe doping during the first 0.6 ␮m of growth.28 BST was deposited on the AlGaN / GaN HFET structures by rf magnetron sputter deposition. The 3 in. Ba0.5Sr0.5TiO3 sputter targets were 30° off axis and a 4.25 in. source-to-substrate distance was used in a sputter-down configuration. The depositions were performed using two opposite facing targets, each operating at 150 W, and a chamber pressure of 50 or 15 mTorr with a 9:1 Ar/ O2 ratio. It has been reported that excess titanium in BST thin films reduces leakage,20,29 and previous studies have shown that the lower pressure condition yields slightly Ti-rich films.30 To determine the effect of BST growth on the transport properties of AlGaN / GaN structures and an optimum deposition temperature, 100 nm BST was first deposited onto several different samples from the same HFET wafer under the growth pressures described above and at various temperatures ranging from 375 to 600 ° C. Hall measurements were taken following the BST depositions. Initial experiments have shown that the BST deposition temperature greatly affected the mobility in the AlGaN / GaN structure, as discussed below. Metal oxide HFETs (or MOSHFETs) were then processed with BST under the gate as well as over the access region in the following manner. Ti/ Al/ Ni/ Au 共200/ 1500/ 375/ 450 Å兲 source and drain ohmic contacts were defined and deposited. Following deposition the contacts were annealed in N2 for 30 s at 870 ° C. The devices were then isolated using a Cl2 reactive ion etch. All devices had a 0.7 ␮m source-to-gate spacing, a 0.7 ␮m gate length, a 2 ␮m gate-to-drain spacing, and a 75 ␮m width. 125 nm of BST was then blanket deposited over one-quarter of a 2 in. wafer. The BST deposition conditions were similar to those described above, with a chamber pressure of 15 mTorr and a deposition temperature of 375 ° C. BST 共40 nm兲 was deposited using the same conditions over another quarter of the same wafer that had been processed in the same manner. Pt/ Au gate metals were deposited and a buffered HF solution was used to etch through the BST to the source and drain contacts. A section of the same wafer that had been previously patterned with standard HFETs was used as a basis for comparison with the devices containing BST under the gate. Transfer length method (TLM) patterns as well as capacitors were included in the pattern to assist in evaluating the contacts, sheet resistance, and capacitance values. The 40 nm sample was then sectioned into two sections and annealed at 500 and 600 ° C in a rapid thermal anneal in an N2 atmosphere for 30 s. A schematic of the MOSHFET structure is shown in Fig. 1(a). Cross-sectional transmission electron microscope (TEM) studies were carried out on representative samples spanning the range of BST growth and anneal conditions to investigate the as-deposited films as well as annealed BST films and the structural quality of the BST/ AlGaN interface. A JEOL 2010 was used for the TEM studies. J. Vac. Sci. Technol. B, Vol. 22, No. 5, Sep/Oct 2004

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FIG. 1. (a) Device schematic for BST/ AlGaN / GaN MOSHFET; (b) quantum well structures used to investigate BST deposition conditions on GaNbased structures; and (c) schematic of device using Si3N4 to passivate the AlGaN surface as well as protect the channel during BST sputtering.

To further evaluate the damage in the semiconductor that resulted in the degradation in charge and mobility during the BST sputtering process, photoluminescence (PL) measurements were performed on GaN samples that contained InGaN quantum wells (QWs). PL studies of buried QWs has been an effective analysis method for observing damage in III-V heterostructures31,32 and GaN in particular33 due to energetic ion bombardment. The InGaN QWs were grown on c-plane sapphire substrates by MOCVD. The QWs were relatively near-surface for comparison to AlGaN / GaN HFET structures, as shown in Fig. 1(b). One structure consisted of a Si-doped GaN template followed by 0.5 ␮m Si-doped GaN buffer layer, 75 Å Si-doped low-temperature (LT) GaN, a 320 Å Si-doped In0.03GaN barrier, a 40 Å In0.09GaN well, a 40 Å In0.03GaN barrier, and a 40 Å LT GaN cap layer. The second structure consisted of a 0.5 ␮m Si-doped GaN buffer layer, 75 Å LT GaN, a 320 Å Si-doped In0.03GaN barrier, a 40 Å In0.09GaN well, a 40 Å In0.03GaN barrier, and a 100 Å LT GaN cap layer. The Si doping concentration in the GaN template was ⬃5 ⫻ 1017 cm−3 and of the cladding for was ⬃1 ⫻ 1018 cm−3 both structures. PL was measured before and after BST growth using a He-Cd laser as an excitation source. Another MOSHFET was processed and Si3N4 was incorporated into the device process to minimize the damage in the HFET structure during BST sputtering as well as to passivate the AlGaN surface. This structure is shown in Fig. 1(c). A similar approach using SiO2 has been shown to protect HEMT structures during BST deposition.34 The devices

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FIG. 2. 2DEG mobility as a function of BST deposition temperature.

were processed in a similar manner as that described above. Ohmic contacts were deposited and annealed, followed by device isolation. Gates were then deposited on some die for measurement standards. A 1700 Å thick Si3N4 layer was deposited using plasma-enhanced chemical vapor deposition. The Si3N4 was etched in areas under the gate in the remaining die using a Cl2 / O2 etch that was carefully calibrated to not etch the underlying AlGaN. This allowed the entire channel of the devices except the region directly under the gate to be protected during the BST deposition. TLM patterns were measured during each step of the process. BST 共20 nm兲 was deposited on this wafer at 375 ° C, 15 mTorr, and an Ar/ O2 ratio of 9:1. III. RESULTS AND DISCUSSION To determine optimum BST growth conditions, initial depositions were performed as described above and Hall measurements were made following the BST deposition.

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Mobility values for samples from a wafer with a mobility of 1730 cm2 V−1 s−1 measured from a sample with no BST decreased with increasing BST growth temperature from 1350 cm2 V−1 s−1 for a sample deposited at 375 ° C, to 600 cm2 V−1 s−1 for a sample from the same wafer with BST grown at 600 ° C, as shown in Fig. 2. A lower mobility value was realized for the film sputtered at a lower pressure for the same temperature, possibly indicating that the high-electronmobility structure (HEMT) structure was damaged by energetic ions during the sputtering since lower pressure plasmas give rise to a larger mean free path for ions. The sheet charge density also showed a decreasing trend with increasing deposition temperature, from 1.3⫻ 1013 cm−2 for the sample with no BST to 1.15⫻ 1013 cm−2 for the sample deposited at 600 ° C and 50 mTorr. Although the decrease in charge was typically not as severe as that of the mobility, charge reduction was generally observed following BST sputtering. Scattering contrast and high-resolution TEM images showed abrupt AlGaN / GaN and BST/ AlGaN interfaces with no evidence of reaction or degradation of the AlGaN at the BST/ AlGaN interface, as shown in Fig. 3. However, an amorphous phase in the BST adjacent to the BST/ AlGaN interface was observed and will be discussed below. The lower BST deposition temperature [required to maintain high mobility in the HEMT two-dimensional electron gas (2DEG)] resulted in a lower dielectric constant of the oxide. A growth temperature of 375 ° C was chosen to balance the tradeoff between BST dielectric constant and HEMT mobility. Pt/ BST/ Pt test capacitors deposited under similar conditions yielded 100艋 ␧ 艋 150 (zero bias). MOSHFETs were then formed as discussed above. Current–voltage characteristics of the processed sample with no BST gave a maximum current of ⬃1050 mA/ mm at a positive gate bias of +1 V and a pinchoff voltage of

FIG. 3. High-resolution cross-sectional TEM images of the BST/ AlGaN inter¯ 0兴) for face (GaN zone axis= 关112 films deposited at (a) 375 ° C and 15 mTorr (total chamber pressure); (b) 450 and 50 mTorr; and (c) 600 ° C and 15 mTorr.

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FIG. 5. Capacitance–voltage measurements for a sample with no BST and 40 nm as-deposited BST.

FIG. 4. Current–voltage characteristics for devices (a) before BST deposition; (b) with BST under the gate as deposited; and (c) BST under the gate following a 30 s N2 anneal at 600 ° C.

⬃−7 V. TLM measurements gave a sheet resistance 共Rsh兲 of 250 ⍀ / square and a contact resistance Rc of ⬃0.7 ⍀ mm, and the local sheet charge extracted from the capacitors was 1.2⫻ 1013 cm−2. The devices with 125 nm BST showed a maximum current of 900 mA/ mm at a positive gate bias of +1 V with a pinchoff voltage of ⬃−12 V. The sample with 40 nm BST under the gate showed a maximum current of ⬃940 mA/ mm at a positive gate bias of +1 V and a pinchoff voltage of ⬃−12 V. On this sample TLM measurements were taken prior to BST deposition. Initial values for sheet resistance as well as contact resistance agreed with those of the baseline HFET, while the sheet resistance increased following BST deposition to ⬃550 ⍀ / square. The contact resistance after BST deposition was 0.7 ⍀ mm, and capacitors again showed a slightly decreased sheet charge compared to the baseline HFET of 9.66⫻ 1012 cm−2. Current–voltage characteristics of the baseline HFET and the sample with 40 nm BST are shown in Figs. 4(a) and 4(b), respectively. It can be seen that, in addition to a lowered maximum current J. Vac. Sci. Technol. B, Vol. 22, No. 5, Sep/Oct 2004

density compared to the baseline HFET, an increased onresistance was also demonstrated for the devices with BST. C – V curves for the baseline HFET and the as-deposited MOSHFET with 40 nm BST are shown in Fig. 5. Figure 6 shows the transconductance values for the devices shown in Fig. 4. The transconductance was reduced from 145 mS/ mm for devices with no BST to 108 mS/ mm following the BST deposition. The cutoff frequency of the device was 18.5 GHz, and the maximum operating frequency was 40 GHz, similar to values measured from standard HEMT wafers grown around the same time. The gate leakage current of the structure containing 125 nm BST was ⬃5 orders of magnitude lower than that of a conventional FET, at ⬃4 ⫻ 10−7 mA/ mm at 50 V, as shown in the three terminal measurement data in Fig. 7. A similar reduction was found in devices from the wafer section with 40 nm BST. The increase in pinchoff voltage discussed above for both the 125 and 40 nm thick BST films indicates a much lower dielectric constant of the BST films than anticipated. A zero bias dielectric constant of 43 and 20 were extracted from the capacitance data for the 125 and 40 nm thick BST films, respectively. The 125 nm thick BST on the HEMT structure was deposited under similar conditions and for the same time as the Pt/ BST/ Pt test structures above. These thin oxide films can be modeled as a low dielectric constant interfacial

FIG. 6. Transconductance curves for standard device without BST, with as-deposited BST, and post-annealed BST with increased dielectric constant.

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FIG. 7. Gate leakage for standard HFET, as-deposited MOSHFET, and MOSHFET following 600 ° C anneal.

layer in series with a bulk layer with a higher dielectric constant when the films are used between two metal electrodes;19,29 such a layer will be present at least on the BST/gate interface in our structures, but two such layers will be present in the test structures. The reason for the disparity between the metal-oxide-metal structures and the metaloxide-semiconductor dielectric constants is still under investigation. To better understand the differences in films and the difference in dielectric constant between the thicker film and the thinner film, cross-sectional TEM was performed on representative samples. A cross-sectional image of a 83 nm thick BST film is shown in Fig. 8(a). An amorphous layer was observed in the BST adjacent to the AlGaN interface, while the BST film is crystalline away from the interface. Similar observations of amorphous interlayers have been reported for BST films grown at low temperature.35,36 The amorphous layer of BST near the BST/ GaN interface presumably has a low dielectric constant relative to the crystalline phase of the film since the high dielectric constant is a feature of crystalline perovskite titanates. A 35 nm thick film grown at 375 ° C and 15 mTorr was observed to be completely amorphous by scattering contrast TEM, as shown in Fig. 8(b). Thus, the difference between dielectric constants of the 125 nm BST film and the 40 nm film can be attributed to a crystalline layer with a high dielectric constant in series with a lower dielectric constant amorphous layer, resulting in a higher overall apparent dielectric constant of the thicker film than that of a predominantly amorphous film. The thinner film may have had a similar structure as it was slightly thicker than the 35 nm sample observed by TEM, but if so, the crystalline layer was most likely still very thin. To increase the dielectric constant of the BST films deposited at low temperature, the wafer with the 40 nm BST film was sectioned and annealed. One section of the wafer was annealed at 500 ° C for 30 s in N2, while another section was annealed at 600 ° C for 30 s in N2 as well. The 500 ° C annealed sample showed little change in device characteristics. As can be seen in Fig. 9, the zero bias capacitance increased significantly, while the pinchoff voltage decreased JVST B - Microelectronics and Nanometer Structures

FIG. 8. Cross-sectional TEM images of (a) 96 nm as-deposited BST film ¯ 0兴; BST reflections were used to obtain the dark-field (GaN zone axis= 关112 image); (b) 35 nm as-deposited BST film; and (c) 35 nm BST film following 30 s 600 ° C N2 anneal. g = 0002 GaN two-beam dark-field condition was used for (b) and (c).

significantly for the 600 ° C annealed sample. The extracted sheet charge decreased to 8.7⫻ 1012 cm−2 and the pinchoff voltage of the capacitor decreased to −7.5 V, while the maximum current and TLM data remained unchanged from their values prior to annealing. Figure 4(c) shows the I – V characteristics of a device with the 40 nm BST film and demonstrates that annealing decreased the pinchoff voltage. The increased zero bias capacitance and decreased threshold voltage after annealing are attributed to the increase of the BST dielectric constant of ⬃66 in comparison with the asdeposited value of ⬃20. TEM images of the 35 nm thick BST layer structure have shown that the amorphous layer

FIG. 9. Capacitance–voltage measurements for a sample with a 40 nm BST film annealed at 500 and 600 ° C in N2 for 30 s.

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thickness decreased to 3 nm after annealing at 600 ° C for 30 s in N2, as shown in Fig. 8(c). Similar films were annealed to 750° and 870 ° C for 30 s in N2 and it was found that the amorphous layer was still present after annealing at the higher temperatures. The transconductance increased to 125 mS/ mm following annealing the devices due to the increase in the dielectric constant of the oxide, as shown in Fig. 6. This data suggests that high transconductance may be possible by incorporating BST as a gate dielectric. Following annealing, the gate leakage increased by ⬃1 order of magnitude and was still ⬃4 orders of magnitude lower as compared with a conventional FET. The leakage data of the annealed 40 nm film is shown in Fig. 7. PL measurements were made on two different QW structures [Fig. 1(b)] that were probed before and after BST deposition to evaluate near-surface damage in the structures. The spectra were also compared for samples with BST and with BST removed. The BST layer was found to affect the intensity only slightly. BST was deposited under several different conditions. On structure 1, depositions were performed under the conditions described above used to deposit the BST on the HFETs. On structure 2, similar conditions were used as well, but the chamber pressure was increased to 50 mTorr. For both samples, the relative integrated PL intensity decreased to less than 0.05 when normalized to the intensity measured prior to BST growth. This further confirms the sensitivity of the GaN structures to the plasma used during the BST growth. AlGaN / GaN HFET devices typically suffer from “dcto-rf dispersion,” (also referred to as “current slump”), which is the reduction in current at ac frequencies when compared to the characteristics shown at dc. Si3N4 has been shown to passivate the surface of the semiconductor and to mitigate this current reduction.37 Si3N4 was incorporated into the MOSHFET process prior to BST deposition to perform the dual function of passivating the surface as well as protecting the underlying channel from the energetic species of the plasma, as shown in Fig. 1(c). Hall measurements on the sample with no dielectric yielded a charge density of 1.5 ⫻ 1013 cm−2 and mobility of 1540 cm2 V−1 s−1, and TLM measurements gave a sheet resistance of 272 ⍀ / square. Following Si3N4 deposition, the TLM measurements gave 276 ⍀ / square. After 20 nm BST deposition (with Si3N4 covering the AlGaN between the TLM pads), the sheet resistance measured by TLM increased to 330 ⍀ / square. Similar results were obtained over several structures on the wafer. Current–voltage curves were also measured for each of the steps in the process. A maximum current of ⬃1.2 A / mm was measured at a positive gate bias of 1 V for both the standard sample and the Si3N4 passivated sample, while the maximum current for the sample with BST under the gate was ⬃1025 mA/ mm. Pulse measurements 共80 ␮s兲 performed using a curve tracer showed the passivation by the silicon nitride was effectively eliminating dc-to-rf dispersion. The 80 ␮s pulse measurement on devices with BST in the etched trench in the silicon nitride showed Si3N4 was no J. Vac. Sci. Technol. B, Vol. 22, No. 5, Sep/Oct 2004

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longer passivating the AlGaN surface, as a current slump was observed in the pulse measurements. Similar experiments on other wafers have shown that the Si3N4 effectively passivates following etching, indicating that the BST deposition renders the Si3N4 passivation ineffective. Although the magnitude of increase in sheet resistance was less for this sample than that of the samples without SiN protection, the resistance was increased. A similar reduction in gate leakage to the devices with no SiN but BST under the gate was observed. It may be possible to incorporate an additional dielectric layer such as SiO2 on the SiN or to use a thicker SiN passivation layer in a similar structure to protect the channel more completely during the BST deposition. IV. CONCLUSIONS This article shows initial results that demonstrate incorporating high-k dielectrics as gate insulators in HFETs results in a larger transconductance and smaller pinchoff voltage than dielectrics with a lower dielectric constant. Transconductance was reduced from 145 mS/ mm for a device with no BST to 108 mS/ mm for a device with 40 nm BST under the gate 共kBST = 20兲 and increased to 125 mS/ mm following a 600 ° C anneal after which the dielectric constant of the BST increased to 66. Gate leakage was reduced by ⬃5 orders of magnitude for as-deposited films, while the reduction decreased to four orders of magnitude following BST annealing. Cross-sectional TEM showed the BST crystallinity depends on deposition time when deposited at low temperatures, resulting in varied dielectric constants. Importantly, high-resolution images of the BST/ AlGaN interface do not show intermixing or reaction between the BST and the AlGaN despite the harsh growth environment of the BST films, even at high temperatures. Although the dc device characteristics were promising, improved dielectric deposition conditions are necessary. We have shown that rf sputtering of the BST damages the underlying GaN. However, these studies do demonstrate the viability of high-k dielectrics with GaNbased devices. An alternate nonenergetic growth method of the oxide, such as MOCVD or molecular-beam epitaxy, would be more suitable for further study of high-k oxides on GaN and AlGaN / GaN structures. ACKNOWLEDGMENTS The authors would like to gratefully acknowledge support of the Office of Naval Research through the Center for Advanced Nitride Electronics (CANE), monitored by Dr. Harry Dietrich, and from DARPA under program manager Dr. Stuart Wolf. Sputtering system fabrication was supported by the Army Research Office through DURIP equipment Award No. DAAD 19-99-1-0060. This work made use of MRL Central Facilities supported by the MRSEC program of the National Science Foundation under award No. DMR00-80034. 1

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