Alternative Technology Concepts for Low-Cost and ...

46th International Symposium on Microelectronics (IMAPS 2013) | Sept. 30 - Oct. 3, 2013 | Orlando, FL USA

Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing F. Roozeboom a,b, M. Smets a, B. Kniknie a, M. Hoppenbrouwers a, G. Dingemans b, W. Keuning b, W.M.M. Kessels b, R. Pohl c and A.J. Huis in't Veld a,c a) TNO, PO Box 6235, 5600 HE Eindhoven, The Netherlands ; b) Eindhoven University of Technology, PO Box 513, 5600 MB Eindhoven, The Netherlands ; c) University of Twente, PO Box 217, 7500 AE Enschede, The Netherlands Phone: +31 40-2474880; Email: [email protected] ; [email protected]

Abstract The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10-20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al 2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing. For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use LaserInduced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.

Key words 3D interconnect, TSV drilling and filling, Spatially-divided Deep Reactive Ion Etching, ALD oxide passivation, Laser-Induced Forward Transfer, redistribution layers

silicon is dominated by the room temperature Bosch process [4]; see Fig. 1a. This process consists of two alternating half-cycles that are repeated: 1) etching with SF6 plasma, and 2) passivation of the feature sidewalls and bottom with a protecting fluorocarbon polymer (i.e. -(C2F4)n-) liner deposited from C4F8 plasma. The first half-cycle is an ion-assisted isotropic etch step with SF6 plasma. It would proceed - if non-interrupted mainly by the non-directional F-containing radicals to form volatile SiFx products. In order to minimize the lateral etching component the etch steps are quickly interrupted by C4F8 passivation steps. During each etch step a bias voltage is applied to the substrate holder. This causes a directional physical ion flux from the plasma that by bombarding the exposed substrate parts sputters the polymer off the feature’s bottom part, thus leaving the sidewall passivation intact, and enabling the anisotropic etching.

I. Introduction 3D through-silicon vias (TSVs) date back to two patents by Bell Labs [1] and IBM [2] in the 1960s. Yet, only in the past few years, with the continuous on-chip scaling reaching the point where Moore’s Law (an empirical economic law) approaches its constraints, TSV technology has received increasing interest for 3D integration [3]. Next to cost reduction the technical driving forces are the reduced form factor and the increased performance of TSV-connected stacked-die devices, such as reduced RC delay and low power consumption..

II. Spatially-Divided Deep Reactive Ion Etching: A New Concept TSV manufacturing consists of ‘drilling’ and ‘filling’. Today’s conventional Deep Reactive Ion Etching (DRIE) of

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A. The Passivation Step in Spatial DRIE: ALD-Based, Low-Pressure or Atmospheric The selected mask material generally affects etch rate, undercutting, and surface quality of etched features [7]. ALD deposited oxide hard masks like Al2O3 and TiO2 are reported to have lower pinhole density and higher etch selectivity than conventionally deposited hard masks [8][10]. Thus a further improvement in the spatial approach can be expected from replacing the CVD-based C4F8 passivation by ALD-based deposition cycles of SiO2, or other oxides (e.g. Al2O3). Unlike the C4F8 case the ALDbased passivation layer is self-limiting and chemisorptive of nature, and less complex in its layer thickness control. This will lead to better control of the anisotropy and sidewall smoothness in the total process. The idea of using temporal ALD passivation in DRIE of high aspect ratio nanosize features was conceived recently, yet without any experimental data [11]. Experimental indications were reported recently in a paper on a timeefficient plasma-assisted process for low-temperature (50400 oC) temporal ALD of SiO2 using H2Si[N(C2H5)2]2 precursor known as SAM.24, and O2-plasma [11]. Precursor dosing times as short as ~50 ms were sufficient to obtain a high conformality (95 ± 5 %) over high aspect ratio (30:1) trenches; see Fig. 2a. This indicates that the recombination of O-radicals in such trenches plays no dominant role [13]. We found that a non-plasma atmospheric spatial ALD alternative for oxidic passivation is also possible. Fig. 2b shows such an Al2O3 layer grown from trimethyl aluminum and H2O vapor during 600 cycles of 13.5 ms each in a rotary atmospheric ALD reactor described earlier [14]. The layer has good step conformality ( 80 %) in trenches with aspect ratios exceeding 130:1. Atmospheric thermal ALD of Al2O3 is already commercially used by the solar cell industry depositing films at least one order of magnitude faster than in conventional (temporal) ALD [15]. Recently, we also succeeded in plasma atmospheric spatial ALD of SiO2. This opens up the way to the development of highspeed atmospheric passivation in DRIE, which would simplify and accelerate etching, and thus reduce costs (subsecond cycles of oxide passivation deposited at ~1 nm/s).

Fig. 1. a) Conventional, DRIE (Bosch) process scheme with temporal switching of consecutive etch (odd-numbers) and passivation (even numbers) half-cycles. The horizontal bar in grey represents a pre-patterned hard mask. Alternative spatial process modes with C 4F8 passivation (b) and with spatial ALD SiO2 passivation (c) of a wafer which moves horizontally back and forth under spatially divided reaction zones. Blue arrows pointing upwards indicate exhaust lines.

The etch and passivation cycle times are each typically 1-10 seconds with 0.1-1 μm etched per cycle. The process enables plasma etching of deep vertical microstructures (aspect ratios AR  20:1) in silicon with relatively high etch rates (typically 3-5 μm/min) and selectivities (up to ~200:1) against a hard oxide mask, usually SiO2 [5]. An accelerated etch alternative is to convert the above process from its temporal (i.e. time-separated) into the spatially separated regime [6]. The spatial separation can be accomplished by inert gas (e.g. N2) bearing ‘curtains’ of heights down to ~20 μm, or even smaller (Fig. 1b). These curtains confine the reactive gases to individual (often linear) injection zones constructed in a gas injector head. By horizontally moving the substrate back and forth under the multiple injector head one can create the alternate exposures needed to complete the overall cycle. The optimum pressure in each injection slot is obtained by balancing the various gas flows which are injected into and exhausted from the slots, and by a proper design of the distance between the various slots and the gas bearing gap height (a smaller gap causes a larger pressure field gradient between the various channels).

B. Spatial DRIE Reactor Design The basics of a full spatial DRIE process scheme are illustrated in Fig. 1c. Fig. 3 gives an impression of the spatial reactor gas inlet design: a wafer is moving under a (plasma) injector head with inlets for etch gas (SF6/O2), bearing gas (N2) and passivation gas (conventional C4F8 or ALD oxide). The pressures pe, pp and ppu assumed for the etch, passivation and purge zones, respectively, and the corresponding flow rates Фe and Фp, lengths Le and Lp and heights He, Hp and Hg of the injection zones are listed in Fig. 3. H is a convenient design parameter to obtain the desired

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Fig. 3. Sketch of the multichannel gas injector head in spatial DRIE. The injector contains the etch gas inlet, the passivation gas inlet(s) and an outer guard gas inlet to screen off the ambient atmosphere. All inlets can be separated from each other by purge outlets (drawn) and by bearing gas inlets (not drawn here, but see Fig. 1c). Each gas is injected through an inlet with or without microplasma source.

during the etch half-cycle. The gas separation accomplished by effective gas bearings between the etch and passivation zones will enable passivation at atmospheric pressure and etching at sub-atmospheric pressure, provided that the ion directionality is sustained in such microplasma design. Thus, our spatial DRIE concept can potentially yield unprecedented etch rates and anisotropy control. C. Timescale Analysis for Convection, Diffusion, Deposition and Mass Supply In order to further optimize the spatial SF6/O2 etch and oxide passivation process parameters preliminary we performed gas transport simulations to analyze all relevant timescales. The simulation program used is a general purpose CFD model CVD-X to predict and optimize deposition processes in semiconductor manufacture [16] and incorporates specific models for the description of rarefied gas transport inside trenches. Thus, transient multi-scale simulations have been performed of flow, precursor transport and deposition reactions in ALD-type reactors filled with high aspect ratio trenched wafers. For more details on the simulation program we refer to [16], and for the detailed simulation to [17]. A short synopsis of the most relevant formulas involved is given in Table 1. The simulations were done for the passivation of three main feature categories with different lateral scales and densities (see Table 2) : 1) 50 μm wide microsystems, 2) 1 μm diameter 3D-vias, and 3) sub-micron (0.15 μm) trenches. For a typical conventional DRIE reactor with ~30 liters volume and process parameter (flow rates, pressure, temperature) settings from [5], we found the relevant process time to be dominated by the flushing time scale,

Fig. 2. SEM images of deep silicon trenches lined with ALD oxide layers: a) a plasma ALD SiO2 layer deposited at low-pressure in trenches with aspect ratio ~30 during 830 cycles on top of an ALD Al2O3 /thermal SiO2 layer stack inside (after [11] ;  Electrochemical Society 2012); b) an ALD Al2O3 layer deposited at 1 atm. in 138:1 aspect ratio trenches during 600 cycles in a rotary ALD reactor (trenched wafers kindly provided by Fraunhofer CNT/Namlab, Dresden). Note: in an actual DRIE application the passivation would require only a few ALD cycles (i.e. monolayers of SiO2 or Al2O3).

pressures. The pressure drop over each channel is proportional to the cube of its compartment height (Δp~H3),and linear in L and Ф. Depending on the pressures needed for the spatial DRIE process one can calculate the different dimensions of the bearings. A typical example for low-pressure DRIE is shown in Fig. 3, indicating these dimensions to be in the mm to sub-mm range. Note, that the pressure for passivation, pp, is taken to be one order of magnitude higher than the pressure pe for etching. Thus the energy of the fluorine ions from the etching plasma will be higher than that for any ions attracted from the passivation plasma (more collisional losses for F-ions in case of C4F8 passivation or oxygen ions in case of oxide ALD passivation). Thus, in an entirely spatial process with continuous voltage biasing of the full substrate, the ion bombardment of the passivation layer will be sustained

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Table 1. Formulas used for the timescale analysis of convection, diffusion, deposition and mass supply in the three different 3D feature categories; see text. (a = aspect ratio; A = area). See also refs. [16 - [17].

D. Microplasma sources The dimensions of the DRIE reactor design described above, call for miniaturized plasma sources or arrays. To fulfill the accelerated etch rate requirements a logical further step is to make the etch cycle proceed at higher pressure, ideally at atmospheric pressure, or at least subatmospheric, e.g. 100 mTorr). Today, high-density plasma sources are being designed and explored by the use of miniaturized plasma sources or arrays. This research aims at a 100-fold increased electron density [18], far beyond the traditional 1012 cm-3, enabling high-speed etching at correspondingly higher pressures. The challenge is to avoid increased ion scattering, while maintaining the directionality of the ion bombardment. Fig. 5 shows the potential gain in plasma density ne upon miniaturization of ultrahighfrequency plasma sources in combination with using UV light sources. Scaling in combination with higher plasma frequency (THz) and photo-stimulation can generate higher plasma densities. The ambition is to enable increased etch rates and anisotropy control in 3D Si etching.

Table 2. Dimensions and densities of three characteristic 3D features used in the timescale analysis of convection, diffusion, deposition and mass supply in spatial DRIE. Flat wafers are used as reference.

which is of the order of seconds (6.12 s for 90% volume flushed; 12.25 s for 99% volume flushed). The calculated optimum saturation time (transition point from the Langmuir-dominated regime to the supply-dominated regime) at 50 oC is around 20-50 ms. This corresponds very well with the experimentally determined Si-precursor dosing times for saturation [12]. The results in miniaturized reaction zones of 2.5 mm height and 5 mm length (in both directions), representative for our spatial reactor dimensions, indicate an optimal pressure range from ~0.5 Torr for flat structures to ~5 Torr for TSVs and microsystems, at ~100 oC, and 5 - 200 ms timescales depending on the feature’s aspect ratio; see [17]. It is evident that for lower temperatures and higher aspect ratio features the timescales increase (more Langmuirdominated). Yet, the corresponding timescales for depositing a few passivation monolayers remain typically in the sub-second regime, even at room temperature, i.e. the targeted process temperature for DRIE in the spatial regime. Considering the mass supply needed to etch bulk silicon (specific density of 5∙1022 atoms/cm3) it will be obvious that the Si-etching half-cycle requires prolonged time intervals. This requirement is the main driving force for the development of high-density plasmas in Si-etching.

Fig. 5. Characteristics of microplasmas in a plane of the spatial size d and the plasma density ne. From [18];  IEE Japan, 2006.

III. Laser-Induced Forward Transfer (LIFT) For medium TSV-sizes and -densities laser drilling can be very attractive from a cost point of view. Furthermore, lasers can be used to deposit metals. Traditional Pulsed Laser Deposition (PLD) is known as an inherently slow process. Yet, the laser metal deposition technology used here, called LIFT (Laser Induced Forward Transfer), enables a fast process with good industrial potential. It has been widely investigated and many varieties of the process exist [19]-[24]. In our experimental set-up a pure metal donor on a transparent carrier is transferred by ultra-short (picosecond) laser pulses on to a moving substrate as shown in Fig. 6. The donor layer (e.g. a Cu film) is positioned face-down, the air gap between donor and substrate being typically 10-50 µm. This way, metal tracks with widths in the µm range can be formed using a ps-laser with a spot size of 5-20 µm.

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µm was selected. The track morphology and electrical conductivity were analyzed. Track width and height ranged from 10 to 15 µm and from 1 to 4 µm, respectively. The resistivity of the deposited lines was about 5 times higher than that of bulk material. This was achieved in air and without any thermal curing afterwards. Similar process settings were applied to deposit droplets inside 10 μm x 130 μm vias. The major part of the droplets landed within a diameter of ~ 20 µm. Fig. 8 shows that TSVs with relatively high aspect ratios can be filled although further process optimization is necessary in terms of wetting and surface chemistry to achieve higher via fill degrees. The same LIFT process has been repeated with a receiving substrate without TSVs. This way free-standing Cu deposition pillars can be obtained with similar diameters as shown in Fig. 8, but with much higher length. This opens up new ways to apply the LIFT process for 3D interconnection (3D-printed wirebonds). More details on these experiments can be found elsewhere [24]. The volume of material transferred in the ps-experiments above is estimated to range from 15 to 80 μm3. The number of droplets required for a 100 % fill of a via as shown in Fig. 8 is estimated to be between 400 and 2500. For a laser source with 400 kHz repetition rate this can be accomplished in 1-4 ms. In practice more time will be required since donor refreshment and scanner speed require additional time. It we extrapolate the results above and combine these with the properties of state-of-the-art picosecond lasers we can conclude that LIFT is an interesting candidate for costeffective mid-size TSV filling, and for printing conductor tracks (redistribution layers, RDL) and wire bonds.

Fig. 6. Principle of Lased-Induced Forward Transfer.

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Cu deposit

c Fig. 7. Images of conductive thin-film copper lines deposited on glass substrates with LIFT with laser parameters: wavelength 515 nm and pulse length 7 ps. a) Optical micrograph of a line printed over copper contact pads that are used to measure the line resistance. The contact pads (dark areas) are sized 1x1 mm2; b) SEM image and c) confocal micrograph of the 3D geometry of the printed line. Note the different z-axis scaling compared to x- and y-axes.

To form continuous 2D and 3D structures, the deposited droplets should overlap each other (Fig. 6), while scanning the substrate (vsubstrate). In order to fully use the donor layer for each laser shot, the donor layer should be refreshed at a rate (vdonor) exceeding the substrate scan speed. Using a straightforward laboratory-scale configuration for the donor refreshment, experiments have been performed using green and UV wavelengths of a ps-laser machining facility. Fig. 7 shows copper lines formed by overlapping droplets. To facilitate easy alignment a basic deposit/droplet size of ~10

50 µm

Filled 10 µm TSV

50 µm

Fig. 8. a) cross-section SEM image of a 10 μm Filled diameter 10 TSVµm filled with Cu using picosecond LIFT process conditions; b) top view of same TSV TSV showing some Cu deposited on the surface just outside the TSV (same scale).

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IV. Concluding remarks We have reviewed our recent research on disruptive technology concepts with industrial potential for interconnect manufacturing, especially on the ‘drill and fill’ of advanced Si-based interconnects like TSVs and RDLs. These concepts may prove their potential as cost-effective or high-speed options. In particular DRIE of silicon has the potential of yielding unprecedented etch rates and becoming a high-speed alternative for the conventional Bosch process, when realized in the spatially-divided regime. An extra advantage of this regime is the significant reduction of parasitic passivation depositing on, and flaking from the reactor walls since no etch or passivation products are likely to deposit in the spatial DRIE regime. Furthermore, F-free, thus environmentally friendlier passivation chemicals can be used. When, for example, the passivation half-cycles are applied with ALD-based SiO2 rather than with C4F8, the anisotropy control can be simplified and yield reduced scallops and mask undercut. Once TSVs have been etched, the SiO2 ALD process can be continued for conformal via isolation. Here, very high via liner conformality (up to 110%) has been recently reported for plasma-assisted thermal ALD SiO2 in state-of-the-art TSVs with ø = 2 µm and 25:1 aspect ratio [25]. Meanwhile, we have developed µ-plasma sources (Dielectric Barrier Discharge type) which we recently showed to be effective in atmospheric spatial ALD of SiO2 on planar Si-wafers and in ultradeep trench filling at 50 oC using bis(diethylamino)silane, BDEAS. In addition, we have shown that DBD µ-plasma sources can successfully be used in dry etching of silicon using SF6 gas. This all points to a potential breakthrough of the disruptive concept of spatial ALD-enhanced DRIE. We also foresee the potential of this concept in other demanding application fields like Atomic Layer Etching for nanoscale MOSFETs requiring etching with atomic layer resolution and supreme sidewall passivation to suppress line edge roughness. Finally, for the Cu-filling of TSVs with medium sizes and densities and for the printing of various RDLs and other 3Dinterconnect features LIFT seems also very promising.

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