cascaded inverter, Total Harmonic Distortion (THD). I. INTRODUCTION. The harmonic distortion is a common occurrence in elec- trical power networks due to ...
2014 International Symposium on Power Electronics, Electrical Drives, Automation and Motion 1
Harmonic Mitigation Technique for Multilevel Inverters in Power Systems Concettina Buccella1 , Carlo Cecati1 Maria Gabriella Cimoroni2 , Kaveh Razi2 1,2
Dept. of Information Engineering, Computer Science and Mathematics and 1 DigiPower s.r.l., University of L’Aquila, 67100 L’Aquila, Italy emails: [concettina.buccella, carlo.cecati, mariagabriella.cimoroni, kaveh.razi] @univaq.it
Active technique provides multiple functions such as harmonic reduction, isolation, damping and termination, load balancing, power factor correction, and voltage regulation, but its cost is high. The hybrid technique is more attractive in comparison to the previous ones from economical points of view, particularly for high-power applications [15]. Paper [16] discusses practical experiences and mitigation methods of harmonics in wind power plants. Simulation case studies obtained from the harmonic analysis of various practical wind power plants are presented, including both resonance and nonresonance conditions. Paper [17] presents a new structure based on a multi-objective particle swarm optimization (MOPSO) formula to mitigate specific harmonics besides hierarchical multi-output support vector regression (HMSVR) to generalize the solutions. In paper [18] a simple harmonic compensation strategy is proposed for current-controlled DG unit interfacing converters. By separating the conventional proportional and multiple resonant controllers into two parallel control branches, the proposed method realizes power control and harmonic compensation without using any local nonlinear load harmonic current extraction or point of connection (PoC) harmonic voltage detection. Paper [19] presents a technique to mitigate zero-sequence harmonics in power distribution systems. The method is based on the concept of passive zero-sequence harmonic filter. Its basic configuration has been expanded to create a double-tuned filtering feature, allowing to trap two harmonics with one filter. In this paper the 5-level three-phase cascaded inverter is considered and a new procedure, based on graphycal analysis, is proposed to compute the two switching angles α1 and α2 ables to mitigate a pair of harmonics among third, fifth and seventh in inverter output voltage according to standard code requirements. Experimental results are obtained by the prototype built at the laboratory. These results validate the presented procedure.
Abstract—A new procedure to mitigate some harmonics is presented for a 5-level cascaded inverter, varying the modulation index. The two switching angles α1 and α2 are computed by using a procedure based on graphycal analysis by using Chebyshev polynomials and the Waring’s formulae. The proposed mitigation technique is applied to reduce a pair of harmonics among third, fifth and seventh in inverter output voltage according to standard code requirements. Experimental results are also extracted by the prototype built at the laboratory. The measured results confirm the quality of the presented procedure. Index Terms—Selective Harmonic Mitigation (SHM), 5-level cascaded inverter, Total Harmonic Distortion (THD).
I. I NTRODUCTION The harmonic distortion is a common occurrence in electrical power networks due to the nonlinear characteristics of many industrial and commercial loads such as power converters, fluorescent lamps and variable speed motor drives used in conjunction with industrial pumps, fans, compressors. If many loads operate, the cumulative effect causes serious harmonic distortion levels, additional losses and reduced power factor [1], [2], [3]. Large industrial converters and variable speed drives are capable of generating significant levels of distortion at the point of common coupling (PCC), where other users are connected to the network [4], [5]. Because of the strict requirement of power quality at the input AC mains, various harmonic standards and engineering recommendations are employed to limit the level of distortion at the PCC [6], [7]. To comply with these harmonic standards, harmonic mitigation techniques have been developed [8]-[11]. They can be divided in three categories: passive techniques, active techniques, and hybrid techniques using a combination of active and passive methods. Passive techniques include the connection of series line reactors, tuned harmonic filters, and the use of higher pulse number converter circuits. In these methods, the undesirable harmonic currents flowing into the system can be prevented by installing a high series impedance in order to block their flow or diverting the flow of harmonic currents by means of a low-impedance parallel path [12]. By using active harmonic reduction techniques, the improving in the power quality is obtained canceling the original distortion by injecting equal, but opposite current or voltage distortion into the network [13], [14]. Passive technique is traditionally used to absorb harmonic currents because of low cost and simple robust structure, but it provides fixed compensation and creates system resonance.
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II. P ROBLEM FORMULATION The considered three-phase 5-level cascaded inverter configuration is shown in Fig. 1 [20]-[24]. The Fourier series expantion of the phase voltage vAN is: vAN (ωt) =
73
4Vdc π
n
[cos (nα1 ) + cos (nα2 )] sin(nωt) n n = 1, 3, 5, 7, ... (1)
2 A
B
Table I G RID C ODES EN 50160 AND CIGRE WG 36-05.
C
Not multiple n 5 7 11 13 17 19 23 25 >25
N
Figure 1.
Three-phase 5-level cascaded inverter.
π 2
harmonics Multiple n 3 9 15 21 >21
of 3 Vn (%) 5 1.5 0.5 0.5 0.2
Even
harmonics
n 2 4 6....10 >10
Vn (%) 2 1 0.5 0.2
x51 + x52 = s5 − 5ps3 + 5p2 s x71 + x72 = s7 − 7ps5 + 14p2 s3 − 7p3 s where s = x 1 + x 2 , p = x1 x 2 . The transformed system, considering the mitigation of the third, fifht and seventh harmonics is: ⎧ s = 2m1 ⎪ ⎪ ⎨ |P3 (p) | ≤ l3 (4) |P5 (p) | ≤ l5 ⎪ ⎪ ⎩ |P7 (p) | ≤ l7
where Vdc represents the dc source, α1 and α2 are the switching angles to compute. The following condition: 0 ≤ α1 ≤ α2 ≤
Odd of 3 Vn (%) 6 5 3.5 3 2 1.5 1.5 1.5 0.2+32.5/n
(2)
is imposed. The transcendental disequations system, required to determine the two switching angles α1 and α2 , is written as: ⎧ cos (α1 ) + cos (α2 ) − 2m1 = 0 ⎪ ⎪ ⎪ ⎪ |cos (3α) + cos (3α2 )| / (6m1 ) ≤ l3 ⎪ ⎪ ⎪ ⎪ |cos (5α) + cos (5α2 )| / (10m1 ) ≤ l5 ⎪ ⎪ ⎪ ⎪ |cos (7α1 ) + cos (7α2 )| / (14m1 ) ≤ l7 ⎨ |cos (11α1 ) + cos (11α2 )| / (22m1 ) ≤ l11 (3) ⎪ ⎪ . ⎪ .. ⎪ ⎪ ⎪ ⎪ ⎪ .. ⎪ ⎪ ⎪ . ⎪ ⎩ |cos (rα1 ) + cos (rα2 )| / (2rm1 ) ≤ lr
where P3 (p) = P5 (p) = P7 (p) =
The first equation is used to control the magnitude of the fundamental voltage and the remaining disequations are used to control some predominating harmonics; for example 3rd , 5th , 7th , 11th , 13th , ...rth harmonic components. m1 is the V1 where V1 is the modulation index defined as m1 = V1max fundamental output peak voltage and V1max is the maximum obtainable fundamental peak voltage expressed as V1max = 8Vdc π . li is the maximum allowed level imposed by both the CIGRE WG 36–05 and the EN 50160 grid code requirements [6], [7] for the ith harmonic component. Table I shows the limits specified in these grid codes. In the columns Vn (%) there are the values of individual harmonic voltages at the supply terminals, given in percent of nominal voltage of the system.
−12p+4(2m1 )2 −3 3 8[10p2 −5(2m1 )2 p+(2m1 )4 ] + 5 −2 −6p + (2m1 )2 + 1
32[−14p3 +14(2m1 )2 p2 −7(2m1 )4 p+(2m1 )6 ] + 7 56[10p2 −5(2m1 )2 p+(2m1 )4 ] + − 7 +4 −6p + (2m1 )2 − 1
A graphical analysis of the system (4) is developed in order to find the angles (α1 , α2 ) ables to mitigate the required harmonics. It performs the following steps: 1) draws the straight lines y = ±l, where l = min {l3 , l5 , ..., lr } 2) identifies some acceptable values of p ∈ [0, 1] such that the polymomials obtained after the transformation |P3 (p)| , |P5 (p)| , ..., |Pr (p)| ≤ l , 3) computes (ξ1 , ξ2 ) by solving the equation ξ 2 − 2m1 ξ + p=0 4) calculates the angles α1 = arccos (ξ1 ) and α2 = arccos (ξ2 ). In order to explain the steps 1. and 2., Figures 2, 3, 4 and 5 are shown. Fig. 2 shows the polynomials P5 and P7 and it is related to the fifht and seventh harmonic mitigation, for m1 = 0.8. In order to give a clear and global graphical view, the polynomials are drawn in a wide range of variation of p also is, as mentioned, p ∈ [0, 1]. In this figure, the straight lines y = ±l are not displayed, a zoom in the valid interval is shown in 3. The value p = 0.6161 is chosen because the polynomials P5 and P7 evaluated in the selected p, assume values within the strip bounded by the straight lines y = ±l , where l = 0.05. Notice that p can be arbitrarily chosen at the inner of the interval [a, b], where a is obtained as the intersection of the
III. P ROPOSED PROCEDURE The proposed procedure is based on the transformation of the disequations system (3) introducing the following odd Chebyshev polynomials Tj j = 1, 3, 5, ... and the Waring’s formulae that are written, in the following, up to seventh degree: T1 (xi ) = xi = cos (αi ) T3 (xi ) = 4x3i − 3xi = cos (3αi ) T5 (xi ) = 16x5i − 20x3i + 5xi = cos (5αi ) T7 (xi ) = 64x7i −112x5i +56x3i −7xi = cos (7αi ) i=1, 2, x31 + x32 = s3 − 3ps
74
3
150
0.05
P7(p)
P (p), P (p)
P (p) 7
7
50 P (p) 5
0 P5(p)
5
P5(p), P7(p)
100
0
a
−50 −0.5
1
0.5
0
p
1.5
2.5
2
0.322
3
Graphical analysis for m1 = 0.8.
Figure 2.
b
−0.05 0.324
0.326
0.328
p
0.33
0.332
0.334
Figure 5.
A zoom of the Fig. 4.
Figure 6.
5-level cascaded H-brige inverter experimental setup.
0.336
0.15 P (p) P5(p), P7(p)
7
0.1
P5(p)
0.05 0 −0.05 0.6
Figure 3.
a 0.605
0.61
0.615
b 0.62 p
0.625
0.63
0.635
0.64
A zoom of the Fig. 2.
curves y = P7 (p) and y = 0.05 and b as the intersection of the curves y = P5 (p) and y = −0.05. Similarly Figures 4 and 5 are shown for m1 = 0.6, choosing p = 0.3288.
A control board, containing Xilinx’s FPGA (SpartanII xc2s50) and Atmel’s AVR mega microcontroller (ATmega16L), has been used to produce switching angles applied to the inverter [25], [26]. The DC voltage of each H-bridge has been set to 40 V and a small resistive load has been connected to output of the inverter. To measure the output voltage THD, Stanford Research Systems network signal analyzer (Model SR780) has been used considering the first 15 harmonics. Table II reports the measured THD and the values Vn (%) for the mitigated harmonics. Figures 7-13 show the measured inverter output voltages and the corresponding harmonic analysis for the cases considered in the Table II. The results shown in the previous figures confirm the validity of the proposed procedure, since the chosen harmonics are mitigated according to the code requirements.
IV. A PPLICATION AND R ESULTS The proposed procedure has been applied to the threephase 5-level cascaded inverter to reduce some harmonics and Table II shows the switching angles obtained to mitigate two harmonics among third, fifth and seventh in inverter output voltage. A low power single phase prototype has been built up in the laboratory. Fig. 6 shows the experimental setup.
6 5 P7(p)
P5(p), P7(p)
4 3
V. C ONCLUSION
2 P5(p)
In this paper a new procedure to mitigate a pair of harmonics from the inverter output voltage has been presented for a 5-level cascaded inverter. A procedure based on graphycal analysis has been used to compute the two switching angles α1 and α2 which have been applied to power MOSFET switches. The proposed mitigation technique has been applied to reduce third and fifth or fifth and seventh harmonics in inverter output
1 0 0
Figure 4.
0.2
0.4
p
0.6
0.8
1
Graphical analysis for m1 = 0.6.
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4
Table II C OMPUTED SWITCHING ANGLES , MEASURED THD AND COMPUTED Vn (%). m1
α1 [rad]
α2 [rad]
0.8 0.7 0.6 0.5 0.85 0.55 0.5
0.2927 0.4798 0.6647 0.7303 0.1885 0.3652 0.4510
0.8730 1.0322 1.1451 1.3129 0.7703 1.4041 1.4706
Experimental THD (%) 14.6 25.3 37.9 43.5 12.9 27 27.1
k=3 2.83 0.37 1.33
Vn (%) k=5 2.18 3.03 1.35 0.88 1.71 4.88 1.52
k=7 3.86 2.78 1.57 4.17 -
Figure 10. Inverter output voltages and corresponding harmonic analysis for 5th and 7th harmonics mitigation, for m1 = 0.5.
Figure 7. Inverter output voltages and corresponding harmonic analysis for 5th and 7th harmonics mitigation, for m1 = 0.8.
Figure 11. Inverter output voltages and corresponding harmonic analysis for 3rd and 5th harmonics mitigation, for m1 = 0.85.
Figure 8. Inverter output voltages and corresponding harmonic analysis for 5th and 7th harmonics mitigation, for m1 = 0.7.
Figure 12. Inverter output voltages and corresponding harmonic analysis for 3rd and 5th harmonics mitigation, for m1 = 0.55. Figure 9. Inverter output voltages and corresponding harmonic analysis for 5th and 7th harmonics mitigation, for m1 = 0.6.
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[12] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of three-phase improved power quality AC-DC converters,” IEEE Transactions on Industrial Electronics, vol. 51, no. 3, pp. 641–660, 2004. [13] Z. Du, L. M. Tolbert, and J. N. Chiasson, “Active harmonic elimination for multilevel converters,” IEEE Transactions on Power Electronics, vol. 21, no. 2, pp. 459–469, 2006. [14] D. Li, Q. Chen, Z. Jia, and J. Ke, “A novel active power filter with fundamental magnetic flux compensation,” IEEE Transactions on Power Delivery, vol. 19, no. 2, pp. 799–805, 2004. [15] S. Khalid and A. Triapthi, “Comparison of sinusoidal current control strategy & synchronous rotating frame strategy for total harmonic reduction for power electronic converters in aircraft system under different load conditions,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 1, no. 4, pp. 305–313, 2012. [16] B. Badrzadeh, M. Gupta, “Practical Experiences and Mitigation Methods of Harmonics in Wind Power Plants,” IEEE Trans. Ind. Applicat., vol. 49, no. 5, pp. 2279 - 2289, 2013. [17] S. Beheshtaein, “Multi-objective selective harmonic mitigation for cascaded H-bridge multilevel inverters connected to photovoltaic systems using hierarchical multi-output support vector regression,” 39th Annual Conference of Industrial Electronics Society, (IECON 2013), pp. 72 - 79, 2013. [18] H. Jinwei, L.W. Yun, F. Blaabjerg, W. Xiongfei “Active Harmonic Filtering Using Current-Controlled, Grid-Connected DG Units With Closed-Loop Power Control,” IEEE Transactions on Power Electronics, vol. 29, no. 2, pp. 642 - 653, 2014. [19] P. Bagheri, W. Xu, “A Technique to Mitigate Zero-Sequence Harmonics in Power Distribution Systems,” IEEE Transactions on Power Delivery, vol. 29, no. 1, pp. 215 - 223, 2014. [20] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2197–2206, Jul. 2010. [21] K. Gopakumar, N. Abdul Azeez, J. Mathew, A. Dey, M. Kazmierkowski, “A Medium Voltage Inverter Fed IM Drive using Multilevel 12-sided polygonal Vectors, with Nearly Constant Switching Frequency Current Hysteresis Controller,” IEEE Trans. Ind. Electron., vol. PP, no. 99, pp. 1, 2013. [22] C. Buccella, C. Cecati, M. G. Cimoroni, “Investigation about numerical methods for Selective Harmonics Elimination in cascaded multilevel inverters”, Proc. of Int. Conf. on Electrical Systems for Aircraft, Railway and Ship Propulsion (ESARS), Bologna, Italy, pp. 1-6, Oct. 2012. [23] C. Buccella, C. Cecati, M. G. Cimoroni, “Harmonics Elimination in 5-Level Converters Operating at Very Low Switching Frequency,” Proc. of Int. Conf. on Ind. Tech. (ICIT), Cape Town, pp. 1946-1951, Feb. 24-27, 2013. [24] C. Buccella, C. Cecati, A. Piccolo, P. Siano, “Fuzzy Control of Multilevel Inverters for Fuel Cell Generator Sets,” in A. Keyhani and M. Marwali (Eds.): Smart Power Grids 2011, POWSYS, Chapter 4, pp. 83–102, 2011. [25] [online] http://www.mcselec.com/?option=com_content&task= view&id=14&Itemid=41. [26] [online] www.xilinx.com/support/download/.
Figure 13. Inverter output voltages and corresponding harmonic analysis for 3rd and 5th harmonics mitigation, for m1 = 0.5.
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