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Abstract— An improved direct digital converter (IDDC) suitable for bridge-connected resistive sensors is presented in this paper. The input stage of a dual-slope ...
IEEE SENSORS JOURNAL, VOL. 16, NO. 10, MAY 15, 2016

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An Improved Direct Digital Converter for Bridge-Connected Resistive Sensors Ponnalagu Ramanathan Nagarajan, Boby George, Member, IEEE, and Varadarajan Jagadeesh Kumar, Senior Member, IEEE Abstract— An improved direct digital converter (IDDC) suitable for bridge-connected resistive sensors is presented in this paper. The input stage of a dual-slope analog-to-digital converter is altered to accommodate a resistive sensor bridge, as its integral part and the logic of conversion incorporate automatic compensation for offset, offset drift, and gain errors. Through a detailed error analysis of the DDC presented earlier, the effects of the non-ideal characteristics of practical components on the performance of the DDC are quantified. From the analysis, it is determined that mismatch between the bridge elements and the input offset of op-amps significantly affect the output. While the earlier version of the DDC requires offline correction for offset and gain errors, the proposed IDDC provides in situ correction for these and hence can also compensate drifts. Simulation studies and experimental results demonstrate the practicality of the proffered scheme and indicate that the worst case error of ±0.2% due to offset in op-amps and mismatch in nominal resistances of sensing elements reduces to ±0.05% with the use of the proposed compensation technique. Index Terms— Direct digital converter, dual slope ADC, resistive sensors, strain gauges, Wheatstone bridge.

I. I NTRODUCTION

R

ESISTIVE sensors such as strain gages and piezo resistances are commonly utilized in the bridge form. Use of four sensing elements connected in the form of a Wheatstone bridge provides good linearity, increased sensitivity and automatic temperature compensation [1]–[3]. To obtain a digital output from such bridge connected resistive sensors, the bridge is excited by a voltage source (dc or ac) and the analog output of the bridge is amplified (instrumentation amplifier for dc or carrier frequency amplifier for ac excitation). The amplified output is then converted using an analog to digital converter (ADC) [4]. In spite of the fact that ac excitation is free of offset errors, it is no longer used for resistive bridges as the use of ac requires (i) amplitude stabilized oscillator and (ii) complex synchronous demodulator or detector [5]. On the other hand dc excitation is preferred for resistive sensors connected in bridge form mainly due to the fact that (i) precision dc reference sources are easily available for excitation and (ii) low offset and offset drift opamps available today ensure reduced offset errors in the output. An alternate approach is to convert the change in the sensor resistances to a quasi-digital signal, such as frequency Manuscript received December 20, 2015; revised February 20, 2016; accepted February 23, 2016. Date of publication February 29, 2016; date of current version April 8, 2016. The associate editor coordinating the review of this paper and approving it for publication was Prof. Jun Ohta. The authors are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/JSEN.2016.2535666

or time [6]. Resistance to frequency converters proposed earlier can have significant nonlinearity in the output due to switching delays [6]–[8]. An improved resistance to frequency converter presented in [9] overcomes this problem. Resistance to time period or pulse-width converters are available but are suited only for a single sensor element, either independently excited or used in the quarter-bridge form [10]–[14]. However, all these schemes require additional interface unit to convert the quasi-digital output to digital [15]. Direct Digital Conversion (DDC) schemes suitable for single element and push-pull type resistive sensors have been reported earlier [16], [17]. A triple slope type DDC scheme suitable for bridge connected resistive sensors proposed earlier requires three integration periods for a typical conversion [18]. A dual-slope direct digital converter (DDC), suitable for a resistive sensor bridge presented earlier is analyzed and possible error sources are identified [19]. The analysis indicates that, of all the possible sources of errors, the offset in opamps and mismatch in the nominal values of the bridge elements affect the output significantly. A novel compensation technique presented here reduces the errors in the output due to offset in opamps and mismatch in the nominal values of the bridge elements and thus realizes an improved DDC, namely IDDC. Fig. 1 shows the functional block diagram of the modified (improved) direct digital converter suitable for four resistive sensor elements R1 , R2 , R3 and R4 connected in a bridge form. The resistances of sensor elements R2 and R3 increase with the input x being sensed and that of R1 and R4 decrease with x as: R1 = R4 = R0 (1 ∓ kx) and R2 = R3 = R0 (1 ± kx).

(1)

Here k is the transformation constant and R0 is the nominal value of the sensor elements, when the input x is zero. II. D IRECT D IGITAL C ONVERTER In order to analyze the DDC presented earlier [19], the operation of the DDC is briefly explained here. With the SPDT switch S3 (in Fig. 1) permanently set at position ‘1’, the scheme can work as the DDC [19]. As in a conventional dualslope technique, here too an auto-zero phase as detailed in the flow chart of Fig. 2 is invoked to ensure that the output of the integrator is zero at the start of the conversion phase [19]. A. Conversion Phase of the DDC The conversion phase is made of two periods of integration T1 and T2 as illustrated in Fig. 3. While the first integration is carried-out for a preset period T1 , the second integration period T2 is measured and taken as the output.

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Fig. 1.

Block schematic of the improved direct digital converter for bridge connected resistive sensors.

Fig. 3.

Waveforms at cardinal points of the converter.

and V2 = V R

Fig. 2.

Here period T1 is set by the control and logic unit (CLU) of the DDC as N1 Tc , where Tc is the clock given to the internal timer of the CLU and N1 is a preset integer. At the start of period T1 , the control and logic unit sets both switches S1 and S2 in position ‘0’ and hence the bridge gets excited by +VR . The voltages V1 and V2 become: R2 VR (1 ± kx) = R1 + R2 2

(3)

During T1 , with S2 in position ‘0’, opamps OA2 , OA3 and OA4 realize a three-opamp instrumentation amplifier, and amplify (V2 – V1 ) to give Vo of OA4 , say Vo |T1 as:

Flowchart showing the conversion logic of the DDC.

V1 = V R

R4 VR (1 ∓ kx). = R3 + R4 2

(2)

Vo |T1 = G(V2 − V1 ) = −GV R kx

(4)

In (4), G is the gain of the three-opamp instrumentation amplifier given by G = (1 + 2R/RG ). Thus during T1 , a current i c = GV R kx/R I flows through the capacitor CI of the integrator. At the end of T1 , the integrator output voltage, voi |T1 is: voi |T1 =

GV R kx T1 RI C I

(5)

RAMANATHAN NAGARAJAN et al.: IDDC FOR BRIDGE-CONNECTED RESISTIVE SENSORS

Equation (5) indicates that if x is positive, then the integrator output at the end of T1 will be positive and the comparator output vc will be high, as shown by the solid line in Fig. 3. Sensing vc to be high, the CLU sets switches S1 and S2 at position ‘1’ and hence a current i c = −V R /R I will flow into CI and discharge it, resulting in the output voi of the integrator reducing (solid line in Fig. 3) and becoming zero. On the other hand, if x is negative, then the output of the integrator at the end of T1 , will be negative and the comparator output vc will be low. Sensing vc to be low, the CLU sets switch S1 at position ‘0’ and S2 at position ‘1’. The bridge is now excited with +V R and output of OA4 , Vo = −(V1 + V2 ) = −V R . In this condition, the current i c = +V R /R I will flow through CI . Once again CI will be discharged and hence the output of the integrator will rise and reach zero (indicated by the dotted line in Fig. 3). In either case, once the output of the integrator reaches zero, the comparator output will flip (‘1’ to ‘0’ when x is positive and ‘0’ to ‘1’ if x is negative). The CLU logic is set such that the elapsed time between the end of T1 and the time at which the comparator output vc flips is measured (say N2 clock cycles) and sent as the output. It is to be noted that at the end of a conversion cycle, the output of the integrator is zero and hence a new conversion can be initiated without the need for an auto-zero phase. At the end of T2 , the charge in CI is zero indicating that the charge acquired by CI during T1 is removed during T2 . Hence: GV R kx VR T1 = T2 . RI C I RI C I

(6)

Substituting T1 = N1 Tc and T2 = N2 Tc in (6) we get: N2 = (N1 Gk)x

(7)

Equation (7) indicates that the final output count N2 can be made to indicate x directly by choosing N1 Gk appropriately. For example, if x is strain in μm/m (popularly called micro strains) then N1 Gk can be chosen to be 1000000 so that N2 indicates x in micro strains. The polarity of x can be easily determined by sensing the output of the comparator vc at the end of T1 . If vc is high at the end of T1 then polarity of x is positive. On the other hand, if vc is low at the end of T1 then polarity of x is negative. Equation (7) is derived assuming all the circuit components are ideal. Errors that may arise due to non-ideal characteristics of the components are analyzed next. III. E RROR A NALYSIS Effects of individual non-idealities of different components on the output of the DDC are analyzed in this section. A. Effect of Reference Voltage Mismatch While deriving (7) it was assumed that the magnitudes of the positive and negative reference voltages obtained are equal (|+V R | = |−V R |). In practice, this may not be achieved and hence the output may deviate from the expected value depending on the extent of mismatch, which is determined by various circuit parameters. In general, at node ‘a’, we can

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take the positive reference voltage as +Vp and the negative reference as −Vn , then (6) becomes: kx GV p Vn N1 Tc = N2 Tc . RI C I RI C I

(8)

If the ratio of magnitudes of the two reference voltages,  namely, +V p /|−Vn | is λ then (8) can be rearranged and the output N2 can be obtained as: N2 = N1 Gk

Vp x = (N1 Gλk)x Vn

(9)

A comparison of (9) with (7) indicates that a mismatch in the magnitudes of the positive and negative reference voltages introduces a gain error in the output. B. Effect Due to ON Resistance of the Switches Equations (4) and (5) were derived assuming switches S1 and S2 to be ideal. However, when implemented practically, these switches will possess non-zero contact (on state) resistances. The contact resistance r1 of S1 will have negligible effect on the output as it carries nearly zero current. On the other hand, the on resistance r2 of switch S2 will modify voi at the end of T1 as     r2 VR r2 r2 − (10) voi |T1 = kx G − + T1 RI C I 4R 2RG 4R Similarly at the end of T2 , voi is:     r2 −V R r2 r2 + 1 + kx − voi |T2 = voi |T1 + T2 RI C I 2R RG 2R (11) Charge gained during T1 and charge removed during T2 , are equal, hence we obtain:     r2 N1 r2 r2  r2 + + − N2 ≈ N1 kx G 1 + 2R 4R 2RG 4R   r2 r2 2 2 + − N1 Gk x (12) 2R RG Comparison of (12) with (7) illustrates that the on resistance of switch S2 introduces a gain error, an offset and also nonlinearity in the output. In general the design can be such that the value of R is chosen to be several orders of magnitude higher than r2 (hundreds of kilo ohms compared to few ohms). On the other hand such a constraint cannot be met with RG as the value of RG is normally in the range: few hundred ohms to few kilo ohms. Thus, care must be taken to use a switch that has very low on resistance as S2 . C. Effect Due to Mismatch in the Nominal Resistances of Sensing Elements While deriving (7), it was assumed that all the resistors R1 , R2 , R3 and R4 have resistance R0 , when x = 0. But in practice there can be mismatch in the nominal values of sensor elements. In general, the nominal values of resistances R1 , R2 , R3 and R4 may be R0 , α R0 , β R0 and γ R0 , respectively.

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With such a variation in the nominal values of sensor resistances the output N2 is: 4αγ (αβ + 2β + γ ) N2 = G N1 kx

2 α(β + γ ) + γ (1 + α) α(β + γ ) − γ (1 + α) + G N1 α(β + γ ) + γ (1 + α) α(β + γ ) − γ (1 + α) 2 2 k x (13) + G N1 α(β + γ ) + γ (1 + α) Comparing the output for an ideal case as given in (7) with (13), we observe that mismatch in the nominal resistances of the four sensing elements introduces a gain error, an offset and non-linearity in the output. A method for correcting this error is explained in the sequel. D. Effect Due to Offset Voltages of the Opamps and Comparator The opamps OA1 , OA2 , OA3 , OA4 and OA5 in the circuit of Fig. 1 will possess input offset voltage when implemented with practical opamps. Offset voltage Vos1 of OA1 modifies the output Va of OA1 as VR + 2Vos1 when S1 = 0 and S3 = 1 and −VR + 2Vos1 when S1 = 1 and S3 = 1. Thus, Vos1 introduces an equivalent mismatch of 4Vos1 between the magnitudes of the reference voltages +VR and −VR . This situation is already dealt with in section A. The offset voltages Vos1, Vos2 , Vos3 and Vos4 of the opamps OA1 , OA2 , OA3 and OA4 alter the output Vo during T1 and T2 as: Vo |T1 = −Gkx (V R +2Vos1)+G (Vos2 +Vos3)+2Vos4 (14) Vo |T2 = V R − 2Vos1 +Vos2 −Vos3 +3Vos4

an offset of only 0.14 % of the full scale at the output. Even if these offsets are trimmed to zero, the offset drift of opamps will introduce errors in the output. To overcome this problem an offset correction technique is proposed in the sequel. The comparator OC may also have an input offset voltage, Vosc and due to the presence of that, the comparator will change its state when voi reaches Vosc instead of zero. This will not introduce any error in the measured time periods as long as the change of state in either direction happens at Vosc , (i.e., the offset voltage is constant within a conversion cycle) hence an input offset of the comparator will not affect the output of the proposed DDC. E. Effect Due to Bias Currents of the Opamps Another non-ideal characteristic, whose effect needs to be analyzed is the bias current drawn by the input terminals of the opamps OA1 , OA2 , OA3 , OA4 and OA5 . Let I1+ , I2+ , I3+ , I4+ and I5+ are the bias currents of the non-inverting inputs and I1− , I2− , I3− , I4− and I5− be the bias currents of the inverting inputs of the opamps OA1 , OA2 OA3 , OA4 and OA5 respectively. It is easily seen that the effect of bias currents I1+ , I1− , I2+ , I3+ and I5+ on the output of the DDC is negligible. On the other hand, I2− , I3− , I4+ , I4− and I5− significantly affect the performance of the DDC. Due to the presence of I2− , I3− , I4+ and I4− , the output Vo of OA4 , during T1 will be: Vo = −Gkx V R + R(I3− − I2− + I4− − 2I4+ ) and Vo , during T2 will be Vo = V R − R (I2− + I3− − I4− + 3I4+ )

(15)

With these values, the output voi would have traversed through during T1 and T2 respectively: G[kx(V R +2Vos1)−(Vos2 +Vos3)]−(2Vos4 −Vos5) T1 RI C I (16) (−V R +2Vos1 −Vos2 +Vos3 −3Vos4 +Vos5) voi |T2 = voi |T1 + T2 RI C I (17)

voi |T1 =

From (16) and (17), the output N2 can be obtained as:   V R + 2Vos1 N2 = G N1 kx V R − 2Vos1 + Vos2 − Vos3 + 3Vos4 − Vos5 G(Vos2 + Vos3) + (2Vos4 − Vos5) − N1 . (18) V R − 2Vos1 + Vos2 − Vos3 + 3Vos4 − Vos5 From (18) we can deduce that the offsets in OA1 , OA2 , OA3 , OA4 and OA5 introduce a gain error and an offset in the output. While the gain error introduced by the offset voltages of opamps is small (