An Improved SVPWM Method for Multilevel Inverters - IEEE Xplore

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The presented scheme is developed for Cascaded H-Bridge. (CHB) inverter. In the proposed strategy, the sectors are defined by two parameters serving for the ...
15th International Power Electronics and Motion Control Conference, EPE-PEMC 2012 ECCE Europe, Novi Sad, Serbia

An Improved SVPWM Method for Multilevel Inverters M. Trabelsi 1, L. Ben-Brahim 1, T. Yokoyama 2, A. Kawamura 3, R. Kurosawa 4, T. Yoshino 4 1

Qatar University, Doha, Qatar, [email protected] Tokyo Denki University, Tokyo, Japan, [email protected] 3 Yokohama National University, Yokohama, Japan 4 TMEIC, Tokyo, Japan

2

Abstract — This paper proposes a new general Space Vector PWM (SVPWM) method for Multi-Level Inverters (MLI) based on a generalization of dwell-times calculation. The presented scheme is developed for Cascaded H-Bridge (CHB) inverter. In the proposed strategy, the sectors are defined by two parameters serving for the easy calculation of dwell-times. A very simple mapping is used to achieve the SVPWM for any n-level inverter. In addition a dead-band hysteresis is introduced in the SVPWM algorithm to avoid the output voltage level jumping. The simulation results show the effectiveness of the proposed method. Keywords — Space Vector PWM, General dwell-times, Voltage Level Jump Compensation, Multilevel Inverters.

I. INTRODUCTION The growing use of Medium voltage high power converters in industry, has led to the progress of MLI topologies. As a result, several types of MLI were proposed such as the Neutral Point Clamped (NPC) inverter which is now a standard topology in the industry with its 3-level version. However, the clamping diodes and the balance of the dc-link capacitors issues present some problems for a higher number of levels [1]. Another alternative structure is the Multi-Cell (MC) topology. The most important topologies are Cascaded Multi-cell [2] and the Flying Capacitors [2-3]. These MC topologies, based on the series connection of cells, are easily scalable and highly reliable as they permit the operation even with some faulty cells [4]. This connection produces low distortion output voltage without increasing the switching frequency and the voltage stress on switching devices. This topology reduces also the dv/dt ratio at the inverter output voltage. Controlling MLI using a suitable modulation technique is necessary for their proper operation. Many modulation techniques, to control MLI, have been studied extensively during the past decades such as sinusoidal PWM [5], third harmonic injection PWM [6] and SVPWM [7-8]. The main aims to be achieved by the modulation technique are: lower switching losses, reduced Total Harmonic Distortion (THD) in the output current, less computation time and easy implementation. SVPWM strategy is proven to be appropriate for controlling MLI, as it offers great flexibility in optimizing switching pattern design and a high suitability for digital implementation. However, SVPWM becomes more complex when applied to more than 3-level inverters. This complexity is due to the high number of space vectors and redundant switching states [9]. For

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example, there are 343 switching states (73 switching states) for a 7-level three-phase CHB inverter which includes 127 active voltage vectors. Thus, SVPWM realization needs complex computations to select voltage vectors and to calculate the dwell-times. This complexity increases with the increase of the number of levels. Several approaches were proposed to realize the SVPWM [10-13]. A complex space vector algorithm has been used to calculate dwell-time and select voltage vectors for 5level inverter [10]. In [11], a fast SVPWM algorithm was proposed nevertheless the dwell-time calculation looks complex due to the use of Euclidean space vector representation. The implementation of SVPWM involves the sector identification, dwell-time calculation, switching-vector determination, and optimum-switchingsequence selection for the inverter output voltage vectors [10–13]. Most of these techniques suffer from the frequent presence of an irregular level jumps in the output voltage which causes a higher dv/dt in the inverter output [14]. This phenomenon is one of the major factors of the increase of the EMI. In this paper, a new approach for implementation of the SVPWM technique is proposed. Unlike the methods used in [7-13], the proposed algorithm provides a general solution of dwell-time computation for any n-level inverter, without any significant increase in computations. In addition, the presented technique uses a simple mapping for generating the switching vectors and the optimum switching sequence. A hysteresis dead-band is introduced in the proposed algorithm to reduce the dv/dt by suppressing the level jumps in the output voltage of the inverter. As a result, the inverter output voltage is free from voltage level jumps. The theoretical analysis and simulation results of the proposed SVPWM technique for 7-level inverter are presented in this paper. II. PROPOSED SYSTEM Fig. 1 shows the nine-cell three-phase CHB inverter. The input DC links of all cells are obtained from multiple secondary windings which are shifted from each other by 20° using a phase-shift transformer. For the proper operation of the CHB inverter, a balanced three-phase voltage reference Vuvw* are input to the proposed SVPWM scheme. Thus, the three-phase voltage reference are transformed into Vαβ* in the α-β frame. SVPWM for multilevel inverters is considered as an extension of SVPWM for the two-level voltage source inverter. In this case, 8 switching states (23) can be achieved for the 6 switches.

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One Cell

Vuvw*

18

3

Dead-time generation

36

New SVPWM technique Fig. 1. The proposed system based on a 9-cell cascaded inverter

These switching patterns can be represented using binary digits 0’s (which represents the on of the lower switch) and 1’s (which represents the on of the upper switch). These patterns can be represented in a hexagonal form with 6 non-zero vectors (V1 to V6), taking into account that one vectors was omitted since it represents zero output voltages which is V0 (000 or 111) as shown in Fig. 2. The angle between any adjacent two non-zero vectors is 60 degrees. Following the derivation of the voltage reference Vref and its angle θ from Vαβ*, the SVPWM algorithm consists of the following steps: ƒ Determination of the sector where the voltage reference tip is located; ƒ After the consideration of the operation in sector1, the dwell-times (switching durations) represented by t1, t2 and t0 which represent the time widths of the vectors V1, V2 and V0 respectively are calculated (the dwell-times are calculated within the sampling time Ts); ƒ Determination of the switching pattern in sector 1; ƒ Determination of the switching pattern for all sectors. Thus, since the SVPWM for the 7-level inverter (Fig. 3) is an extension of the SVPWM for 2-level inverter (Fig. 2), the proposed strategy is based on the abovementioned steps. However, the sector is extended into encompass other regions. The presented technique reduces the computational complexity of the conventional SVPWM strategies due to the large number of space vectors and redundant switching states. This is achieved with a fast location of

the reference vector, a generalization of the dwell-time equations irrespective of the number of levels, and an optimum determination and selection of switching states. Unlike several techniques, the proposed algorithm will generate the inverter gate signals in a fast manner using a fixed execution time irrespective of the number of levels. The proposed selection strategy of the switching states among the 343 possible cases is simplified by dividing the sectors into two types of triangular called regions. First, the region in which the voltage reference tip is located is selected. Then, depending on the type of region (Fig. 3), a proper derivation of dwell-times is computed.

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Fig. 2. Space Vector diagram for 2-level inverter

The details of the various steps are explained in the following sections A. Sector determination The voltage magnitude Vref is obtained from transforming the u-v-w voltage reference into the α-β frame using Clark’s transformation. 1

V V

0





V V V

(1)

Then, the reference angle θ with respect to α-axis can be determined by: θ

V

tan

(2)

V

Consequently, the operation sector number, for any given reference vector, is given by [15]: Fig. 3. Space vector diagram

The proposed algorithm is summarized by the following flowchart:

s

1

floor

(3)

B. Region type identification This step consists on the identification of the type of region (triangular) in which the reference vector tip is located. For a MLI, the number of regions in the space vector is given by: nR

6

n

1

(4)

where nR is the number of regions, and n is the number of levels. This leads to 216 regions for a 7-level CHB inverter. In order to reduce the algorithm complexity, the proposed method allows narrowing down the region search, by using the α-β coordinates of the reference vector. Thus, the only information required for the tip location is the region type defined by the following; Type1:

Fig. 4. Proposed Space vector algorithm flowchart

V

√3V Type2:

V

√3V

(5)

C. Dwell-time calculations In this paper, a new dwell-times calculation method is proposed. The computations for each switching state are simplified. As a result, the execution time of the SVPWM scheme is reduced. The proposed dwell-time equations depend mainly on the region type and on two parameters H given by (6) and L given by (7). These parameters are defined as two bounds serving for the identification of the vector location. The first parameter H divides the space vector into six hexagons (for a 7-level space vector, the number of hexagons is equal to 6). The second parameter L divides the sectors horizontally (L represents

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the layer number) as shown in Fig. 3. Moreover, the dwell-time equations given by (8) depend on the number of level n of the output voltage. Thus, these computations are valid for any n-level inverter θ 1 (6) H floor n 1 . m . cos L

floor n

1 . m . sin θ

1

(7)

Type1: T

t t

n T

1 . m . sin n

θ

1 . m . sin θ Type2:

t

T

H

L

n

t

T

n

1 . m . sin

H L

L

1 (8)

1 . m . sin θ

θ H

1

t T t t where ma is the modulation index. To validate the proposed dwell-time computations, the equations given by (8) are computed for the standard 3lvel inverter (n=3). In this case, as mentioned above, an n-level inverter is characterized by n3 switching states. Thus, a three-level inverter is characterized by 27 switching states. The space vector diagram for the threelevel inverter is divided into six sectors. There are 24 active states, and three zero states that lie at the center of the hexagon. Each sector is extended into encompass four regions (Fig. 5). This leads to the following well known formula [16]. Region1: H

1, L

1

T 2. m . sin

t

θ

t T 2. m . sin θ Region2: H 2, L 1 T 2. m . sin

t

θ

1

t T 2. m . sin θ Region3: H 2, L 1 t

T 1

2. m . sin

t

T 2. m . sin Region4: H

T 2. m . sin

t t

θ θ

2, L

T 2. m . sin θ

(9)

Fig. 5. Space vector diagram for 3-level inverter (Sector1)

where V0, V1 and V2 are vectors that define the triangle region in which the voltage reference vector tip is located as shown in Fig. 6. The rotation sequence between the three vectors in region1 (region type1) is also illustrated in the same figure. It’s worth noting that this rotation sequence will be reversed in even sectors. D. Switching states selection for the first sector In this paper, the switching transition of only one device at any time is considered to minimize harmonic components. Thus, the selected states should minimize transitions during the sampling period. For example, in the case of location of the reference vector in region1, a distribution of states during the sampling time is shown in Fig. 7. For the given example, the switching sequence for the u-phase will be given by SuR1 = 0111110. One of salient advantages of the proposed SVPWM technique is that the switching sequences for the three phases can be easily determined from the sequences calculated for region1 as follows:

1 S S

2 θ 1

As known, the principle of SVPWM method is to find the nearest three vectors, known as the NTV approach, which approximately define the reference voltage vector to minimize harmonic components. It’s worth noting that the inverter performance significantly depends on the selection of these switching vectors. The application durations of the switching vectors are given by the dwelltime equations given by (6). Thus, the characteristic voltseconds equation is given by: t V t V T (10) t V

S S

Type1: S R H SR L S R S Type2: SR H S R L S R S

1 1 (11) 1 1

E. Switching states selection for all sectors Once the switching states in sector1 are determined for the n-level inverter, the switching states for the other five sectors can be determined using a mapping between sector1 and the other sectors as given by Table I.

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TABLE I. RELATIONSHIP BETWEEN SWITCHING STATES IN VARIOUS SECTORS

Switching states of phase u, v, w Sector

Su

Sv

Sw

I

Su

Sv

Sw

II

- Sv

- Sw

-Su

III

Sw

Su

Sv

IV

- Su

- Sv

- Sw

V

Sv

Sw

Su

VI

- Sw

- Su

- Sv

Fig. 6. Possible switching states as well as the rotation sequence of the three vectors (region1)

This level jump is seen also in the line-to-line voltage (Fig. 12) which can cause problems for motor drive applications. In theory, this crossing is represented by a modification in the H parameter value (Hexagon number) within the sector (during a sixth of fundamental period). However, the crossing can occur once or twice within the sector and consequently it can occur six times or twelve times during the fundamental period. Thus, in motor drive applications, motors can fail due to insulation stress caused by repetitive peak voltage and high dv/dt ratio. When this ratio is very high, the voltage gradient between turns and between phase windings can be excessively high, resulting in premature breakdown of the motor insulation system and ultimately motor failure. This problem is most prevalent on higher systems voltage because the peak terminal voltage experienced often exceeds the insulation. To overcome this problem, a dv/dt filters are usually used to protect AC motors. In addition, the increase of the dv/dt ratio is one of the major factors of the increase of the Electromagnetic interference (EMI). Thus, this paper proposes a new solution for the compensation of the level jump in the output line voltage (Fig. 15) and line-to-line voltage (Fig. 16) by using a dead-band technique (Fig. 14). This strategy is based on dynamic dwell-time calculations depending on the H parameter calculation. This means that the dead-band technique proceeds as a hysteresis used for the adjustment of the H parameter value within the sector at each variation. The hysteresis bandwidth ∆H0, calculated using a new parameter H0, is given by: ∆ n

1.35 1 . m . cos

(12)

θ

The modified flow chart is shown in Fig. 13. H=6

Crossing point between 36 2 hexagons

Fig. 7. States distribution over the sampling period

H=5

F. Gate signals generation The final step consists on the generation of the gate signals from the switching states in order to control the MLI switches.

25

35

H=4 16

24

34 33

23

32

H=3

III. SIMULATIONS Many simulation tests were done in order to verify the SVPWM approach under a wide range of modulation indexes. These tests show that the inverter output voltage quality is affected by the modulation index variation in the motor drive applications. However, an unexpected level jump in the output occurs with some modulation indexes. In reality, this level jump (Fig. 10 and Fig. 11) is due to the crossing Vref from a hexagon to another (Fig. 8 and Fig. 9).

9

15

14

22

21

31

30

H=2 4 H=1

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1

8

7

13

6

3 2

5

12 11

20

10

19

29

28 27

18 17

Fig. 8. A single jumping within the sector

26 Vref

H=6 36 H=5 25

35

H=4 16

24

Crossing points between 2 hexagons 34 33

23

32

H=3 9

15

14

22

21

31

30

H=2 4

8

7

13

12

20

19

29

28

H=1 1

6

3 2

5

11

10

27

18 17

26 Vref Fig. 12. Voltage level jumping due to a double crossing (line-line voltage)

Fig. 9. A double jumping within the sector

Unexpected Level Jump

Fig. 10. Voltage level jumping drop due to a single crossing

Fig. 11. Voltage level jumping due to a double crossing

Fig. 13. Modified SVPWM flowchart

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A new hysteresis dead-band was proposed to improve the output voltage waveforms by suppressing the inherent level jumps in the SVPWM technique. A 9-cell three-phase CHB inverter was used as prototype to validate the proposed method. Theoretical analysis and simulation results were shown to prove the originality and the effectiveness of the presented design. ACKNOWLEDGMENT The authors would like to acknowledge the support of Qatar Foundation through the NPRP Grant #08-548-2223. REFERENCES [1]

[2] Fig. 14. Proposed Hysterisis compensation [3] [4]

[5]

[6] [7] [8] [9]

Fig. 15. Voltage level jumping compensation

[10]

[11] [12]

[13]

[14]

Fig. 16. Voltage level jumping compensation (line-line voltage)

[15]

IV. CONCLUSIONS A newly generalized SVPWM technique was presented in this paper. The proposed algorithm allows a fast DSP execution time.

[16]

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