Highly ntegrated 3-0MMlC Technology Being Applied To
Novel Masterslice GaAs- and Si-MMIC's Tsuneo Tokumitsu, Makoto Hirano*, Kimiyoshi Yamasaki*, Chikara Yamaguchi* and Masayoshi Aikawa
NTT Wireless Systems Laboratories 1-2356 Take, Yokosuka-shi, Kanagawa 238-03, Japan *NTT System Electronics Laboratories 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa 243-01, Japan Tel: +81-468-59-3084, Fax: +81-468-59-5098, email:
[email protected]
ABSTRACT A novel masterslice MMlC design approach employing a 3-D MMlC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.
INTRODUCTION Over the past several years, MMlC technology has progressed and has been implemented with reasonable success in various commercial application fields. This progress takes us one step closer to-forthcoming multimedia era. However, MMlC development depends strongly on market size. Some issues remain that are impeding more widespread application of MMIC's. These are; (1) high development and fabrication costs, (2) long TAT for fullcustom designs, and (3) the complex design procedure for die-size minimization due to 2-D layout limitations. The three-dimensional (3-D) MMIC[''[61 has gone a long way toward resolving these issues. 3-D MMlC technology, which uses thin polyimide layers on a semiconductor wafer, significantly increases the integration level of multifunction MMIC's. This is because a narrow line width and spacing of less than 30 pm are used free from parasitics due to the four polyimide layers, each of which is as thin as 2.5 pm. Singlechip receivers fabricated using 0.3-pm-gate FET's have an integration level of 1.7 +/- 0.2 (dB/mm2) above the C band. This is three times the integration level of conventional 2-D MMlC's. In this paper a novel masterslice MMlC design appr~ach'~' employing the 3-D MMlC structure is described using our most recently fabricated devices. One of those devices - a K-band receiver integrated on 6 x 3 master-array units - is shown in Fig. 1. This approach effectively uses a ground metal that partially covers the master-array units on the surface of a wafer, creating a space wide enough for the 3-D circuits stacked above it. The simple and riskless development and short TAT with low-cost manufacturing provided by this approach make it a very powerful way to expand the GaAs and Si MMlC application market. 0-7803-3504-X/96 $5.00 0 1996 IEEE
Fig. 1 A 17-24 GHz single-chip receiver MMlC using a GaAs Masterslice with 6 x 3 array units. Nine RF components are integrated in a 1.78 x 1.78 mm area. Polyimide layers
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STRUCTURE AND FABRICATION A. Structure Figure 2 shows the basic structure of the masterslice MMIC. Many units, each of which contains transistors,
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resistors, and the lower electrodes of MIM capacitors, are repeatedly placed (nearly 6 units/mm2) on a GaAs or Si wafer to form a master array, and the entire wafer surface is passivated. On-wafer elements not selected for microwave circuit design are covered with a ground metal, GNDI. Thin polyimide layers (and an additional ground metal, GND2, as occasion demands), are stacked over the wafer and GNDl to complete the 3-D MMlC design. The upper electrodes of MIM capacitors are used for GNDl in order to maximize the space. Therefore, a space for many miniature passive circuits is created over GNDl. GNDl and the polyimide and metal layers provide passive circuits whose performance is not affected by the substrate properties.
B. Fabrication Figure 3 shows the fabrication process flow of the whole 3-D interconnection structure. First, a polyimide insulator is spin-coated and cured. The polyimide thickness is within 2% standard deviation over the 3-inch-diameter wafer, as shown in Fig. 4. Second, a gold metal layer is electroplated with sputtered seed metal and patterned in series after via-hole etching for interconnections. These processes are simply repeated until the final metal layer on the top surface of the polyimide layers has been patterned. The total polyimide thickness is 10 pm. The final (sixth) metal layer is 2-pm thick and the other metal layers (2nd to 5th) are each 1-pm thick. A key issue is how to form small vias through the 10pm-thick polyimide insulator. For this purpose, we use recently developed folded metal interconnection technology with a thick insulator (FMIT [6'). The minimum size of the via hole is only 6 pm. In FMIT, 02/He RIE is used to form viaholes through the 10-pm-thick polyimide insulator. The combination of 0, and He gas forms the holes without 152
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Fig. 5 Vias fabricated by FMIT
residue. By means of low-current side-wall electorplating, the deep vias can be formed at the same time with plain interconnections in a very simple process. Gold metal on the polyimide top surface is patterned by ion-milling with WSiN stopper metal. A mask photoresist was optimized in thickness for fine-patterning without redeposition. Figure 5 shows an example of vias fabricated by FMIT. In this case, the polyimide insulator was removed by RIE for SEM observation. 10-pm-high pillar-like vias were successsfully fabricated.
3-D MASTERSLICE MMlC DESIGN We designed and fabricated several X and K band receivers to verify the 3-0 masterslice MMlC technology. As mentioned earlier, the 17-24 GHz single-chip receiver shown in Fig. 1 is one of our most recent devices. It uses a GaAs masterslice wafer. The circuit scheme for the chip is shown in Fig. 6. Seven microwave components - three variable-gain amplifiers (VGA's), two single-mixers (MIX'S), a broadside coupler (BC), and a Wilkinson divider (WD) - are combined for frequency conversion in the area enclosed by dotted lines. In the other portion of the chip, a voltage-controlled oscillator (VCO) with a buffer amplifier (BA) are separated from the frequency converter.
A. Masterslice In the schematic in Fig. 6, the MESFET's are shown as they are in the master arrhy. A pair of 100-pm-gatewidth MESFET's are included in an array unit. Three MIM lower
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Fig. 7 Performance of the 17-24 GHz, 3-D masterslice MMlC receiver Fig. 6 Circuit schematic of the 3-D masterslice, single-chip receiver MMlC shown in Fig. 1. electrodes, four 1-kQ resistors, and two 250-C2 resistors accompany each MESFET pair. There are six array units in each of the three lines (hence 36 MESFET's are prepared on a chip) and 5042 and 100-S2 resistors in the small areas between the lines. The masterslice arrangement was designed empirically to be effective for various small-signal circuits; importance was attached to an amplifier design with this arrangement because it is the basis of other active circuits. The chip size is only 1.78 x 1.78 mm.
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B, Circuit Lavout The MESFET's and resistors not selected for circuit design are covered with the GNDl (the second metal layer). The 14 gray-colored MESFET's in Fig. 6 are unused ones. All of MIM lower electrodes, except those for series capacitance, are covered with GNDl. The multilayered polyimide area above the ground metal is as much as 80% of the array area (1.6 x 1.6 mm2), and it is effectively used for 3D passive circuit implementation. Miniature transmission lines, mainly thin-film microstrip (TFMS) lines on different layers in this case, are patterned in a meander-like configuration with a line-to-line spacing as narrow as 30 pm or less, but with negligibly small parasitics at discontinuities and couplings between adjacent lines due to the polyimide layers, each of which is as thin as 2.5 pm. Coupling at cross sections is also negligibly small due to the very narrow line widths. These features, which are maintained even at 60 GHz, make circuit layout from a schematic design very easy and accurate. The area occupied by each component is less than 0.4 mm2.
C. Performance The measured performance of the frequency converter in the receiver MMlC is shown in Fig. 7. The desired IF output power through an external IF quadrature coupler is around -15 dBm for an input RF power of -30 dBm from 17 to 24 GHz. This means a 15-dB small signal gain in the
Fig. 8 Quick prototype fabrication using a masterslice wafer. frequency range. The image-rejection ratio is 20 dB and the noise figure is around 6 dB. These values were obtained at 5 V and 50 mA. The tuning range of the VCO is more than 2 GHz. The associated output power of nearly 5 dBm and the phase noise at 1-MHz offset frequency is -80 dBclHz. An external local signal is also available when lower phase noise is required.
D. Quick Prototype Evaluation The masterslice wafer can also be employed to quickly establish critical components in advance of receiver fabrication. Prototype circuits on a master array - a threestage VGA and a VCO with buffer amplifiers - are shown in Fig. 8. These circuits were separately implemented and measured. The measured data indicates that the center frequency of the VCO tuning range should be lowered by 2
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GHz. Since only the polyimide 3-D process is necessary to complete the work, the whole development term can be shortened considerably.
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APPLICATION TO Si-MMIC GNDI, which separates the wafer and the 3-D passive circuits, enables fabrication of Si MMIC's as that of GaAs MMIC. We first evaluated the X-band amplifier shown in Fig. 9, using the 3-D masterslice MMlC technology. Two Si bipolar transistors fabricated by Super Self-Align Techn010gy[~](SSTI CIS) are cascode connected and TFMS lines above a ground metal in the middle of the polyimide layers (GND2 in Fig. 2) and thin-film striplines between GNDI and GND2 are attached to the cascode FET's for reactive impedance matching. Three 05x1 10.6-lm-emitter SSTI C's and resistors are located between the MIM lower electrodes to form an array unit, where these components are isolated from each other. The single-stage amplifier using an array unit measures only 730 x 770 km and exhibits an 8-dB gain from 7 to 10 GHz, as shown in Fig. 10. Since the measured ,,,f of the 110.6-km-emitter-width SSTIC is nearly 30 GHz, the measured amplifier performance indicates that the highest operation frequency of the 3-D Si MMIC's is one-third ,of ,,,f while that of conventional Si direct-coupled amplifier
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EFFECTIVE TATKOST REDUCTION To conclude this paper, we mention the effects the 3-0 masterslice MMlC technology has on TAT and chip cost. Figure 11 compares the turn-around-time (TAT) of the 3-D masterslice MMlC with the conventional TAT, under the condition that ready-made masterslice wafers are widely available. A one-half to one-fourth reduction is expected from the masterslice technology. The chip cost can also be reduced considerably due to the threefold integration level, much shorter TAT, and lower-skill engineering. The 3-D Si MMIC's accelerate the cost reduction of MMIC's below X band due to the low-cost, large-scale wafer process. The estimated cost of Si MMIC's is less than one-tenth that of conventional GaAs MMIC's.
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REFERENCES [ l ] T. Tokumitsu et al., "Multilayer MMlC using a 3 pm x 3layer dielectric film structure," in Proc. IEEE Intl. Microwave Symp., May 1990, pp. 831-834. [2] I. Toyoda et al., "Multilayer MMlC branch-line coupler and broadside coupler," in Proc. IEEE Intl. Microwave Symp., June 1992, pp. 79-82. [3] T. Tokumitsu et al, "Three-dimensional MMIC technology for multifunction integration and its possible application to masterslice MMIC," in Proc. IEEE Microwave and MillimeterWave Monolithic Circuits Symp., June 1996, pp. 85-88. [4] I. Toyoda et al., "Highly integrated three-dimensional MMlC single-chip receiver and transmitter," in Proc. IEEE Intl. Microwave Symp., June 1996, 1209-1212. [5]T. Tokumitsu et al., "Three-dimensional MMlC technology: Possible solution to masterslice MMIC's on GaAs and Si," IEEE Microwave and Guided Wave Letters, Vol. 5, No. 11, pp.411-413, NOV.1995. [6] M. Hirano et al., "Three-dimensional passive circuit technology for ultra-compact MMIC's," IEEE Trans. Microwave Theory Tech., Vol. 43, No.12, pp. 2845-2850, Dec. 1995. [7] H. lchino et al., "18-GHz 1/8 dynamic frequency divider using Si bipolar technologies," IEEE J. Solod State Circuits, Vol. 24, No. 6, pp. 1723-1728, Dec. 1989.
