Appliances Control Using Mobile Phone

University of Omer Al-Mukhtar College of Engineering Electrical and Electronics Engineering Department

Appliances Control Using Mobile Phone A Project Submitted in Partial Fulfillment of the Requirement for the Bachelor Degree (B.Sc.) in Electrical and Electronic Engineering

By Manhal J. Alhelaly

Supervisors Dr. Ayad A. Mousa Mr. Abdelhamid M. Raheel MSc.

June, 2010

Acknowledgment

To my supervisors: Dr. Ayad A. Mousa Mr. Abdelhamid M. Raheel You learn me how to do it, I will be forever thankful,,,

Contents Title

Page No.

Abstÿÿract

VII Chapter 1 Introduction

1.1 System Overview

2

1.2 The System Features

3

1.3 The System Description

3 Chapter 2 DTMF Detection Unit

2.1 DTMF Signaling

4

2.2 DTMF Detection

6

2.2.1 DTMF Decoder Specifications.1

6

2.2.2 DTMF Detection Methods

8

2.3 The Integrated DTMF Decoder

10

2.4 The Control Unit Interfacing

14 Chapter 3 Control Unit

3.1 Device Switching Section

16

3.2 Device Status Feedback Section

18

3.2.1 The Feedback Circuitry

18

3.2.2 Beep Tone Generator

19

3.3 Relay Drive Circuit

19

-I-

Title

Page No. Chapter 4 Overall System Design and Practical Work

4.1 System Operation

21

4.2 The System Block Diagram

22

4.3 The DTMF Detection Unit

23

4.4 The Control Unit

24

4.5 The Practical Work

27

Chapter 5 Conclusions and Future Work 5.1 Conclusions

29

5.2 Future Work

29

References

30 Appendices

A ITU-T Q-24 Recommendations B Background: Gortzel Algorithm C CM8870 Data Sheet

-II-

List of Tables Table No.

Table Title

Page No.

2.1

Requirements of DTMF specified in ITU-TQ.24

2.2

The respective DTMF data into BCD digits

12

2.3

The DM74154 decoder truth table

15

-III-

7

List of Figures

Figure No.

Title

Page No.

1.1

Home automation system

1

1.2

Applinaces control using mobile phone

2

2.1

Telephone keypad matrix

5

2.2

DTMF signal of key number“3” [697,1477] Hz

5

2.3

The DTMF detection secheme

8

2.4

Flow chart for the DTMF detector using Goertzel

11

Algorithm 2.5

The Block Diagram of CM8870

13

2.6

Block Diagram of the decoder chip 74154

14

3.1

3 state buffer symbol

16

3.2

DM74126 Connection Diagram

17

3.3

HD7474 Connection Diagram

18

3.4

HD7408 Connection Diagram

18

3.5

EN7408 Connection Diagram

19

3.6

SRD-05VDC- SL-C Connection Diagram

20

4.1

White list program (WebGate Advanced Call Manager

21

v2.66) 4.2

Home Controller Block Diagram

-IV-

22

Figure No.

Title

4.3

DTMF Detection unit construction with photograph

Page No.

23

for the practical work 4.4

Device Status check section with photograph for the

24

practical work 4.5

Tri-state buffer with LM555 monostable multivibrator with photographs for the practical work

4.6

7474 D flip-flop connection Diagram, with photograph for it in the practical work

4.7

Astable multi-vibrator with photograph for it in the practical work

25

26

27

4.8

The system case

27

4.9

The system board

28

-V-

Abbreviations used DTMF

Dual-Tone Multi Frequency

ITU-T

International Telecommunication Union – Telecommunication Standardization Sector Recommendation

DFT

Discrete Fourier Transform

FFT

Fast Fourier Transform

BCD

Binary Coded Decimal

-VI-

Abstract

In many cases it is desirable to turn on or off some appliances, such as air conditioning and heating units before arriving home, this is known as home automation systems. This project uses the Dual-Tone Multi Frequency (DTMF) technique used in touch tone telephones, to control multi electronic devices from long distances using the mobile phone. A practical application case for this system was implemented to control four electronic devices. A test to detect the DTMF signal received from different mobile phones was also carried out. The DTMF decoder was tested for accurate detection of the presence of these tones under various conditions. The automation features of this work makes it possible for homeowners to remotely control a large number of appliances, indoor and outdoor lamps and lights, landscape sprinkler timers and more using their mobile phones.

-VII-

Chapter 1

Introduction

The remote control used in home automation systems, is a wonderful feature that everyone would like to enjoy, if they were not expensive to install, maintain, and able to be used from long distance. The idea of the remotely controlled home automation systems is shown in Figure 1.1.

Figure 1.1

Home Automation system

The home automation have many features makes the homeowner remotely toggle appliances such as air conditioning and heating units, lamps or porch lights, landscape sprinkler timers, snow-melt systems, outdoor property lighting, and safety lighting. The mobile phones and Touch-Tone telephones use the Dual-Tone Multi Frequency (DTMF). That was developed initially for telephony signaling such as dialing and automatic redial. Each key-press on the phone keypad generates DTMF signal consists of two tones that must be generated simultaneously.

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Chapter 1

Introduction

1.1 System Overview Using the DTMF technology, the system in this project will control multi electronic devices from long distance using the mobile phone. This system allows the user to control and know the present state of home appliances by cell phone, it can be done by send signal over the cell phone (control phone) to other cell phone in the home (home-based phone), this cell phone is connected to an interface circuit detects the DTMF signals and give it the access to a control unit which controls the home devices and turn the power of these devices On or Off. A design of a home appliances control system using cell phone presented in this project is shown in Figure 1.2.

Home-based phone

Figure 1.2

Appliances control using mobile phone

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Control phone

Chapter 1

Introduction

1.2 The System Features 

This system can control up to 10 devices, it may be any electric or electronic appliances, and each device is given a unique code.



There is no risk for false switching, it makes accurate switching any false switching the device are not done.



This system doesn’t cost a lot of money, and it’s easy to implement.



Before changing the state of the device we can confirm the present status of the device.



The system gives an acknowledgement tone after switching on the devices to confirm the status of the devices.



Its highly secured system using the white list programs on the home-based phone to block any other call from controlling the home appliances.



This system can be controlled by multi users, this feature refer to user choice.

1.3 The System Description The Home Controller divided into two units which is, the DTMF detection unit, and the device control unit, these units consists of many sub-circuit blocks, beginning with the DTMF decoder, 4-16 line decoder/de-multiplexer, some D-flip-flops, relay driver circuits, feedback circuitry, etc.

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Chapter 2

DTMF Detection Unit DTMF detection is the main object before starting to control the appliances. In this chapter we will discuss in details the DTMF signaling and detection using several methods, and later we will show the integrated circuit we use in this project, and how to get its output on 16 different output line.

2.1 DTMF Signaling DTMF signaling, increasingly being employed worldwide with push-button telephone sets, offers a high dialing speed over the dial-pulse signaling used in conventional rotary telephone sets. In recent years, DTMF signaling also found many applications such as automatic redial, modems that use DTMF for dialing stored numbers to connect with network service providers. DTMF has also been used in interactive remote access control with computerized automatic response systems such as airline’s information systems, remote voice mailboxes, electronic banking systems, as well as many semiautomatic services via telephone networks. DTMF signaling scheme, reception, testing, and implementation requirements are defined in the International Telecommunication Union Recommendations ITU-T Q.23 and Q.24. DTMF generation is based on a 4×4 grid matrix shown in Figure 2.1. This matrix represents 16 DTMF signals including numbers 0–9, special keys * and #, and four letters A–D. The letters A–D are assigned to unique functions for special communication systems such as the military telephony systems. The DTMF signals are based on eight specific frequencies defined by two mutually exclusive groups. Each DTMF signal consists of two tones that must be generated simultaneously. One is chosen from the low-frequency group to represent the row index, and the other is chosen from the high-frequency group for the column index [3]. The implementation of a DTMF signal involves adding two finite-length digital sinusoidal sequences with the later simply generated by using look-up tables or by computing a polynomial expansion [2]. By pressing a key, for example number 3, it will

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Chapter 2

DTMF Detection Unit

generate a dual-tone consist of 697 Hz for the low group, and 1477 Hz for the high group, as shown in Figure 2.2.

Figure 2.1

Figure 2.2

Telephone keypad matrix [3]

DTMF signal of key number ”3” [697,1477] Hz

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Chapter 2

DTMF Detection Unit

A DTMF decoder must able to accurately detect the presence of these tones specified by ITU-T Q.23. The decoder must detect the DTMF signals under various conditions such as frequency offsets, power level variations, DTMF reception timing inconsistencies, etc. DTMF decoder implementation requirements are detailed in ITU-T Q.24 recommendation. For voice over IP (VoIP) applications, a challenge for DTMF signaling is to pass through the VoIP networks via speech coders and decoders. When DTMF signaling is used with VoIP networks, the DTMF signaling events can be sent in data packet types. The procedure of how to carry the DTMF signaling and other telephony events in real-time transport protocol (RTP) packet is defined by Internet engineering task force RFC2833 specification [3].

2.2 DTMF Detection This section introduces methods for detecting DTMF tones used in communication networks. The correct detection of a DTMF digit requires both a valid tone pair and the correct timing intervals. The DTMF signaling may be used to set up a call and to control functions, for that it is necessary to detect DTMF signal in the presence of speech [3]. Since the signaling frequencies are all located in the frequency band used for speech transmission, this is an in-band system. Interfacing with the analog input and output devices is provided by codec (coder/decoder) chips, or A/D and D/A converters. Although a number of chips with analog circuitry are available for the generation and decoding of DTMF signals in a single channel, these functions can also be implemented digitally on DSP chips [2].

2.2.1 DTMF Decoder Specifications The implementation of DTMF decoder involves the detection of the DTMF tones, and determination of the correct silence between the tones. In addition, it is necessary to perform additional assessments to ensure that the decoder can accurately distinguish DTMF signals in the presence of speech.

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Chapter 2

DTMF Detection Unit

For North America, DTMF decoders are required to detect frequencies with a tolerance of ±1.5%. The frequencies that are offset by ±3.5% or greater must not be recognized as DTMF signals. For Japan, the detection of frequencies has a tolerance of ±1.8 %, and the tone offset is limited to ±3.0 %. The ITU-T requirements for North America are listed in the Table 2.1. Another requirement is the ability to detect DTMF signals when two tones are received at different levels. This level difference is called twist. The high-frequency tone may be received at a lower level than the low-frequency tone due to the magnitude response of the communication channel, and this situation is described as a forward (or standard) twist. Reverse twist occurs when the received low-frequency tone has lower level than the high-frequency tone. The final requirement is that the receiver must avoid incorrectly identifying the speech signal as valid DTMF tones. This is referred as talk-off performance [3].

Table 2.1

Signal frequencies

Frequency tolerance

Signal duration

Twist

Signal power

Interference by echoes

Requirements of DTMF specified in ITU-T Q.24

Low group

697, 770, 852, 941 Hz

High group

1209, 1336, 1477, 1633 Hz

Operation

≤ 1.5%

Nonoperation

≥ 3.5%

Operation

40 ms min

Nonoperation

23 ms max

Forward

8 dB max

Reverse

4 dB max

Operation

0 to −25 dBm

Nonoperation

−55 dBm max

Echoes

Should tolerate echoes delayed up to 20 ms and at least 10 dB down

-7-

Chapter 2

DTMF Detection Unit

2.2.2 DTMF Detection Methods The scheme used to identify the two frequencies associated with the button that has been pressed is shown in Figure 2.3. Here, the two tones are first separated by a low pass and a high pass filter. The passband cutoff frequency of the low pass filter is slightly above 100 Hz, whereas that of the high pass filter is slightly below 1200 Hz. The output of each filter is next converted into a square wave by a limiter and then processed by a bank of bandpass filters with narrow passbands. The four bandpass filters in the low-frequency channel have center frequencies at 697 Hz, 770 Hz, 852 Hz, and 941 Hz. The four band pass filters in the high-frequency channel have center frequencies at 1209 Hz, 1336 Hz, 1477 Hz, and 1633 Hz. The detector following each band pass filter develops the necessary dc switching signal if its input voltage is above a certain threshold.

Bandpass Filter 1#

697 Hz

Bandpass Filter 2#

770 Hz

Bandpass Filter 3#

852 Hz

Low group tones

Lowpass Filter

Limiter

Bandpass Filter 4#

941 Hz

Highpass Filter

Limiter

Bandpass Filter 5#

1209 Hz

Bandpass Filter 6#

1336 Hz

Bandpass Filter 7#

1477 Hz

Bandpass Filter 8#

1336 Hz

Figure 2.3

High group tones

The DTMF detection secheme [2] -8-

Chapter 2

DTMF Detection Unit

The entire signal processing functions described above are usually implemented in practice in the analog domain. However, increasingly, these functions are being implemented using digital techniques. Digital techniques surpass analog equivalents in performance, since it provides better precision, stability, versatility, and reprogrammability to meet other tone standards. The DTMF digital decoder computes the Discrete Fourier Transform (DFT) samples closest in frequency to the eight DTMF fundamental tones. The DFT computation scheme employed is a slightly modified version of Goretzel’s Algorithm. The flow chart of DTMF detection using the modified Goertzel’s Algorithm is illustrated in Figure 2.4. Six tests are followed to determine if a valid DTMF digit has been detected [2]. Magnitude test: According to ITU Q.24, the maximum signal level transmit to the public network shall not exceed −9 dBm. This limits an average voice range of −35 dBm for a very weak long-distance call to −10 dBm for a local call. A DTMF receiver is expected to operate at an average range of −29 to +1 dBm. Thus, the largest magnitude in each band must be greater than a threshold of −29 dBm; otherwise, the DTMF signal should not be detected. Twist test: The tones may be attenuated according to the telephone system’s gains at the tonal frequencies. Therefore, we do not expect the received tones to have same amplitude, even though they may be transmitted with the same strength. Twist is defined as the difference, in decibels, between the low and high-frequency tone levels. Frequency-offset test: This test prevents some broadband signals from being detected as DTMF tones. If the effective DTMF tones are present, the power levels at those two frequencies should be much higher than the power levels at the other frequencies. To perform this test, the largest magnitude in each group is compared to the magnitudes of other frequencies in that group. The difference must be greater than the predetermined threshold in each group. Total-energy test: Similar to the frequency-offset test, the goal of total-energy test is to reject some broadband signals to further improve the robustness of a DTMF decoder. To perform this test, three different constants c1, c2, and c3 are used. The energy of the -9-

Chapter 2

DTMF Detection Unit

detected tone in the low-frequency group is weighted by c1, the energy of the detected tone in the high-frequency group is weighted by c2, and the sum of the two energies is weighted by c3. Each of these terms must be greater than the summation of the energy from the rest of the filter outputs. Second harmonic test: The objective of this test is to reject speech that has harmonics close to the DTMF frequencies so that they might be falsely detected as DTMF tones. Since DTMF tones are pure sinusoids, they contain very little second harmonic energy. Speech, on the other hand, contains a significant amount of second harmonic. To test the level of second harmonic, the detector must evaluate the second harmonic frequencies of all eight DTMF tones. These second harmonic frequencies (1394, 1540, 1704, 1882, 2418, 2672, 2954, and 3266 Hz) can also be detected using the Goertzel algorithm. Digit decoder: Finally, if all five tests are passed, the tone pair is decoded and mapped to one of the 16 keys on a telephone touch-tone keypad [3]. Goertzel’s algorithm is very efficient for DTMF signal detection. However, some realworld applications may already have other DSP modules that can be used for DTMF detection. For example, some noise reduction applications use Fast Fourier Transform (FFT) algorithm to analyze the spectrum of noise, and some speech-coding algorithms use the linear prediction coding (LPC). In these cases, the FFT or the LPC coefficients can be used for DTMF detection.

2.3 The integrated DTMF Decoder The integrated DTMF decoder is the device that receives the incoming DTMF data and converts it into a respective 4-bit binary coded decimal (BCD) numbers as shown in the Table 2.2. The CM8870 is a full DTMF receiver that integrates both band split filter and decoder functions into a single 18-pin DIP. Its filter section uses switched capacitor technology for both the high and low group filters and for dial tone rejection. Its decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit BCD code. -10-

Chapter 2

DTMF Detection Unit

Initialization

Magnitude > threshold

N

Y Twist normal?

Get 8 kHz input sample

N

Y Does frequency offset pass?

N

Y Total energy test pass?

Compute the Goertzel Algorithm filter for the eight frequencies

N

Y Second harmonic signal too strong?

Y

N Output digit

Figure 2.4

Flow chart for the DTMF detector using Goertzel Algorithm [3]

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Chapter 2

DTMF Detection Unit

Table 2.2

The respective DTMF data into BCD digits [4]

Flow

Fhigh

Key

Q4

Q3

Q2

Q1

697 697 697 770 770 770 852 852 852 941 941 941

1209 1336 1477 1209 1336 1477 1209 1336 1477 1209 1336 1477

1 2 3 4 5 6 7 8 9 0 * #

0 0 0 0 0 0 0 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1

0 1 1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0 1 0

697 770 852 941

1633 1633 1633 1633

A B C D

1 1 1 0

1 1 1 0

0 1 1 0

1 0 1 0

External component count is minimized by provision of an on-chip differential input amplifier, clock generator, and latched tri-state interface bus. Minimal external components required include a low-cost 3.579545 MHz crystal, a timing resistor, and a timing capacitor. It can also inhibit the decoding of fourth column digits. The Block Diagram of CM8870 shown in Figure 2.5 [4]. The CM8870’s internal architecture consists of a band split filter section which separates the high and low tones of the received pair, followed by a digital decode (counting) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus. The filter section also incorporates notches at 350 Hz and 440 Hz which provides excellent dial tone rejection. Each filter output is followed by a single order switched capacitor section which smoothes the signals prior to limiting. Signal limiting is performed by high gain comparators [4].

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Chapter 2

DTMF Detection Unit

Figure 2.5

The Block Diagram of CM8870 [4]

The CM8870 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while providing tolerance to small frequency variations. The averaging algorithm has been developed to ensure an optimum combination of immunity to “talk-off” and tolerance to the presence of interfering signals and noise. When the detector recognizes the simultaneous presence of two valid tones known as “signal condition”, it raises the Early Steering Flag (ESt) Any subsequent loss of signal condition will cause ESt to fall. Before the registration of a decoded tone pair, the receiver checks for a valid signal duration referred to as “character recognition-condition”. This check is performed by an external RC time constant driven by ESt. Logic high on ESt causes the voltage on the capacitor VC to rise as the capacitor discharges. Providing signal condition is maintained (ESt remains high) for the validation period called Guard time period tGTP, VC reaches the threshold voltage VTSt of the steering logic to register the tone pair, thus latching its corresponding 4-bit code into the output latch.

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Chapter 2

DTMF Detection Unit

At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the Three-State Control Input TOE to logic high. The steering circuit works in reverse to validate the inter digit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions too short to be considered a valid pause. This capability together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements [4].

2.4 The Control Unit Interfacing To have the BCD output on 16 different lines, we feed the DTMF decoder output to a 4-16 line decoder like IC74154. This IC takes the BCD number and decodes. According to that BCD number it selects the active low output line from 1 to 16 which is decimal equivalent of the BCD number present at its input pins. To get a logical high output, the output of the IC74154 needs to get inverted. This inversion is carried out by an inverter, like the hex inverter IC 7404. This IC inverts the data on its input terminal and gives inverted output. The DM74154 integrated circuit is a 4-16 line decoder; it takes the 4 line BCD input and selects respective output, one among the 16 output lines. It is active low output IC so when any output line is selected it is indicated by an active low signal; the rest of the output lines will remain active high, when both the strobe inputs, G1 and G2, are low. The de-multiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. These de-multiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design; the multiplexer/de-multiplexer diagram in Figure 2.6, and the truth table for this de-multiplexer shown in Table 2.3 [4].

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Chapter 2

DTMF Detection Unit

Figure 2.6

Block diagram of the decoder chip 74154 [4]

Table 2.3

The DM74154 decoder truth table [4]

L – Logic low

H – Logic High

X – No change

G1

G2

D

C

B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

L

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

L

H

L

L

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

L

L

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

L

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

-15-

Chapter 3

Control Unit The Device Control unit designed for this project consists of device switching section, device status feedback section, and relay driver circuit. In this chapter we will show the main components of each section of this unit.

3.1 Device Switching Section The main object of the device switching section, is giving access to the relay drive circuit when needed to turn On/Off the controlled devices. The Device Switching section consists of a tri-state buffer and flip-flops. The tristate buffer contains independent gates each of which performs a buffer function. The outputs have the 3-STATE feature. When control signal is at high state, the outputs are nothing but the data present at its input terminals. When control signal is at low state, the outputs are held at high impedance state, so no output will be available at the output terminal. Figure 3.1 illustrate the 3-state feature.

Input

Control signal

Output Figure 3.1

3 state buffer symbol

The tri-state buffer will lead the device control unit to operate in two different ways. First for device status check before switching On/Off any device (the tri-state buffer is disable), to avoid any confusion about the device present status of the output, this can be done by fed the BCD decoder inverted output and the output line of the respective device to the device status feedback section. The second way that the device control unit operates -16-

Chapter 3

Control Unit

is after making confirmation of current status of the device to alter the status of that device, now we have to enable the tri-state buffer by making the control input high. That make the output of the tri state buffer be the signal at its input terminal. Now the device code of the chosen relay whose status is to be altered is again pressed. The DM74126 IC contains four independent gates each of which performs a noninverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard output with additional drive capability to permit the driving of bus lines without external resistors, when disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Figure 3.2 show the connection diagram of this IC [4].

Figure 3.2

DM74126 Connection Diagram [4]

The output of the tri-state buffer is latched by using a D flip-flop. This D flip flop is used in the toggle mode. For each positive going edge of the clock a pulse will trigger the flip flop. The HD7474 is a dual positive edge-triggered D-type flip-flop. This IC consists of two D flip-flops. These flip-flops are used to latch the data that present at its input terminal. Each flip-flop has one data, one clock, one clear, and one preset input terminals. Figure 3.3 show its connection diagram [4].

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Chapter 3

Control Unit

Figure 3.3

HD7474 Connection Diagram [4]

3.2 Device Status Feedback Section Before and after changing the present status of the device On/Off, it’s important to check the status of the device. The control unit will give a feedback tone after switching On any device, this help us to check the device status. 3.2.1 The Feedback Circuitry This status feedback circuitry, utilizes a dual input AND gate, When the both inputs are high that indicates that the device is switched ON, then the output of the AND gate goes logic high state. This output is fed to the beep generator. When we press the key the feedback tone is heard. This feedback tone is heard only when the device is switched ON. After switching OFF the device, this tone is not heard. The HD7408 contains four independent gates each of which performs the logic AND function. The Connection diagram of this IC is shown in figure 3.4.

Figure 3.4

HD7408 Connection Diagram [4] -18-

Chapter 3

Control Unit

3.2.2 Beep Tone Generator The beep tone generator section produces a beep tone of audible frequency. This unit is constructed using a 555 timer chip. Here it is wired as an astable multi-vibrator with a few external components like resister and capacitor, required along with the timer 555 chip set. This frequency comes in the audible range between 40 to 650 Hz. It should be less than 650 Hz otherwise it will mix up with the DTMF tone. The EN555 timer chip connection diagram is shown in Figure 3.5.

Figure 3.5

EN7408 Connection Diagram [4]

We will discuss later the working of the timer 555 chip as an astable multi-vibrator.

3.3 Relay Drive Circuit In order to switch the appliances On or Off, small board type relays were used. Since the output of the D flip flop is normally +5 V or it is the voltage of logic high state, we cannot use this output to run the device or appliances. Therefore here we use relays which can handle a high voltage of 230 V or more, and a high current in the rate of 10 A to energize the electromagnetic coil of the relays +5 V is sufficient. Here we use four SRD-05VDC- SL-C relays to switch On/Off four different devices. The connection diagram of this relay is shown in the Figure 3.6.

-19-

Chapter 3

Control Unit

1

Figure 3.6

SRD-05VDC- SL-C Connection Diagram

And to protect the relay coils from damage we use a single IN4007 diode, connected in reverse between the coil terminals.

-20-

Chapter 4

Overall System Design and Practical Work A practical work has been done to control four different home appliances; in this chapter we will show the overall system design and each sub-circuit block in this system.

4.1 System operation A Design of a home appliances control system using cell phone presented in our project is referring to Figure 1.2 as a block diagram, let's beginning with the two cell phones one remote cell phone which called Control phone, this phone control the system after a call is made by only press the buttons that generate the DTMF signal; and the other home cell phone which called home-based phone because it’s based in the home with the home controller board; the home controller is divided into two parts, DTMF detection unit, and the control unit. Once the user call to the home-based phone, in order to control the home appliances, the home-based phone answer the call automatically if the user is the one who recorded in the white list program, that we use for the system security. The white list program is shown in Figure 4.1.

Figure 4.1

White list program (WebGate Advanced Call Manager v2.66)

After that the user can accesses to the system, check the current status of the devices, and change the state of any device (On/Off).

-21-

Chapter 4

Overall System Design and Practical work

4.2 The System block diagram

Figure 4.2

Home Controller Block Diagram -- DTMF Detection Unit -- Control Unit -- 1st Status Feedback Section -- 2nd Status Feedback Section -22-

Chapter 4


4.3 The DTMF Detection unit As discussed in Chapter 2, the DTMF detection unit constructs of DTMF decoder, 4-16 line Decoder/de-multiplexer, and inverter to invert the output of the 4-16 line Decoder/de-multiplexer. In this project we use the CM8870 DTMF decoder for allowed the system to decode the DTMF signals sent by the user through home-based phone in to BCD digits, these digital codes fed to the input of the 4-16 line decoder/de-multiplexer input which in turns selects respective output, one among the 16 output lines, It is active low output IC so its needs to get inverted to get a logical high output. This inversion is carried out by hex inverter IC 7404. The DTMF detection unit is connected as shown in Figure 4.3. The internal clock circuit of the DTMF decoder is completed with the addition of a standard television color burst crystal or ceramic resonator having a resonant frequency of 3.579545 MHz.

OP-amplifier input Steering circuit

Figure 4.3

DTMF Detection unit construction with photograph for the practical work

-23-

Chapter 4


The TOE (Tri-State output enable) pin in the DTMF decoder is an active low input used to disable/enable the output latch. We connect it to VDD in order to have the output latch enabled at all times. The INH pin Inhibits detection of tones represents keys A, B, C, and D, and giving the PD pin Logic high powers down the device and inhibits the oscillator, for that these two pins are connected to the ground. While the gain selector GS pin Gives access to output of front-end differential amplifier (shown in Figure 2.5) for connection of feedback resistor.

4.4 The Control Unit The control unit consists of device status check section, device switching section, device status feedback section, and relay driver circuit. Before switching On/Off any device, to avoid any confusion about the device present status of the output, we can check the status of any device by fed the BCD decoder inverted output (the button that the user pressed) and the output line of the respective device (from the relay circuit) to independent block of And gates, where the output of the And gates is connected to the beep tone generator (B), that generates a beep if the respective device in the ON state. Figure 4.4 show the device status check section. From the BCD decoder output

From the respective device relay

Figure 4.4

Device Status check section with photograph for the practical work

In this project we use HD7408 IC which provides quadruple two input positive And Gates. -24-

Chapter 4


After checking the device status, the tri-state buffer mode can be changed by making the control input high. This is done by pressing the “0” key. When this key is pressed the output of the 4-16 line decoder goes low. This gives a triggering pulse to the monostable multi-vibrator which is built around the LM555. This will keep the output high for about 5 seconds. In this time interval the output of the tri state buffer will be the signal at its input terminal. Now the device code of the chosen relay (1, 2, 3 or 4) whose status is to be altered is again pressed. The output of the tri-state buffer is latched by using a D flipflop. After a period of 5 s the output of the LM555 monostable multi-vibrator goes low and puts the tri state buffer in the high impedance state. Therefore to change the status of any other device to be done we must press again “0” key to make the tri-state buffer act as input–output state and the respective code of the device is pressed. Figure 4.5 show the Tri-state buffer with the LM555 monostable multi-vibrator circuit.

From the BCD decoder output

To the D Flip-Flops

Figure 4.5

Tri-state buffer with LM555 monostable multi-vibrator with photographs for the practical work

-25-

Chapter 4


We use the timer LM555 for monostable operation; in this mode of operation, the timer functions as a one-shot. The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a positive trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. The voltage across the capacitor then increases exponentially for a period of time = 1.1 R C (we make it 5 seconds), at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. During the timing cycle when the output is high, the further application of a trigger pulse will not affect the circuit so long as the trigger input is returned low. The output of the tri-state buffer is latched by using a D flip-flop. This D flip-flop is used in the toggle mode. For each positive going edge of the clock a pulse will trigger the flip flop. As shown in Figure 4.6, the output of the tri-state buffer is connected to the clock input, and the inverted output connected to the D input, this will make the D flip-flop invert its output each time a trigger pulse applied from the tri-state buffer. The main reason to use the D flip-flop is to keep the status of the tri-state buffer output after it disabled.

Figure 4.6

7474 D flip-flop connection Diagram, with photograph for it in the practical work

-26-

Chapter 4


The beep tone generator constructed using a 555 timer chip wired as an astable multi-vibrator with a few external components, required along with the timer 555 chip set. The connection of the astable multi-vibrator is shown in Figure 4.7.

And gates block output

5v speaker

Figure 4.7

Astable multi-vibrator with photograph for it in the practical work

4.5 The Practical Work This system has been implemented practically as shown in the Figures 4.8, 4.9.

Figure 4.8 The system case

-27-

Chapter 4


Figure 4.9 The system board

-28-

Chapter 5

Conclusions and Future Work

5.1 Conclusions During the realization of the presented project the following points can be depicted: 

It is simple to control the operation of any where appliances by exploiting the existing mobile network, i.e. it’s not necessary to install a specific network.



Any type of mobiles can do the job.



The control circuit is reliable and simple to build.



The system is secure, by black listing all the call number except that of the specific users (installed in the white list).



The system can let the user know the status of the appliances, before and after the switching.



The system is implemented practically and the expected results are obtained.



Some practical problems are encountered during the realization of the practical implementation and are solved using the substitution component.

5.2 Future Work In this system we did not use any applications on the control mobile, so for a future work it will be useful to develop programs for the mobile devices to give more control options and security control. As a future work in the field of the presented project, we suggest to develop the system using PLCs or Microcontrollers instead of the control unit, to give more reliability and control options, as temperature control, security and more computational work so the system can do more than just turn On/Off the devices.

- 92 -

References

[1] Fathia H. A. Salem, A Design of a Home Appliances Control System using Cell phone & J2ME, A Thesis Submitted in Partial Fulfillment of the Requirement for the Degree of Master of Science in Electrical and Electronic Engineering, University of Garyounis, Benghazi-Libya, 2008.

[2] Sanjit K. Mitra, Digital Signal Processing, Second Edition, McGraw-Hill, University of California, International Edition, 2002.

[3] Sen M Kuo, Bob H Lee, Wenshun Tian, Real-Time Digital Signal Processing Implementations and Applications, Second Edition, John Wiley & Sons, Ltd, 2006.

[4] www.datasheetcatalog.com

[5] Gunter Schmer, DTMF Tone Generation and Detection: An Implementation Using the TMS320C54x, Application Report, Texas Instrument, May 2000

-30-

Appendices

Appendix A ITU-T Q.24 Recommendations MULTIFREQUENCY PUSH-BUTTON SIGNAL RECEPTION

1 Introduction Characteristics of multi-frequency push-button (MFPB) telephone sets using voice frequency signals are included in Recommendation Q.23. This Recommendation Q.24 is intended primarily for application in local exchanges for the reception of MFPB signals. Other MFPB signal receiving applications, such as transit exchanges, would need to take into account the effects of transmission impairments, such as signal clipping, that could be introduced in long distance telephone networks. Since technical factors, such as transmission loss, vary among national networks, varying national standards exist. Varying standards may also exist, for example, to incorporate differences between local and transit exchange applications. This Recommendation is not intended to supersede existing national standards nor is it intended to imply that Administrations should modify those standards.

2 Technical parameters 2.1 General The technical parameters identified herein are fundamental to the MFPB receiving function and reasons are given for the importance of each parameter. The parameters require operational values to be specified for compatibility with the MFPB sending equipment (Recommendation Q.23) and the network environment in which the receiving equipment must function. Annex A contains a Table showing values for some of these parameters that have been adopted by various Administrations and RPOAs. In addition to the fundamental parameters covered by this Recommendation, Administrations should consider whether other parameters need specification to account for operating conditions found in their networks.

2.2 Signal frequencies Each signal consists of two frequencies taken from two mutually exclusive frequency groups (a high group and a low group) of four frequencies each, as specified in Recommendation Q.23. These frequencies and their allocation to form the various digits and symbols of the push-button signaling code are defined in Recommendation Q.23. The exchange shall provide a check for the simultaneous presence of one and only one frequency from the high group and one and only one from the low group.

2.3 Frequency tolerances The exchange should respond to signals whose frequencies are within the tolerances for MFPB sending. Somewhat wider tolerances may be appropriate, for example to cater for transmission impairments encountered in subscriber cables or FDM transmission facilities. However, wider limits may increase susceptibility to noise and digit simulation by speech.

2.4 Power levels The exchange should provide proper reception of signals whose power levels are determined by the amplitude of the sending equipment and loss that may be introduced by the subscriber cables or other network elements. The sending amplitude and transmission attenuation may be different for different frequencies. The reception characteristics may take advantage of a limitation, if specified, on the maximum difference in power level between the two received frequencies forming a valid signal to facilitate improved overall performance.

2.5 Signal reception timing The exchange should recognize signals whose duration exceeds the minimum expected value from subscribers. To guard against false signal indications the exchange should not respond to signals whose duration is less than a specified maximum value. Similarly, pause intervals greater than a specified minimum value should be recognized by the exchange. To minimize erroneous double-registration of a signal if reception is interrupted by a short break in transmission or by a noise pulse, interruptions shorter than a specified maximum value must not be recognized. The maximum rate at which signals can be received (signaling velocity)

may be related to the above minimum values. All of these values may also be determined by subscriber feature requirements.

2.6 Signal simulation by speech

Because telephone set speech transmitters are normally connected in the circuit during the push-button dialing interval, it is necessary for the exchange to properly receive valid MFPB signals in the presence of voice or other disturbances. The nature of such disturbances may vary from one geographical area to another. The number of calls affected by signal simulation should not significantly degrade the overall telephone network performance experienced by subscribers. Since actual immunity to digit simulation may be difficult to measure, a test environment using recorded speech, music, and other voice frequency sounds may be utilized to verify design performance.

2.7 Interference by dial tone

MFPB reception should not be adversely affected while dial tone is being applied. Characteristics of dial tone such as frequencies, power levels and spurious components are covered in Recommendation Q.35. These characteristics are specified to minimize the interference between the dial tone sending and the MFPB receiving functions. These functions are normally provided by closely related exchange equipment which must be designed to function properly over the entire range of signal characteristics and transmission impairments to be encountered.

2.8 Interference by echos

MFPB signal reception from extended subscriber lines having long 4-wire transmission sections must discriminate between a true signal condition and an echo condition which may persist for a number of milliseconds. Failure to provide such discrimination could result in signal reception errors, for example due to a reduction of the detected pause duration.

Administrations having such extended subscriber lines with MFPB signalling should therefore specify the echo conditions under which the MFPB signalling function must operate.

2.9 Noise immunity

Noise sources such as power lines, electric railways and telecommunication circuits may induce electrical disturbances with various characteristics into MFPB signaling paths. These disturbances may cause MFPB signals to be missed, split (double signal registration) or cause signal simulation. The distortion products produced by the MFPB signaling source should also be included in the noise environment. A realistic noise environment specification and facilities for testing MFPB reception under the specified conditions, e.g., using recorded test tapes, are important to ensure that performance standards will be met under actual service conditions.

Appendix B Background: Goertzel Algorithm

Appendix C CM8870 Data Sheet

CM8870/70C

CALIFORNIA MICRO DEVICES

CMOS Integrated DTMF Receiver Features

Applications

• Full DTMF receiver

• PABX

• Less than 35mW power consumption

• Central office

• Industrial temperature range

• Mobile radio

• Uses quartz crystal or ceramic resonators

• Remote control

• Adjustable acquisition and release times

• Remote data entry

• 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin PLCC

• Call limiting

• CM8870C

• Paging systems

—

Power down mode

—

Inhibit mode

—

Buffered OSC3 output (PLCC package only)

• Telephone answering systems

• CM8870C is fully compatible with CM8870 for 18-pin devices by grounding pins 5 and 6

Product Description The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an external component.

+##'

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1

CM8870/70C

CALIFORNIA MICRO DEVICES Absolute Maximum Ratings: (Note 1)

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating.

ABSOLUTE MAXIMUM RATINGS Parameter

Symbol

Value

Power Supply Voltage (VDDV SS)

VDD

6.0V Max

Voltage on any Pin

Vdc

Current on any Pin

ID D

VSS-0.3V to VDD+0.3V 10mA Max

Operating Temperature

TA

-40°C to +85°C

Storage Temperature

TS

-65°C to +150°C

Notes: 1. Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied.

DC Characteristics: All voltages referenced to VSS, VDD = 5.0V ± 5%, TA = -40°C to +85°C unless otherwise noted. DC CHARACTE RISTICS Symbol Min Typ

Parameter Operating Supply Voltage

V DD

Operating Supply Current

4.75

I DD

Standby Supply Current

3.0

I DDQ

Power Consumption

PO

15

Low Level Input Voltage

V IL

High Level Input Voltage

V IH I I H/ L I L

0.1

I so

6.5

Input Impedance, (IN+, IN-)

R IN

8 2.2

Steering Threshold Voltage

V Tst

Low Level Output Voltage

V OL

Units

5.25

V

7.0

mA

25

µA

PD =VDD

35

mW

f=3.579 MHz; VDD=5.0V

1.5

V

VDD=5.0V

V

VDD=5.0V

µA

VIN = VSS = VDD (Note 1)

µA

TOE=0V, VDD=5.0V

MΩ

@ 1K H z

3.5

Pull Up (Source) Current on TOE

Input Leakage Current

Max

20

10

Test Conditions

2.5

V

VDD = 5.0V

0.03

V

VDD = 5.0V, No Load

High Level Output Voltage

V OH

4.97

V

VDD = 5.0V, No Load

Output Low (Sink) Current

I OL

1.0

2.5

mA

VOUT = 0.4V

Output High (Source) Current

I OH

0.4

0.8

mA

VOUT = 4.6V

V R EF

2.4

V

VDD = 5.0V, No Load

Output Voltage Output Resistance

VREF

2.7 10

R OR

ΚΩ

Operating Characteristics: All voltages referenced to VSS, VDD = 5.0V ± 5%, TA = -40°C to +85°C unless otherwise noted. Gain Setting Amplifier

OPERATING CHARACTERISTICS Parameter

Symbol

Input Leakage Current

IIN

Input Resistance

R IN

Input Offset Voltage

V OS

Min

Typ

Max ±100

10

Units

Test Conditions

nA

V S S < V IN < V D D

MΩ ±25

mV

Power Supply Rejection

PSRR

50

dB

1KHz (Note 12)

Common Mode Rejection

CMR R

40

dB

-3.0V < VIN < 3.0V

D C Open Loop Voltage Gain

A V OL

32

dB

Open Loop Unity Gain Bandwidth

fc

0.3

MHz

Output Voltage Swing

VO

4.0

VP-P

Maximum Capacitive Load (GS)

CL

10 0

pF

Maximum Resistive Load (GS)

RL

50

KΩ

Common Mode Range (No Load)

Vcm

2.5

VP-P

RL ≥ 100KW to VSS

N o L o ad

©2000 California Micro Devices Corp. All rights reserved.

2


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CM8870/70C


AC Characteristics: All voltages referenced to VSS, VDD=5.0V ±5%, TA=-40°C to +85°C, fCLK=3.579545 MHz using test circuit (Fig. 1) unless otherwise noted.

AC CHARACTERISTICS Parameter

Symbol

Max

Units

-29

+1

dBm

27.5

869

mVRMS

Positive Twist Accept

10

dB

Negative Twist Accept

10

dB

1.5%±2Hz

Nom.

2,3,5,8,10

Nom.

2,3,5

Valid Input Signal Levels (each tone of composite signal)

Min

Typ

Freq. D eviation Accept Limit Freq. D eviation Reject Limit

±3.5%

Notes 1,2,3,4,5,8 2,3,4,8

Third Tone Tolerance

-16

dB

2,3,4,5,8,9,13,14

Noise Tolerance

-12

dB

2,3,4,5,6,8,9

D ial Tone Tolerance

+22

dB

2,3,4,5,7,8,9 Refer to Timing D iagram

Tone Present D etection Time

t DP

5

8

14

mS

Tone Absent D etection Time

t DA

0.5

3

8.5

mS

Min Tone D uration Accept

t R EC

40

mS

Max Tone D uration Reject

t R EC

20

mS

Min. Interdigit Pause Accept

t ID

Max. Interdigit Pause Reject

t DO

Propagation D elay (St to Q)

t PQ

6

11

µS

Propagation D elay (St to StD )

t PSt D

9

16

µS

Output D ata Set Up (Q to StD )

t QSt D

3.4

µS

Enable

t PTE

50

nS

D isable

t PTD

300

nS

Propagation D elay (TOE to Q) Crystal/Clock Frequency Clock Output (OSC 2)

f CL K Capacitive L o ad

40 20

3.5759

µS

3.5795

C LO

Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40mS. Tone pause = 40 mS. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. Bandwidth limited (0 to 3 KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350 Hz and 440 Hz) ±2%. 8. For an error rate of better than 1 in 10,000

9. 10. 11. 12. 13. 14.

mS

3.5831

MHz

30

pF

(User Adjustable) Times shown are obtained with circuit in Fig. 1)

TOE = VDD

R L = 10 K Ω CL = 50pF

Referenced to lowest level frequency component in DTMF signal. Minimum signal acceptance level is measured with specified maximum frequency deviation. Input pins defined as IN+, IN-, and TOE. External voltage source used to bias VREF. This parameter also applies to a third tone injected onto the power supply. Referenced to Figure 1. Input DTMF tone level at -28 dBm.



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CM8870/70C


Explanation of Events A) Tone bursts detected, tone duration invalid, outputs not updated. B) Tone #n detected, tone duration valid, tone decoded and latched in outputs. C) End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone. D) Outputs switched to high impedance state. E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). F) Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched. G) End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone. Explanation of Symbols VIN ESt St/GT

DTMF composite input signal. Early Steering Output. Indicates detection of valid tone frequencies. Steering input/guard time output. Drives external RC timing circuit.

Q1-Q4 4-bit decoded tone output. StD Delayed Steering Output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid signal. TOE Tone Output Enable (input). A low level shifts Q1-Q4 to its high impedance state. tREC Maximum DTMF signal duration not detected as valid. tREC Minimum DTMF signal duration required for valid recognition. tID Minimum time between valid DTMF signals. tDO Maximum allowable drop-out during valid DTMF signal. tDP Time to detect the presence of valid DTMF signals. tDA Time to detect the absence of valid DTMF signals. tGTP Guard time, tone present. tGTA Guard time, tone absent.


4


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CM8870/70C

CALIFORNIA MICRO DEVICES Functional Description The CAMD CM8870/70C DTMF Integrated Receiver provides the design engineer with not only low power consumption, but high performance in a small 18-pin DIP, SOIC, or 20-pin PLCC package configuration. The CM8870/70C’s internal architecture consists of a bandsplit filter section which separates the high and low tones of the received pair, followed by a digital decode (counting) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus.

Filter Section Separation of the low-group and high-group tones is achieved by applying the dual-tone signal to the inputs of two 9th-order switched capacitor bandpass filters. The bandwidths of these filters correspond to the bands enclosing the low-group and high-group tones (See Figure 3). The filter section also incorporates notches at 350 Hz and 440 Hz which provides excellent dial tone rejection. Each filter output is followed by a single order switched capacitor section which smooths the signals prior to limiting. Signal limiting is performed by highgain comparators. These comparators are provided with a hysteresis to prevent detection of unwanted low-level signals and noise. The outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.

Decoder Section The CM8870/70C decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while providing tolerance to small frequency variations. The averaging algorithm has been developed to ensure an optimum combination of immunity to “talk-off” and tolerance to the presence of interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as “signal condition”), it raises the “Early Steering” flag (ESt). Any subsequent loss of signal condition will cause ESt to fall.

Steering Circuit Before the registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as “characterrecognition-condition”). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (See Figure 4) to rise as the capacitor discharges. Providing signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (See Figure 2) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop outs) too short to be

considered a valid pause. This capability together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

Guard Time Adjustment In situations which do not require independent selection of receive and pause, the simple steering circuit of Figure 4 is applicable. Component values are chosen according to the following formula: tREC = tDP + tGTP tGTP » 0.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40 milliseconds would be 300K. A typical circuit using this steering configuration is shown in Figure 1. The timing requirements for most telecommunication applications are satisfied with this circuit. Different steering arrangements may be used to select independently the guardtimes for tone-present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. Design information for guard time adjustment is shown in Figure 5.

Input Configuration The input arrangement of the CM8870/70C provides a differential input operational amplifier as well as a bias source (VREF) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 1, with the op-amp connected for unity gain and VREF biasing the input at ½ VDD. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5.

Clock Circuit The internal clock circuit is completed with the addition of a standard television color burst crystal or ceramic resonator having a resonant frequency of 3.579545 MHz. The CM8870C in a PLCC package has a buffered oscillator output (OSC3) that can be used to drive clock inputs of other devices such as a microprocessor or other CM887X’s as shown in Figure 7. Multiple CM8870/70Cs can be connected as shown in figure 8 such that only one crystal or resonator is required.



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CM8870/70C

CALIFORNIA MICRO DEVICES Pin Function Table PIN FUNCTION

N am e

D escription

IN +

Non-inverting Input

IN -

I n v e rti n g I n p u t

Connection to the front-end differential amplifier

VREF

Gives access to output of front-end differential amplifier for connection of feedback resistor. R e f e r e n c e v o l ta g e o u tp u t ( n o mi n a l l y V D D /2 ) . M a y b e u s e d to b i a s th e i n p u ts a t mi d -r a i l .

IN H

Inhibits detection of tones represents keys A, B, C, and D

OSC3

D igital buffered oscillator output.

PD

Power D own

OSC1

Clock Input

OSC2

Clock Output

V SS

Negative power supply (normally connected to OV).

TOE

T h r e e -s t a t e o u t p u t e n a b l e ( i n p u t ) . L o g i c h i g h e n a b l e s t h e o u t p u t s Q1 -Q4 . I n t e r n a l p u l l -u p .

Q1 Q2 Q3 Q4

Three-state outputs. When enabled by TOE, provides the code corresponding to the last valid tone pair received. (See Fig. 2).

GS

Gain Select

StD ESt St/Gt

Logic high powers down the device and inhibits the oscillator. 3.579545 MHz crystal connected between these pins completes internal oscillator.

D elayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on St/GT falls below VTSt. Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected a St causes the device to register the detected tone pair . The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Fig. 2)

VDD

Positive power supply.

IC

Internal Connection.

Must be tied to VSS (for 8870 configuration only)

FLOW

F H IGH

KE Y

TOW

Q4

Q3

Q2

Q1

697

1209

1

H

0

0

0

1

13 36

2

H

0

0

1

0

697

All resistors are ± 1%tolerance. All capacitors are ± 5% tolerance.

697 770 770 770 8 52 8 52 8 52 9 41 9 41 9 41 697 770 8 52 9 41 -

1477 3 H 0 12 0 9 4 H 0 13 3 6 5 H 0 147 7 6 H 0 12 0 9 7 H 0 13 3 6 8 H 1 147 7 9 H 1 12 0 9 0 H 1 13 3 6 · H 1 147 7 # H 1 16 3 3 A H 1 16 3 3 B H 1 16 3 3 C H 1 16 3 3 D H 0 ANY L Z L = logic Low, H = Logic High, Z = High

0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 Z Z Impedance

1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z

Figure 2. Functional Diode Table

Figure 1. Single Ended Input Configuration ©2000 California Micro Devices Corp. All rights reserved.

6


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CM8870/70C


Figure 3. Typical Filter Characteristic

Figure 4. Basic Steering Circuit

Figure 6. Differential Input Configuration

Figure 5. Guard Time Adjustment



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CM8870/70C


OSC1

OSC2

OSC1

OSC3

OSC2

OSC1

OSC2

OSC1

OSC2

OSC1 of other CM887X’s Clock input of other devices 3.58 Mhz

30pF

Figure 7. CM8870C Crystal Connection (PLCC Package Only)

30pF

30pF

Figure 8. CM8870/70C Crystal Connection

Q4

VREF

5

13

Q3

IC*

6

13

Q3

IC * 6

12

Q2

OSC1

7

12

Q2

IC * 7

OSC2

8

11

Q1

VSS

9

10

TOE

P — Plastic DIP (18) F — Plastic SOP EIAJ (18) S — SOIC (18)

VREF

4

StD

INH

5

18

Est

17

16

NC

PD

6

StD

16

15

Q4

OSC3

NC

7

15

14

Q3

OSC1

Q4

8

14

Q3

PE

PE — PLCC (20) * — Connect To VSS

P — Plastic DIP (18) F — Plastic SOP EIAJ (18) S — SOIC (18)

Ordering Information Example:

CM8870C 9

TOE

ESt

17

OSC2

10

13

9

8

Q2

VSS

OSC1

11

Q1

12

11

Q1

8

TOE

OSC2

9

7

OSC2

OSC1

CM8870 10

6

VSS

IC*

18

CM8870 CM8870C

St/GT

14

19

5

P

13

IC*

Q2

Q4

IN+ IN-

4

14

VDD

GS

5

1

StD

INH

20

15

11

4

12

VREF

Q1

StD

TOE

15

GS

4

ININ+

ESt

VREF

3

16

2

3

10

GS

VSS

ESt

St/GT

16

19

3

IN+ IN-

St/GT

GS

VDD

VDD

17

1

18

2

20

1

IN-

NC IN+

St/GT

ININ+

VDD

17

3

18

2

CM8870

1

IN-

CM8870C

IN+

2

Pin Assignments

— PLCC (20)

I

Product Identification Number Package P — F — PE — S —

Plastic DIP (18) Plastic SOP EIAJ (18) PLCC (20) SOIC (18)

Temperature/Processing None — 0OC to +70OC, ±5% P.S. Tol. I — -40OC to +85OC, ±5% P.S. Tol.


8


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9/28/2000