Application Of Fuzzy Logic In Computer-aided VLSI Design - Fuzzy

IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 6, NO. 1, FEBRUARY 1998

163

Application of Fuzzy Logic in Computer-Aided VLSI Design Eugene Shragowitz, Jun-Yong Lee, and Eric Q. Kang

Abstract— Application of fuzzy logic structures in computeraided design (CAD) of digital electronics substantially improves quality of design solutions by providing designers with flexibility in formulating goals and selecting tradeoffs. In addition, the following aspects of a design process are positively impacted by application of fuzzy logic: utilization of domain knowledge, interpretation of uncertainties in design data, and adaptation of design algorithms. We successfully applied fuzzy logic structures in conjunction with constructive and iterative algorithms for selecting of design solutions for different stages of the design process. We also introduced fuzzy logic software development tool to be used in CAD applications. Index Terms— Adaptive systems, fuzzy logic, greedy algorithms, iterative algorithms, multiobjective optimization, VLSI CAD.

I. INTRODUCTION

F

UZZY set theory has been recently applied in many areas of science and engineering [24], [30], [35], [37], [38]. Works raising possibility of application of fuzzy logic in computer-aided design of digital electronics started to appear in late 1980’s and early 1990’s. In [7]–[9], the authors proposed fuzzy logic structures for decision making in architectural synthesis of VLSI and transistor network optimization. In these papers, the authors considered fuzzy logic as a method of enhancement in the knowledge-based reasoning process, but do not present implementation of the theoretical considerations into working CAD tools. Few published works with the experimental background on fuzzy logic-based CAD tools addressed isolated problems in digital design [12]–[14], [18], [19], [21], [26]. This list mainly includes publications of the authors of this paper. In this work, the authors describe, classify, and generalize their experience in building of fuzzy logic-based systems for digital CAD. Several works were published during the last two to three years on application of fuzzy logic in CAD of analog circuits [2], [32]–[34]. Methodologies and tools for analog circuits design are outside of the scope of this paper. The majority of design tasks in digital electronics can be formulated as combinatorial optimization problems with multiple objectives and constraints. Unlike single objective optimization problem, no concept of optimal solution is universally accepted for the multi-objective optimization. In practical cases, the rating of individual objective reflects the preference of decision makers. At best, the compromise between

Manuscript received July 26, 1996; revised December 12, 1996. This work was supported in part by the National Science Foundation under Grants MIP9123945 and MIP-9628022. E. Shragowitz and E. Q. Kang are with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455 USA. J.-Y. Lee is with the Department of Computer Engineering, Hong-Ik University, Seoul, 121-791 Korea. Publisher Item Identifier S 1063-6706(98)00792-9.

competing objectives can be expected. In fuzzy logic approach, optimization of a vector-valued function is replaced by optimization of a scalar function, which is constructed from levels of satisfaction of decision makers by values of components of a vector function. In practice, this approach is proven to be useful for finding of compromise solutions in different applications. In many CAD problems, multiobjective decision making is performed hierarchically. Fuzzy logic structures are effective in supporting hierarchical multiobjective decision making by producing on each level values for criteria to be used as values of membership functions on the next hierarchical level. Fuzziness and uncertainty typical for human decision making can be captured by such structures. Another reason to consider fuzzy logic approach is treatment of uncertainties in design data. While description of uncertainties in terms of conditional probabilities is possible, in the majority of practical cases it is difficult. Fuzzy logic provides more convenient framework for representation of such knowledge. Fuzzy logic systems allow adaptation of design algorithms in input data and to design goals. Traditional design algorithms do not have this flexibility. One more argument in favor of application of fuzzy logic in CAD is derived from a nature of algorithms used for solving design problems. Many of the models are proven to be NP hard even in their simplest forms. The majority of algorithms for design synthesis are heuristics. Heuristics are based on human knowledge acquired through experience and understanding of problems. The natural language, which is a base of fuzzy logic, is a more convenient vehicle for expressing such knowledge. To place this work in a perspective, it is instructive to reexamine informational aspects of design process for digital systems. Information about the object of design exists in two forms. The first form is numerical information derived from mathematical models of designed objects. Examples of such information are voltages and currents at different elements of the circuit, boolean values of logic variables, etc. The second common form of representation is a linguistic form, when a description is formulated in the natural or artificial language. Linguistic descriptions usually are given in fuzzy terms not only because it is the most common form of representation of human knowledge, but also because our knowledge about many aspects of the design is fuzzy. Fuzziness in design information exists on several levels. Many of our definitions in linguistic terms are imprecise, for instance, “low power design.” This term is fuzzy because meaning of “low power” is fuzzy and dependent on the context. The term “correct design” possibly can be described completely and crisply by using a large number of descriptors. Another source of fuzziness is complexity of dependencies between different characteristics

1063–6706/98$10.00  1998 IEEE

164


Fig. 1. Multiple objective for initial standard cell placement.

of the designed system. For example, knowledge about relations between area of the circuit and a clock rate prior to implementation of the design exists in the form of the fuzzy rule “if area could be made larger, then clock rate could be made higher.” Linguistic information, while not precise, is an important source of knowledge about the system. A problem is to generalize methods for utilization of numerical and linguistic information in a design process. In this paper, we intend to show how fuzzy logic can be used to extend power of basic algorithmic approaches to problems from different domains of digital design. II. CLASSIFICATIONS OF FUZZY LOGIC APPLICATIONS IN CAD TOOLS Human factors involved in design selection and evaluation make design problems natural targets for application of fuzzy logic. This does not preclude an application of fuzzy logic for certain types of analysis when fuzziness in input data should be taken into consideration. The ultimate criteria for effectiveness of fuzzy logic in design is practice, i.e., whether or not quality of solutions obtained by fuzzy logic tools is higher than solutions generated by tools, which do not employ fuzzy logic. The gain certainly should be weighted against efforts required for incorporation of fuzzy logic into design tools, their flexibility to adaptation and user friendliness. Based on our experience, such efforts are justifiable. In the following text, we will generalize our experience and propose a plan for further developments. Design of complex digital systems is a multistage process, which involves application of variety of algorithms. Design systems differ by how they organize design flow and formulate subtasks as well as how they solve them. In this paragraph, we propose a classification useful for describing fuzzy logic applications in CAD. By their level in the design hierarchy: 1) physical design; 2) logic design; 3) architectural design. By aspects of design addressed by fuzzy logic: 1) multiobjective decision making; 2) encapsulation of domain knowledge; 3) adaptation of design algorithms; 4) uncertainty in design data and their interpretation.

By types of algorithms used for finding design solutions: 1) constructive; 2) iterative; 3) combination of constructive and iterative. We will use this classification in the following descriptions.

III. APPLICATION OF FUZZY LOGIC IN CONSTRUCTIVE ALGORITHMS FOR PHYSICAL DESIGN Many physical design problems are solved by constructive algorithms also called “successive augmentation” and “greedy.” These algorithms generate a final solution by successively adding one or a group of new elements at a time to a partial solution. Multiple criteria are used for making decisions on each consecutive step. For instance, in a fuzzy constructive placer for the standard cell-design style, each new cell added to the partial placement was characterized by three linguistic variables: timing, area of partial placement, and interconnection length. Each linguistic variable is characterized by linguistic values; for instance, good timing, satisfactory timing, or bad timing. Each linguistic value represents a fuzzy set, i.e., for each numerical value of timing, area of partial placement, and interconnection length, the degree of their participation in the respective fuzzy sets satisfactory timing, small interconnection length, and small area of partial placement are defined by the membership functions , , and . These userdefined functions map the universe of discourse for each linguistic variable in the interval [0,1]. A fuzzy logic decision maker (FZDM) for constructive methodology (called FZDM-C) takes different objectives and many criteria involved in the process of placement into consideration. The FZDM-C consists of two levels of objectives and each leaf level-objective has one or more levels of criteria. Relations among various objectives are shown in Fig. 1. The criteria for one of leaf objectives is shown in Fig. 2. Assignment of a cell to one of its feasible intervals is achieved by first selecting one of the rows where a feasible interval is present; then, by assigning the cell to this interval. While many heuristic rules were formulated in the literature for choosing cells for each row, they take only same aspects of placement into consideration. Fuzzy logic can help to solve this problem.

SHRAGOWITZ et al.: APPLICATION OF FUZZY LOGIC IN COMPUTER-AIDED VLSI DESIGN

165

Fig. 2. Fuzzy logic criteria for minimizing wire length.

For the sake of convenience, we assume that placement starts from the top of the chip and proceeds row by row to the bottom. Our implementation, on the other hand, allows users to specify a row sequence in addition to the default top bottom sequence. For each row, the candidates are any cells that have feasible intervals in the row. Since the number of candidate cells for the row usually exceeds the capacity of a row, we need to select a subset from the candidate cells to be placed in the row. To produce feasible placement it is necessary to consider not only timing requirements, but also chip size and interconnections length. The selection of cells in any given row affects both the timing and the chip size. A set of criteria is used to describe each candidate cell. Many different objectives and criteria are involved in decision making process. On the highest level of hierarchy, an objective is good placement. Fuzzy logic rules are used to relate objectives/criteria on two consecutive levels. Relations between peer objectives/criteria are defined by fuzzy logic preference rules. To ensure that good placement would be obtained by constructive procedures, reasonably good decisions have to be made at every stage of placement. Therefore, in the initial constructive stage, the root objective good placement is defined to be good partial placement at each stage of placement (Fig. 1). Many fuzzy logic rules and preference rules implemented for the lower level objectives/criteria take placement stages into considerations. For example, linguistic variable placement stage has linguistic values early stage, middle stage, etc. Then the objective good partial placement at each stage of placement is adapted at each stage according to fuzzy logic rules. Such strategy alleviates negative consequences of application of a greedy algorithm for standard cell placement. The following rules are used to relate level 1 and level 2 objectives: R.1a If a candidate cell (added to partial placement) produces satisfactory timing and small chip area and small interconnection length, then it is good partial placement. R.1b If a candidate cell produces satisfactory timing and (small chip area or small interconnection length), then it is good partial placement.

R.1c If a candidate cell produces small chip area and (satisfactory timing or small interconnection length), then it is good partial placement. As one can see, rule R.1a) assigns equal significance to all three criteria: timing, area, and wire length, while rules R.1b) and R.1c) put more emphasis on timing or area. In addition to fuzzy logic rules on the highest hierarchical level, criteria involved in making decision may be emphasized or de-emphasized by an additional set of rules that give preferences to one criterion or another depending on stages of the process or desires of users. Some preference rules on the second level are formulated in the following form: PR.2a If not in the early placement stage, then objective 1/1 (satisfactory timing) has a strong preference over objective 1/2 (small area) and objective 1/3 (small interconnection length). PR.2b Objective 1/3 (small interconnection length) has a mild preference over objective 1/2 (small area). PR.2c Objective 1/2 (small area) has a strong preference over objective 1/1 (satisfactory timing). PR.2d Objective 1/3 (small interconnection length) has a strong preference over objective 1/1 (satisfactory timing). In these rules, linguistic values early placement stage, strong preference, and mild preference have been introduced. Whatever system of goals and preference rules is chosen, a cell that corresponds to the largest value of objective function is selected for placement. As we mentioned earlier, the linguistic values satisfactory timing, small area, and small interconnection length are themselves hierarchically constructed fuzzy sets. For details see [13]. As an example, a fuzzy logic structure for one of objectives on the highest hierarchical level (wire length) is given in Fig. 2. Here, the fuzzy logic operation and is used to combine the criteria at the lowest level for defining the membership function for the criteria at the higher level. Preference rules are given as follows: • In the early stages of placement, criterion 1/3/1/1 has a strong preference over criterion 1/3/1/2 and criterion 1/3/1/3 combined.

166


TABLE I CHARACTERISTICS OF BENCHMARK TEST CASES

operate over the values from the interval [0, 1] defined by the membership functions for each objective. For example, the objective function for the simulated annealing model of the placement problem [29] includes interconnection length, an overlapping penalty, and a penalty for length of the net exceeding bounds. The objective function is defined by the formula

• If the cell size distribution of the candidate cells for a row is wide distribution, then criterion 1/3/2/1 has a strong preference over criterion 1/3/2/2. A. Experiments with MCNC Standard Cell Benchmarks The system described in this paper is written in C/C++, the essential part of the package contains approximately 15 000 lines of code. Effectiveness of this placer has been tested on three MCNC standard cell benchmark test cases. (The only MCNC benchmarks with timing information.) The basic characteristics of these benchmarks are given in Table I. We compared our placer with two well-known and available placers: OASIS (VPNR) and TimberWolf6.1. Timing delay in Table II comes from our own experiments with OASIS and TW6.1 packages. Table III lists results for the fuzzy logic placer with three different combinations of goals. When the set of rules emphasizing timing was selected, propagation delay (Table III-A) with respect to OASIS and TW6.1 was reduced 36% in average with accompanying area increasing by 4.5%. When the set of rules emphasizing area was invoked, area produced was 3% smaller (Table III-B) for all benchmarks compared to the best area achieved by OASIS and TW6.1, while timing delay was also reduced by 8% in average. When the set of rules emphasizing both area and timing was selected (balanced solution), no increase in area with respect to the best OASIS or TW6.1 solutions was accompanied by propagation time reduction by 28% in average (Table III-C). IV. APPLICATION OF FUZZY LOGIC IN ITERATIVE ALGORITHMS FOR PHYSICAL DESIGN Unlike constructive algorithms for physical design, which produce a solution only at the end of the design process, iterative algorithms operate with design solutions defined at each iteration. Many popular algorithms used in physical design automation are iterative in nature (simulated annealing genetic algorithms). A value of the objective function is used to compare results of consecutive iterations and to select a solution based on the maximal (minimal) value of the objective function [4], [6], [10], [15], [22], [25], [28]. In the situations with the multiple objectives, they are included in the objective function with the weight coefficients reflecting hierarchy of goals in the eyes of the designer. Balancing different objectives by the weight function is difficult because it requires comparison of “apples” and “oranges.” Fuzzy logic is a convenient vehicle for solving this problem because it allows to map values of different criteria into linguistic values, which characterize level of satisfaction of the designer with the numerical value of objectives and to

where is the weight coefficient for the objective and is the point in the solution space of the placement problem. In fact, the objective function is not a scalar, but a vectorfunction

where is the interconnection length, is the overlapping area, and is the timing delay. To obtain a fuzzy logic definition of the objective function for an iterative algorithm, three linguistic variables—interconnection length, overlapping, and timing—are defined for these functions. A set of linguistic values is defined for each component of the objective function. In case of placement, only one linguistic value is defined for each variable; that is, small length, small overlapping, and good timing. These linguistic values characterize a degree of satisfaction of the designer with values of objectives . These degrees of satisfaction are described by membership functions on fuzzy sets of linguistic values. Membership functions for small length, small overlapping, and good timing are easy to build. They are assumed to be nonincreasing functions because the smaller interconnection length , overlapping , and timing , the higher degree of satisfaction , , and of the expert and, vice versa, the longer are interconnections, the larger overlapping and timing, the smaller are degrees of membership in the fuzzy sets small length, small overlapping, and good timing. To make the membership functions applicable to different designs, linguistic variables interconnection length, overlapping, and timing are normalized to design data. We substitute a problem of minimization of by maximization of where is the vector function comprised of degrees of satisfaction with the value of objective . Then evaluation for the vector of solution corresponds to the evaluation of the the following rule: R.0 If a solution has small length and small overlapping and good timing, then is a good solution. This rule defines a degree of membership of the solution in the fuzzy set good solution over the universe of all solutions. IF-part of rule R.0) defines an intersection operation over the fuzzy sets small length, small overlapping, and good timing. Then-part of the rule assigns a degree of membership in the insection to the degree of membership in the fuzzy set good solution.


LAYOUT RESULTS

BY

OASIS

167

TABLE II AND TW6.1 AFTER DETAILED ROUTING

TABLE III LAYOUT RESULTS BY FUZZY LOGIC PLACER

Fuzzy logic compensatory operators [5] are used for intersection and union operations emerging in design applications. According to these definitions, membership in intersection of fuzzy sets is defined as

where Here is a user-defined value; then a value of a vectorfunction is evaluated by a value of scalar function and the optimal solution is found as

The example given above exhausts neither all possible factors to be considered in physical design nor their dependencies, but it demonstrates how a traditional definition of a multi-objective problem can be transformed into a fuzzy logic definition. Function can be used instead of function in making decisions in iterative procedures. An additional resource of ranking criteria in multi-objective optimization is assigning weights as exponents to membership functions, i.e., considering , where a weight can be adapted from iteration to iteration. V. FUZZY LOGIC ALGORITHMS TOOLS FOR LOGIC SYNTHESIS

AND

It is clear that application of fuzzy logic in CAD should not be restricted to physical design. Numerous problems in logic synthesis involve multiplicity of goals and constraints and domain knowledge in the linguistic form. One promising area of application of fuzzy logic is a fastdeveloping field programmable gate array (FPGA) technology. Mapping of combinational and sequential circuits in FPGA’s presents such a problem.

A. Constructive Fuzzy Logic Mappers for Complex FPGA’s Often the circuit design starts with the logic-level description of the circuit, presented in a form of a system of Boolean equations. This initial Boolean representation is first optimized according to selected criteria and then mapped into an existing cell library. In the case of FPGA’s, the optimized network is mapped into a circuit that consists of FPGA logic blocks. Recently, many technology mapping algorithms were developed by universities and by industry. The majority of technology mapping methods is designed to map the Boolean network into the XILINX XC3000 FPGA circuit structure, where each configurable logic block (CLB) has 2 bits of SRAM look-up table (LUT) capable of implementing Boolean equations with up to five inputs. As the FPGA’s became more popular, the FPGA architecture evolved. For example, in XILINX XC4000, the CLB consists of two four-input LUT’s with their outputs connected to the input of one three-input LUT. It can implement any two four-input functions, any single five-input function, a combination of any single four-input function and some five-input functions, or some functions of up to nine inputs. A potential advantage of the complex CLB structures is the fact that with a small additional memory, potential modeling capabilities can be substantially enhanced. An accurate mathematical formulation of the mapping problem for Xilinx XC4000 in the form of quadratic assignment problem of large dimensions reveals that the mapping problem is NP-hard [11]. The proposed algorithm utilizes memory resources of CLB’s in order to obtain better timing performance. This problem is also characterized by multiplicity of objectives and constraints. A greedy multiobjective algorithm is used to construct a solution. From a given directed acyclic graph (DAG) of Boolean equations the algorithm first selects the best node to start mapping to logic blocks. The set of fuzzy criteria is used to select the best candidate. Starting from the seed node, the mapping is continued to the nodes connected to the already mapped node until no more nodes can be mapped into the logic

168


Fig. 3. The objectives and constraints to choose a seed node.

block. A seed node for mapping is selected by an hierarchical structure of fuzzy rules. On the highest hierarchical level the rule to select a new seed node is formulated as a fuzzy rule: • If a node produces small timing delay and small number of new logic blocks, then a node is a good candidate to be mapped into a logic block. In its own turn the values of subobjectives small timing delay, small number of logic blocks are defined from the previous hierarchical level by the structure depicted in Fig. 3. An hierarchy of the fuzzy logic rules connects criteria from the same hierarchical level and propagates computed values through the hierarchical structure. In FPGA mapping, several goals compete in choosing an element from a given set. Area and delay are considered as the two competing goals. These goals for area and delay are declared by the user in terms of the number of CLB’s and the number of CLB levels expected for a design. Additional improvement of results achieved by the constructive algorithm can be obtained by adaptation of design procedures [20]. For the proposed goals, the adaptation is performed on two levels. On the first level, the adaptation is dynamic while the input DAG is being mapped to the FPGA logic blocks (CLB’s). During the mapping process, the number of mapped nodes is counted and the ratio of the mapped nodes over all ) is computed. At regular intervals nodes in DAG ( in mapping ratio (0.1), area, and delay are evaluated and the mapping process is modified to move results closer to the expected values. As one can see from Table IV, the fuzzy logic mapper for combinational circuits (FMC) traded a decrease in number of maximal levels (28%) for the increase in number of logic blocks (2%). More details about this system can be found in [19]. B. Constructive Fuzzy Logic Mappers for Sequential Logic with Retiming Sequential elements are important integral parts of digital circuits along with combinational elements. Therefore, the

TABLE IV EXPERIMENTAL RESULTS

technology mapping algorithm should consider both types of elements to improve mapping in FPGA’s. Timing in sequential circuits depends on delay of the longest path between flipflops. Area in the FPGA circuit is determined by the number of flipflops as well as by the number of LUT’s. Design objectives in the sequential logic mapping coincide with those for the combinational logic mapping: area, delay, and routability. As in the other applications in this paper, fuzzy logic can be used to solve this multi-objective problem.


169

Fig. 4. Retiming in FPGA mapping.

A commonly employed technique to optimize a sequential circuit is to partition it into combinational and sequential parts. Then the combinational part is mapped into FPGA and the sequential elements are added to the result. For this methodology, timing is dependent on the results of mapping of combinational part of the circuit. In order to improve timing of a sequential circuit, re-timing transformations are necessary [17]. Retiming can alter the clock period of a circuit by relocating registers and reducing length of the critical path. Fig. 4 illustrates the basic idea of retiming in FPGA mapping. By relocating the register, the critical path delay is reduced from two to one in terms of CLB levels. A decision to relocate registers will be formulated as a hierarchical structure of fuzzy logic rules that will include several criteria such as small critical path delay, small number of CLB’s, good routability, etc. Fuzzy logic rules are used to select candidate nodes for retiming. Multiple criteria which are used in fuzzy logic rules are derived from the properties of input DAG or from the results of the mapping. These fuzzy logic rules are organized into the hierarchical structure. One example of fuzzy logic rules governing retiming is given below. • If a node is a good candidate for the “move-forward” operation or for the “move-backward” operation, then a node is a good candidate for re-timing. This rule is supposed to choose an which maximizes the value of the decision function

This rule computes a level of membership of a candidate node in the fuzzy set of good candidates for re-timing. and are defined on the lower hierarchical levels in the similar manner. The results of experiments are shown in Table V. In order to demonstrate performance of the mapper, 16 benchmark circuits were randomly selected from the set of MCNC test cases for sequential circuits. The results of technology mapping were completed by Xilinx’s placement and routing system (PPR 5.2). The first three columns report the numbers of used CLB’s, the maximal number of CLB levels, and the delay of the

critical path after the initial mapping was performed for the test cases. The following three columns present the results of the mapping after iterations of mapping and re-timing. The last three columns present the results achieved by the Xilinx system for the same test cases. The overall results show that the fuzzy logic mapper for sequential circuits (FMS) system [19] out-performs Xilinx’s technology mapper for sequential circuits in both area and timing. The FMS system reduced the maximal number of the CLB levels by 18.4%, which resulted in 15.6% reduction in actual delay after layout. Our system also reduced the number of used CLB’s by 6.2%. The experiments show that the fuzzy logic mapper even without re-timing steps produced the solutions with 10% better timing than Xilinx. Retiming step cuts additional 10% from timing obtained by the initial mapping.

VI. FUZZY LOGIC ALGORITHMS ARCHITECTURAL SYNTHESIS

FOR

An architectural level of design synthesis presents wide opportunities for application of fuzzy logic because knowledge in this level of design very often is expressed in the linguistic form. Such knowledge should be combined with the crisp values for selected criteria to obtain good design solutions. A. Fuzzy Logic Algorithms for List Scheduling One of the most important problems in high-level (architectural) synthesis is scheduling. Scheduling assigns operations to time steps under constraints on sequence of operations and hardware resources available for implementation [1], [3], [16], [31]. Area/latency tradeoffs for a given clock rate characterize the scheduling problem. All realistic definitions of scheduling problems are proven to be NP-hard [3]. When one of the major criteria (area, latency) is scheduled as an objective and another is considered as a constraint, the two-problem formulations emerge. 1) minimum-latency resource-constrained problem; 2) minimum-resource latency-constrained problem. A family of heuristic algorithms known for this problem is called list-scheduling algorithms. When latency is minimized, the list-scheduling algorithms generate a solution for each

170


TABLE V EXPERIMENTAL RESULTS

resource by successively selecting candidates from the set of candidate operations. The list-scheduling algorithms are classified by their selection steps. A priority list used for this purpose is based on the length of the path to the sink in the sequencing graph. This criterion is similar to that of the multiple criteria used in selection of the seed node in FPGA mapping described in the previous section. Fuzzy logic structure can be used for finding priority by including multiple criteria in the selection process and connecting them by fuzzy logic rules as in problems described earlier. Among factors to be included are the number of resources and timing of unfinished operations, minimum timing constraints, duration and type of operations that immediately follow already scheduled operations, restrictions on concurrency, requirements on operation chaining, and other factors. These factors, when included into decision making, should provide better solutions for the stated problem. For minimizing resource usage under latency constraints, fuzzy logic can be used for allocation of additional resources before it is clear from the slack calculation that the latency bound will be violated. Application of fuzzy logic in list scheduling will not change low computational complexity of this algorithm (i.e., will keep it applicable for practical situations characterized by large graphs). VII. GENERIC HIERARCHICAL FUZZY LOGIC DECISION MAKER FOR CAD PROBLEMS A generic tool is recommended for fuzzification of hierarchical decision making in computer-aided design (CAD) environment.

It should be emphasized that applications of fuzzy logic hierarchical decision makers are not limited to specifically designed fuzzy logic CAD tools. It can be extended to existing CAD tools to improve their flexibility in selecting and balancing of multiple criteria computed by numerical algorithms. In our own CAD applications, fuzzy logic is mostly used to make decisions over numerical data. Existing commercial fuzzy logic development tools lack many characteristics essential for successful applications in CAD development. The main features absent from the existing commercial products are: 1) support for hierarchical multi-objective decision-making structures; 2) porting mechanisms of decision-making structures to host programs written for implementation of numerical algorithms. The new tool should satisfy the following requirements: 1) easy definition of fuzzy logic linguistic variables; 2) simple graphic and analytical definitions of membership functions; 3) simple way to define fuzzy logic operations and set fuzzy logic rules; 4) easy-to-support hierarchical structures of decision makers; 5) verification of consistency; 6) easy-to-port and incorporate the designed decision makers to host programs. Guided by these goals, we developed a prototype of a tool that should satisfy stated goals. To take the advantage of object-oriented programming (OOP) technology [23], the basic block is designed to be a basic OOP class that can be extended to form more specific blocks (classes) with special properties. These blocks can be instantiated easily to form


171

goals according to designer’s desires and more effective in generating solutions that match stated goals. We also provide a description of a generic fuzzy logic CAD development tool that allows to include fuzzy logic structures into existing traditional design algorithms without the major redesign of a computer code. We are going to continue to develop and improve fuzzy logic based CAD tools mainly for the multi-objective problems in the digital CAD. REFERENCES Fig. 5. Basic block of fuzzy logic decision-making structure.

an hierarchical fuzzy logic decision-making structure. Fig. 5 shows the graphic representation of internal elements of a basic block. A basic block is, in essence, a linguistic variable that represents either an objective or a criterion. A membership function for a linguistic variable can be introduced either by an analytical formula or in a table form, which is then interpolated into a piecewise linear function. Users can customize the linguistic variable and its membership function for each basic block. If the link point to a parent for a basic block is not used, then the block is on the highest hierarchical level; similarly, if the link point to children is not used then this block is on the lowest level of hierarchy. Otherwise, both link points will be used. Basic fuzzy logic operators are defined in several different ways according to the most popular standard definitions or customized definitions are allowed. For example, fuzzy “and” is defined in several different ways: by min over the values of membership functions or according to Dubois and Prade formulas [5] or by customized definitions. Fuzzy logic rules are used to define relations between a linguistic value of a parent block and linguistic values of children blocks. The hierarchical structure allows membership functions of linguistic values at a higher level to be defined by membership functions on a lower level. The membership functions of linguistic values at the lowest level have to be given explicitly in a graphic form or in a table form. This tool has already been used for development of some systems described earlier.

VIII. CONCLUSION This paper presents characterization, justification, and classification of fuzzy logic-based CAD tools for digital design. It is demonstrated that application of fuzzy logic is beneficial on all hierarchical levels of the design process. It allows to merge traditional numeric techniques with the domain information available in the linguistic form and, as a result, to improve quality of design solutions. Fuzzy logic structures are shown to be used in constructive and iterative procedures. Short descriptions of several CAD tools are accompanied by the experimental data and comparison of design solutions is obtained by different tools for popular benchmarks. It is demonstrated that fuzzy logicbased tools are capable of emphasizing and de-emphasizing

[1] D. Bajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Norwell, MA: Kluwer, 1992. [2] J. Chaves, A. Torralba, and L. G. Franquelo, “A fuzzy-logic based tool for topology selection in analog synthesis,” in Proc. IEEE ISCAS’94, London, U.K., 1994, vol. 1, pp. 367–370. [3] G. DeMichelli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994. [4] W. Donath, R. Norman, B. Agrawal, S. Bello, S. Han, J Kurtzberg, P. Lowy, and R. McMillan, “Timing-driven placement using complete path delay,” in Proc. ACM/IEEE 27th Design Automat. Conf., Orlando, FL, June 1990, pp. 84–89. [5] D. Dubois and H. Prade, “New results about properties and semantics of fuzzy set-theoretic operators,” Fuzzy Sets-Theory and Applications to Policy Analysis and Information Systems. New York: Plenum, 1980, pp. 59–75. [6] A. E. Dunlop, V. D. Agraval, D. N. Deutsch, M. F. Jukl, P. Kozak, and M. Wiesel, “Chip layout optimization using critical path weighting,” in Proc. ACM/IEEE 21st Design Automat, Conf., Albuquerque, NM, 1984, pp. 133–136. [7] R. Felix and A. Hollmann, “ A Knowledge-based system using reasoning with uncertainty in the VLSI chip synthesis domain,” Eng. Applicat. Artificial Intell. vol. 2, pp. 144–161, June 1989. [8] R. Felix, “Goal-oriented control of VLSI design processes based on fuzzy sets,” in IEEE Proc. 20th Int. Symp. Multiple-Valued Logic, Charlotte, NC, May 1990. [9] T. Gao, P. M. Vaidya, and C. L. Liu, “A performance driven macro-cell placement algorithm,” in Proc. ACM/IEEE 29th Design Automat. Conf., Anaheim, CA, June 1992, pp. 147–152. [10] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979. [11] S. Iman, M. Pedram, and K. Chaudhary, “Technology mapping using fuzzy logic,” in Proc. ACM/IEEE 28th Design Automat. Conf., 1994. [12] E. Kang, R.-B. Lin, and E. Shragowitz, “Fuzzy logic approach to vlsi placement,” IEEE Trans. Very Large Scale Integrat. Syst., vol. 2, pp. 489–501, Dec. 1994. [13] E. Kang and E. Shragowitz, “Generic fuzzy logic CAD development tool,” in Proc. Asia South-Pacific Design Automat. Conf. (ASP-DAC), Makuhari, Japan, Aug. 1995, pp. 75–80. [14] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreigh, “GORDIAN: VLSI placement by quadratic programming and slicing optimization,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 357–365, Mar. 1991. [15] D. Ku and G. DeMicheli, High-level Synthesis of ASIC’s Under Timing and Synchronization Constraints. Norwell, MA: Kluwer, 1992. [16] C. E. Leiserson and J. B. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol. 6, no. 1, pp. 5–35, 1991. [17] J.-Y. Lee and E. Shragowitz, “Performance driven technology mapper for FPGA’s with complex logic block structures,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Seattle, WA, Apr. 1995, vol. 2, pp. 1219–1222. , “Technology mapping for FPGA’s with complex block archi[18] tectures by fuzzy logic technique,” in Proc. Asia South-Pacific Design Automat. Conf. (ASP-DAC), Makuhari, Japan, Aug. 1995, pp. 295–300. , “Application of fuzzy logic for technology mapping of field [19] programmable gate arrays,” in Proc. SPIE Int. Symp. Aerosp./Defense Sensing Contr., Orlando, FL, Apr. 1996, pp. 237–248. [20] R.-B. Lin and E. Shragowitz, “Fuzzy logic approach to placement problem,” in Proc. ACM/IEEE Design Automat. Conf. (DAC), Anaheim, CA, June 1992, pp. 153–158. [21] M. Marek-Sadowska and S. P. Lin, “Timing driven placement,” in Proc. Int. Conf. Comput.-Aided Design, Santa Clara, CA, Nov. 1989, pp. 94–97. [22] J. K. Ousterhout, Tcl and the Tk Toolkit. Reading, MA: AddisonWesley, 1994.

172


[23] W. Pedrycz, Fuzzy Control and Fuzzy Systems. New York: Wiley, 1989. [24] M. Pirlot, “General local search methods,” Eur. J. Operat. Res., vol. 92, pp. 493–511, 1996. [25] M. Razaz and J. Gan, “Fuzzy set based initial placement for IC layout,” in Proc. Eur. Design Automat. Conf., 1990, pp. 655–659. [26] E. Shragowitz, J.-Y. Lee, and E. Kang, “Application of fuzzy logic to computer-aided design of electronic systems,” in Proc. SPIE Int. Symp. Aerosp./Defense Sensing Contr., Orlando, FL, Apr. 1996, pp. 196–209 (invited paper). [27] A. Srinivasan and K. Chaudhary, “Ritual: A performance driven placement algorithm,” IEEE Trans. Circuits Syst., vol. 39, pp. 825–840, Nov. 1992. [28] W.-J. Sun and C. Sechen, “Efficient and effective placement for very large circuits,” in Proc. Int. Conf. Comput.-Aided Design, Santa Clara, CA, Nov. 1993, pp. 170–177. [29] T. Takagi and M. Sugeno, “Fuzzy identification of systems and its applications to modeling and control,” IEEE Trans. Systems, Man, Cybern., vol. SMC-15, no. 1, pp. 116–132, 1985.

[30] D. Thomas, E. Lagnese, R. Walker, J. Nester, J. Rajan, and R. Blackburn, Algorithmic and Register Transfer Level Synthesis: The System Architect’s Workbench. Norwell, MA: Kluwer, 1990. [31] A. Torralba, J. Chaves, and L. G. Franquelo, “Fault detection and classification of analog circuits by means of fuzzy logic based techniques,” in Proc. IEEE ISCAS, Seattle, WA, Apr. 1995, pp. 1828–1831. [32] A. Torralba, J. Chaves, and L. G. Franquelo, “FASY: A fuzzy-logic based tool for analog synthesis,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 705–715, July 1996. , “Circuit performance modeling by means of fuzzy logic,” IEEE [33] Trans. Computer-Aided Design, vol. 15, pp. 1391–1398, Nov. 1996. [34] L.-X. Wang, Adaptive Fuzzy Systems and Control. Englewood Cliffs, NJ: Prentice-Hall, 1994. [35] L. A. Zadeh, “The concept of a linguistic variable and its application to approximate reasoning—I,” Inform. Sci., vol. 8, pp. 199–249, 1975. [36] H. J. Zimmermann, Fuzzy Set Theory and Its Applications, 2nd ed. Norwell, MA: Kluwer, 1991. [37] , Fuzzy Sets, Decision Making, and Expert Systems. Norwell, MA: Kluwer, 1987.