based Harmonic Elimination PWM Generator

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concurrent, high-speed response for determination of circuit output (switching ... maximum available amplitude of the inverter output voltage corresponding to the ...
A Simple Approach to the Realization of an FPGAbased Harmonic Elimination PWM Generator Woei-Luen Chen Member, IEEE

Yung-Ping Feng

Chun-Hao Pien

Dept. of Electrical Engineering Chang Gung University, Taiwan, R.O.C. [email protected] overmodulation, the switching rate of SPWM is limited and can only be operated at medium frequency as shown in Fig. 1. In order to make up defects of the SPWM as mentioned above, the switching frequency of the SVPWM inverter is selected to be greater than that of the HEPWM. The operational principle of an SVPWM generator is based on the configuration of the inverters. For a three-phase VSI which consists of three legs, one for each phase. Therefore, only eight combinations (states) are possible. Since two of these states are null vectors, the vector space can thus be divided into equal sectors by the left six states (active vectors). Any voltage vector in this vector space can be synthesized by two active and one null voltage vectors according to the time control of each switching state. Based on this time control rule, the switching sequence may not be unique. The annoying common mode voltage caused by conventional PWM switching can be reduced by taking the Index Terms—EPROM, FPGA, HEPWM, VSI, VHDL. advantage of the flexible assignment of the switching sequence within each switching cycle [11-12]. The SVPWM I. INTRODUCTION generator can be realized by a low-cost chip set which has It is well known that inverters operated at high switching the capability in determining the pulse width of the SVPWM frequency can reduce harmonic distortions and decrease the waveform [9]. The most attractive feature of HEPWM technique is an size of output filter. However, further improvement on inherent compromise to the usual confliction between harmonic distortion by raising the switching frequency is inverter switching frequency and harmonic distortions. A unrealistic because high power, fast switching device are not number of papers have been published on the available. Several modulation strategies have been developed implementation of HEPWM waveforms [2-7]. Even though for VSIs including the following: sinusoidal PWM (SPWM), that various algorithms developed for calculating the near space vector PWM (SVPWM), harmonic eliminated PWM optimal switching angles were possessed of a fast and (HEPWM), and square-wave switching. efficient realization in a microprocessor-based controller [4The conventional sinusoidal PWM can be obtained by comparing a sinusoidal control signal with a triangular 5], yet the apparent time delay due to sequential programs is waveform. The frequency of the triangular waveform still inevitable. This paper describes a digital realization of establishes the inverter switching frequency and is generally an HEPWM generator by using FPGA as a kernel controller. higher than the inverter output frequency. The high The controller is essentially a look-up table which consists of frequency switching results in a substantially lower harmonic a synchronous circuit, a clock control circuit, and a lockout distortions compared to the square-wave switching. However, circuit. The off-line calculated switching patterns are stored except for the significant drawback of switching losses, the in the EPROM and will be picked out according the given maximum available amplitude of the inverter output voltage modulation index and phase angle. sw. rate corresponding to the SPWM in the linear range (modulation SPWM index mi≦1) is lower than the others. If the modulation high SVPWM /SVPWM index exceeds unity, SVPWM and HEPWM techniques are med. alternatives for the modulation index lower than 1.15 [1-10]. HEPWM SPWM Although higher modulation index (mi>1.15) is attainable by Square wave low repeating the tactics of SPWM or square-wave switching, the mi voltage quality will be scarified in that manner. Furthermore, 0.0 1.0 1.15 3.24 since the notches are suppressed in the range of Figure 1. Summary of PWM generator capabilities. Abstract-This paper presents a low-cost and effective approach to generate harmonic elimination PWM (HEPWM) waveforms for three-phase voltage-sourced inverters (VSIs). In the developed approach, the off-line computations of switching patterns based on harmonic elimination strategy are stored in EPROM, thereby allowing a microprocessor-free design. With the proposed configuration, the circuits for the adjustments of modulation index and phase angle are synthesized onto a fieldprogrammable gate array (FPGA) by means of hardware description language (VHDL). Since the VHDL statements, contrary to regular microprocessor programs, are inherently concurrent, high-speed response for determination of circuit output (switching state associated with the specified modulation index and phase angle) can be achieved. Furthermore, in order to limit switching losses for high power applications, eight switching sets having switching angles from 3 to 17 (M=2N+1, N=1…8) in each quarter fundamental period are available. Experimental and simulation results are presented to verify the effectiveness and accuracy of the proposed configuration.

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II. REVIEW OF HEPWM PRINCIPLE As shown in Fig. 2, the HEPWM waveform with M switching angles in each quarter fundamental period is odd quarter-wave symmetric, only odd-order harmonics exist [67] and are given by

s ( t ) = a0 +



∑b

h∈odd

h sin ( hω t )

(1)

where bh =

M 4 ⎡ ⎤ k +1 −1 + 2∑ ( −1) cos ( hα k ) ⎥ . ⎢ πh ⎣ k =1 ⎦

1

Switching function

...

0

...

...

α1α2α3 α4 ...αM

π/2

III. HARDWARD IMPLEMENTATION



Figure 2. Typical switching waveform of HEPWM generator.

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Fig. 4 shows the circuit block diagram of the configuration of the proposed FPGA-based HEPWM generator. In this work, eight switching patterns related to the cases of M=3, M=5,…,and M=17 are stored in the EPROM. The switching patterns can be encoded by cascading the digitized signals of the modulation index and phase angle as address inputs for the EPROM. In addition, to synthesize the circuit functions on an FPGA, the timing management is essential. As illustrated in Fig. 5, the timing control circuit consists of READ timing control as well as synchronous input for EPROM, and dead-time control for lockout circuit. The access time, a measure of EPROM’s operation speed, should be programmed on the FPGA (EPM7128SLC84-15) to enable the READ operation of the EPROM. The output frequency of the oscillator-I in Fig. 4 is regarded as the time reference in order to create the access time, the dead-time, and the synchronous time for the FPGA. The sequences of timing circuits are carried out in the syntax of the finite state machine (FSM).

α9 α8

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rad

With M number of αk angles, the fundamental voltage can be controlled and M-1 harmonics can be eliminated. The nonlinear equations, as mentioned above, can be solved numerically for the specified fundamental amplitude and then α1, α2, ... αM can be determined. The switching angles within each quarter fundamental period for different modulation indices related to the cases of M=3, M=11, and M=17 are plotted in Figs. 3(a), 3(b), and 3(c), respectively.

...

3π/2

π

The phase-to-neutral voltage according to the switching function (1) can be written as ∞ V v An = dc ∑ bh sin ( hω t ) , k = 1, 2,3... . (2) 2 h∈{1,6 k ±1}

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α17 α16 α15 α14 α13 α12 α 11 α10 α9 α8 α7 α6 α5 α4 α3 α2 α1

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Figure 3. Trajectories of harmonic elimination solutions for various modulation index. (a) M=3. (b) M=11. (c) M=17.

Figure 4. Block diagram of the FPGA-based HEPWM generator. Oscillator-II 40k~400kHz

Phase angle counter

HB

LB

Phase angle transformation Oscillator-I 10MHz

Finite state machine (FSM)

EPROM reader Dead time control

φ 90

Enable

td

Figure 5. Block diagram of the clock control circuit.

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Since the pulses generated by the oscillator-II are accumulated as the phase angle, the VSI output frequency is adjustable while varying the output frequency of the oscillator-I. Another advantage of the phase angle counter is that the circulative counting with auto-reset capability is analogous to the vector control in the polar coordinate. The overflow problem while accumulating the clock pulses is therefore can be avoided. The first-two positions of the output digits of phase angle counter herein denotes as highorder bits (HB) and the remainder as the low-order bits (LB), as shown in Fig. 5. The symmetric property of the HEPWM waveform is advantageous to reduce the memory need for the EPROM. In Fig. 6, it is clear that the LB is in charge of the phase angle in the range of 0 to π/2, only the LB and the modulation index are needed to be scheduled as the address inputs for the EPROM. In order to determine the switching patterns, a logic circuit was proposed to read the stored data circularly. The first step of this control logic is to transform a one-cycle phase angle within the 0 to π/2 interval. The phase angle output (φ90) of the clock control circuit can be expressed by truth table as follow:

ctrl = '1' AND td