Elektrotehniˇski vestnik 69(5): 247–252, 2002 Electrotechnical Review, Ljubljana, Slovenija
Basic Characteristics of FIFO Packet Switches Peter Homan, Janez Beˇster, Tomaˇz Slivnik, Andrej Kos University of Ljubljana, Faculty of Electrical Engineering, Trˇzaˇska 25, 1000 Ljubljana, Slovenia E-mail:
[email protected] Abstract. In this paper we compare characteristics of different FIFO packet switch types. In accordance with our expectations, the best results are obtained by using the output-queued packet switches. The main drawback of these switches is the need for a fast switching fabric. This can be avoided by using the input-queued packet switches, whose performance depends upon individual packet sizes. Characteristics of the input-queued packet switches are similar to those of the output-queued packet switches; if fixed-size packets are transferred, the consequences of the output-contention problem are relatively small. Transfer of the variable-size packets in the input-queued switches is more complicated. Practically, a 100% throughput can be achieved if an asynchronous switching fabric is applied. Packet delays are in this case comparable to those in the output-queued packet switches. The drawback of such switches is the inability to differentiate among multiple service classes. On the other hand, by using a synchronous switching fabric, a 100% switch throughput of cannot be achieved. Another disadvantage of the synchronous packet switches are relatively high packet delays. However, usage of such switches enables a differentiation between multiple service classes, that is one of the conditions for enabling quality of service. Key words: packet switch, output and input queuing, fixed and variable packet size
Osnovne karakteristike paketnega stikala FIFO Povzetek. V cˇ lanku primerjamo karakteristike razliˇcnih tipov paketnih stikal FIFO. Po priˇcakovanjih dobimo najugodnejˇse rezultate ob uporabi paketnih stikal z izhodnim cˇ akanjem. Slabost teh paketnih stikal se kaˇze v zahtevi po uporabi hitrih stikalnih matrik. Tej zahtevi se lahko izognemo z uporabo paketnih stikal z vhodnim cˇ akanjem. Lastnosti teh paketnih stikal so odvisne od velikosti posameznih paketov. Pri prenosu paketov stalne velikosti so lastnosti paketnih stikal z vhodnim cˇ akanjem primerljive z lastnostmi paketnih stikal z izhodnim cˇ akanjem - vpliv konfliktov, do katerih prihaja pri vzpostavljanju poti skozi stikalno matriko, je relativno majhen. Pri prenosu paketov spremenljive velikosti se stvari zapletejo. Ob uporabi asinhronega delovanja stikalne matrike doseˇzemo tako rekoˇc 100 odstotni izkoristek stikalnih kapacitet in zakasnitve, ki so primerljive z zakasnitvami v paketnih stikalih FIFO z izhodnim cˇ akanjem. Slabost asinhronega delovanja se kaˇze v nezmoˇznosti loˇcevanja storitvenih razredov. Ob uporabi sinhronega delovanja stikalne matrike je izkoristek stikalnih zmogljivosti manjˇsi od 100 odstotkov, v naˇsem primeru pribliˇzno 75-odstoten. Poleg tega dobimo od uporabi sinhronega delovanja velike zakasnitve paketov. Prednost sinhronega delovanja v primerjavi z asinhronim se kaˇze v zmoˇznosti loˇcevanja storitvenih razredov, kar je pogoj za uˇcinkovito zagotavljanje kakovosti storitev. Kljuˇcne besede: paketno stikalo, izhodno in vhodno cˇ akanje, stalna in spremenljiva velikost paketov
1
Introduction
Queues in packet switches are required in order to preserve temporary blocked packets. There exist different Received 20 February 2002 Accepted 18 July 2002
queue types. They can be classified according to packet insertion and packet removal procedures. In most cases, the so-called FIFO (First-in First-out) queues are used. This is mainly because of their simple and inexpensive implementation [1,2]. In such queues, a packet is always inserted at the end of the queue and removed from the beginning of the queue. The FIFO packet switches are switches, in which only FIFO queues are implemented. The FIFO packet switches are composed of the following elements: • input and output ports, • classifier, assuring correct classification and insertion of newly received packets into appropriate FIFO queues, • scheduler, responsible for removal of packets from the queues and for control of the switching fabric, • FIFO queues, • switching fabric, enabling the transfer of packets from the input ports to the selected output ports. Non-blocking switching fabrics are usually implemented in contemporary packet switches [3]. They are capable of a concurrent packet transfer from all input ports, provided that each packet is then transfered to a different output port. Depending on the location of FIFO queues [2], FIFO packet switch types can be roughly divided into two categories:
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• input-queued packet switches, where all queues are located at the switching fabric input ports, • output-queued packet switches, where all queues are located at the switching fabric output ports. In this paper we deal with a comparison of basic characteristics of different FIFO packet switch types. Outputqueued and input-queued FIFO packet switches are presented in Sect. 2 and Sect. 3, respectively. In Sect. 4, a methodology used during the switch performance analysis is presented. Simulation results are presented in Sect. 5 and Sect. 6. The main implications are summarized in Sect. 7.
2
Output queuing
Newly received packets are immediately transferred across the switching fabric in output-queued packet switches. Switching fabric speedup is required in order to achieve such delay-free packet transfer. The switching fabric speedup factor is typically equal to the number of input ports in a packet switch and is N [2]. Possible conflicts, which arise when multiple packets from different input ports all want to go to the same output port at the same time, are eliminated. It is therefore possible to achieve a 100% switch throughput, regardless of the selected queue configuration and scheduling mechanism. Fig. 1 depicts a typical structure of the output-queued FIFO packet switch. The total number of N FIFO queues iisncluded in this switch, one at each output port.
Figure 1. Output-queued FIFO packet switch, N = 2
3
Input queuing
Figure 2. Input-queued FIFO packet switch, N = 2
No switching fabric speedup is required in the inputqueued packet switches [2]. However, packet-scheduling
procedure becomes more complicated. When new connections are to be established across the switching fabric, conflicts between different input ports cannot be avoided. This is so, even if a non-blocking switching fabric is implemented. Such events are called output contention. The selected queue configuration has a major influence on both packet switch price and performance. In the simplest configuration, a single FIFO queue can be attached to each input port, as presented in Fig. 2. By using such configuration, a problem known as HOL (Head of Line) blocking appears [4]. The packet at the head of a queue is compelled to wait if the selected output port is busy. All subsequent packets inside this FIFO queue are blocked as well. It is shown [4] that the maximum throughput of such switches is limited to 58.6%. This result was obtained by using fixed-size packets and homogenous and uniform traffic sources. If variable-size packets with an exponential packet size distribution are transferred, the maximum switch throughput drops to no more than 50% [5]. Modifying queue configuration [2] can increase the maximum switch throughput. VOQ (Virtual Output Queuing) queue configuration is usually implemented [4]. In VOQ, there are multiple queues at each input port, one for each output port, as depicted in Fig. 3. Altogether there are N 2 queues inside a packet switch. By using the VOQ queue configuration, the HOL blocking effect can be entirely eliminated. That is because within each individual FIFO queue, all packets are destined to the same destination.
Figure 3. Input-queued FIFO packet switch, VOQ queue configuration, N = 2
Packets can be scheduled and transferred across the switching fabric in two different ways, either synchronously or asynchronously [6]. In a synchronous mode, connections through the switching fabric between all input and output ports are set-up and torn-down at a single instance of time. Synchronous packet scheduling is performed in uniform time intervals T and is especially appropriate for the transfer of fixed-size packets. For variable-size packets, asynchronous packet scheduling is more appropriate. In this case, connections through the switching fabric between input and output ports are setup and torn-down one by one, in an asynchronous way, immediately after a packet has arrived in the switch or after a packet has been transferred across the switching fabric.
Basic Characteristics of FIFO Packet Switches The situation is more complex if variable-size packets are transferred across a synchronous packet switch. Switching fabric transfer speed C is of a constant value, while packet size P varies from packet to packet. The length of the time slot T must be at least as long as it takes to transfer the maximum size packet across the switching fabric. Thus, maximum packet size Pmax must be set in advance and must not be exceeded. Time slot length T must be set to no less than Pmax /C seconds. The analysis in [6] shows that the maximum throughput of such packet switches cannot reach 100%. The exact throughput number depends upon the packet size distribution function.
4
Methodology
Simulated packet switches are composed of N = 10 input and output ports. We use a non-blocking switching fabric. In all simulated input-queued packet switches a VOQ queue configuration is implemented. Implementing a scheduling mechanism in the outputqueued packet switches is a trivial task, since a single FIFO queue per output port (single service class) is used. In the input-queued packet switches connections must be established through the switching fabric in such a way that no output-contention can occur. Several solutions exist for this problem. We decided to use OPF (Oldest Packet First) [4] scheduling algorithm, which performs well, according to our experiences. The age of an individual packet is defined by the delay of this packet inside FIFO queues; older the packet, higher the priority. Each input port is fed by its own independent traffic source. Packets output ports are defined in a random and uniform manner, i.e. all output ports are presented with an equal probability. Exponential packet inter-arrival times are assumed. Two different traffic sources are used in our simulations. All packets have the same, unvariable size in the first traffic source. In the second traffic source, the packet size varies between specified minimum and maximum values - an uniform packet size distribution is assumed. Throughout our simulations, normalised units are used. All packets have normalised size 1 in the first traffic source. The minimum packet size is set to 1 and the maximum packet size is set to 10 in the second traffic source. The normalised transfer speed of all input lines, switching fabric and output lines is set to 1. An exception is the transfer speed of the switching fabric in output-queued packet switches, which is set to infinity. Thus, a single normalised time unit is needed in order to transmit or receive a single minimum size packet. The size of the FIFO queues is also expressed in relative units. For example, in a queue with a normalised size 100, no more than 100 packets can be accommodated at a time. Simulation results, presented in this paper, were obtained using Modsim III, an object-oriented simulation
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language from CACI. Simulation results were obtained by simulating the steady-state behaviour of these systems and by applying the replication method, as explained in [7]. Simulations were repeated until performance measures for switch throughput and average packet delay achieved or exceeded the required level of relative precision (1%), at a 95% confidence level. During each simulation, executions of at least 106 packets were generated, setting the minimum detectable packet loss probability to 10−6 . In order to simplify the presentation of the simulation results, a special notation was applied. This notation enables readers to promptly identify, which packet switch type has been simulated and which traffic source type has been used in the simulations. The following packet switch types are defined: • O, for the output-queued FIFO packet switch, • S, for the synchronous input-queued FIFO packet switch, • A, for the asynchronous input-queued FIFO packet switch. The following label is located in front of the packet switch type label to indicate the selected traffic source type: • F, if fixed-size packets have been generated, • V, if variable-size packets have been generated. For example, a VS packet switch is a synchronous inputqueued FIFO packet switch whose characteristics have been tested for variable-size packets.
5
Comparison of FO and FS packet switches
FO and FS packet switches are compared in this chapter. The total capacity of all queues in each simulated packet switch amounts to 10000 normalised units. There are N queues inside each FO packet switch and individual queue size is set to 1000 units. On the other hand, there are N 2 queues inside each FS packet switch and individual queue size is set to 100 units. Table 5 presents the measured average packet delays versus the offered switch load for both simulated packet switch types. Generally speaking, we can conclude that the average packet delays in the FS packet switches are approximately twice as high as the average packet delays in the FO packet switches. Switch type FO FS
50 1.6 2.4
Offered load % 60 70 80 90 1.8 2.2 3.2 6.1 3.0 4.1 6.4 13.5
100 39 67
Table 1. Average packet delay versus the offered switch load
Table 5 presents the measured maximum packet delays versus the offered switch load for both simulated
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packet switch types. The maximum packet delay values are similar in both packet switches if offered switch load is set low or moderate. Only when the offered switch load is set high, the differences between the maximum packet delays in FO and FS packet switches become noticeable. Switch type FO FS
50 8.3 8.7
60 10.2 12.1
Offered load % 70 80 90 17.7 33 110 19.6 37 117
100 190 230
Table 2. Maximum packet delay versus the offered switch load
Comparing the FO and FS packet switches, we came to the following conclusions. A 100% switch throughput can be achieved in both FO and FS packet switches. The simulation results revealed a 99.1% throughput in the FO packet switches and a 98.5% throughput in the FS packet switches. The packet loss probability is kept low (< 10−6 ) in both simulated packet switches, if the offered switch load is kept below the maximum switch throughput. While increasing the offered switch load, packet losses appear a bit sooner in the FS packet switches in comparison to the packet losses in the FO packet switches. The average packet delays in the FS packet switches are approximately twice as high as the average packet delays in the FO packet switches. The maximum packet delays are similar in both simulated packet switches. Differences do appear only when the offered switch load is set high. The maximum packet delays in the FO packet switches are in this case several 10% lower in comparison to the maximum packet delays in the FS packet switches.
6
Comparison of VO, VA and VS packet switches
VO, VA in VS packet switches are compared in this chapter. The total capacity of all FIFO queues inside each packet switch is set to 20000 normalised units. There are N FIFO queues inside each VO packet switch, which amounts to 2000 units per queue. On the other hand, there are N 2 FIFO queues inside each VA and VS packet switch, which amounts to 200 units per queue. Figure 4 depicts simulation results for the switch throughput versus the offered switch load for all three simulated packet switch types. A 100% switch throughput can be achieved in both VO and VA packet switches. A 100% switch throughput cannot be expected in VS packet switches, which is in line with the theoretical results obtained in [6]. In simulation, a maximum switch throughput of 74.7% was measured for the VS packet switch. Figure 5 depicts simulation results for the packet loss probability versus the offered switch load for all three
Figure 4. Switch throughput versus the offered switch load
simulated packet switch types. The lowest packet loss probability was measured in the VO packet switches. Somewhat higher packet loss probability was detected in the VA packet switches. The measured packet loss probability in the VS packet switches is in accordance with the surplus of the offered switch load. There is a relatively swift transition between the area with no detected packet loss event and the area where the maximum switch throughput is achieved and where the packet loss probability complies with the surplus of the offered switch load. Packet loss events were not detected until the offered switch load was only a few percents below the maximum switch throughput.
Figure 5. Packet loss probability versus the offered switch load
Figure 6 depicts simulation results for average packet delay versus the offered switch load for all three simulated packet switch types. Table 6 presents the same results in a tabular form. Average packet delays in the VS packet switches are several 100% higher in comparison to the average packet delays in the VO and VA packet switches. Average packet delays in the VA packet switches are only a few 10% higher in comparison to the average packet delays in the VO packet switches. A noticeable differences in average packet delay values of VO and VA packet switches do not appear until the offered switch load is high. Figure 7 depicts simulation results for the maximum packet delay versus the offered switch load for all three simulated packet switch types. Table 6 presents the same results in a tabular form. Similar to the previous figure, there is a rapid increase in the maximum packet delay values in the VS packet switches. This delay increase appears when the offered switch load reaches the maxi-
Basic Characteristics of FIFO Packet Switches
Figure 6. Average packet delay versus the offered switch load
Switch type VO VA VS
30 7.5 8.0 21.9
Offered load % 50 70 9.4 13.7 11.7 20.6 53.4 257
80 19.2 32.2 2063
Table 3. Average packet delay versus the offered switch load
mum switch throughput. Maximum packet delay values in the VS packet switches are approximately 100% higher in comparison to the maximum packet delay values in the VA packet switches. The maximum packet delay values in VA packet switches are approximately 100% higher in comparison to the maximum packet delay values in the VO packet switches.
Figure 7. Maximum packet delay versus the offered switch load
Switch type VO VA VS
30 54 80 110
Offered load % 50 70 80 70 119 126 350 507 213 1041 2577
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operation mode of the switching fabric. The influence of the OPF algorithm is thus minimal. The combination of random scheduling and the high offered switch load can cause temporary starvation of individual queues, which in term results in high maximum packet delay values. On the other hand, the synchronous operation mode of the switching fabric in the VS packet switches enables the OPF algorithm to take full control of the packet scheduling procedure. This in turn prevents the starvation of individual queues and results in lower maximum packet delay values. As can be seen in Fig. 7, there are lower maximum packet delay values in the VS packet switches in comparison to the maximum packet delay values in the VA packet switches, if the offered switch load is 100%. The maximum possible packet delay in the VS packet switches is always limited by the size and number of the FIFO queues inside the switch and by the maximum packet size. Comparing the VO, VA, and VS packet switches, we came to the following conclusions. The lowest switch throughput value, 74.7%, is achieved in the VS packet switches. In VO and VA, packet switches of a practically 100% switch throughput can be achieved. The simulation results revealed a 99.8% switch throughput in the VO packet switches and 99.0% switch throughput in the VA packet switches. Packet loss probability is kept low (< 10−6 ) in all simulated packet switches, if the offered switch load is kept below the maximum switch throughput. A high maximum packet delay can occur in the VA packet switches, if the offered switch load is set high. The maximum possible packet delay in the VS packet switches is always limited by the size and number of embedded FIFO queues and by the maximum packet size. The increment of the offered switch load results in a higher packet loss probability, whereas the maximum packet delay is not increased. The average packet delay values in the VS packet switches are several 100% higher in comparison to the average packet delay values in the VA packet switches. The average packet delay values in the VA packet switches are only a few 10% higher in comparison to the average packet delay values in the VO packet switches. The maximum packet delay values in the VS packet switches are approximately 100% higher in comparison to the maximum packet delay values in the VA packet switches. The maximum packet delay values in the VA packet switches are approximately 100% higher in comparison to the maximum packet delay values in the VO packet switches.
Table 4. Maximum packet delay versus the offered switch load
The advantage of the VS packet switches in comparison to the VA packet switches is seen if the offered switch load is high. Although the scheduling procedure in the VA packet switches is set to work according to the OPF algorithm, new packets are actually scheduled on a predominantly random basis, because of the asynchronous
7
Conclusions
A comparison of basic characteristics of different FIFO packet switch types is presented in this paper. Simulations of both input-queued and output-queued packet switches were performed. Both fixed-size and variable-size packets were used in two different traffic sources.
Simulation results confirmed the anticipated superior characteristics of the output-queued packet switches, regardless of whether fixed-size or variable-size packets were generated by the traffic sources. The transfer of fixed-size packets in the input-queued packet switches performed flawlessly. The influence of the output contention turned out to be relatively small and is predominantly affecting the average packet delay values. The maximum packet delay values are not significantly affected. We showed that a 100% switch throughput can be expected in such packet switches. The transfer of the variable-size packets in the inputqueued packet switches turned out to be more difficult. The switching fabric operation mode is of key importance. The synchronous operation mode results in a lower maximum switch throughput and higher packet delay values. On the other hand, the asynchronous operation mode results in high maximum packet delay values, if the offered switch load is high. The following combinations can be used for the transfer of variable-size packets in input-queued packet switches: in LAN (Local Area Networks) with relatively low transmission speeds and high number of switch ports, two solutions can be used. The first one anticipates the usage of an asynchronous switching fabric. This solution is appropriate for networks with a single service class. The second solution anticipates the usage of a special SAR (Segmentation and Reassembly) function in combination with a synchronous packet switch for fixed-size packets. This solution enables service class differentiation, which in term enables different quality of service for different traffic flows. In reality, SAR functions have a limited capacity [3], making them inappropriate for implementation in high speed networks. In the WAN (Wide Area Networks) networks with relatively high transmission speeds and a low number of switch ports, synchronous operation of the switching fabric for the transfer of variable-size packets is more appropriate. High transmission speeds provide for low queuing delays and the synchronous operation mode provides for service class differentiation. Simulation results were obtained by using relatively simple traffic sources. Traffic sources in real packet networks are usually bursty or even fractal [8]. Further simulations with more real-like traffic sources are required in order to obtain more accurate assessments of packet switch characteristics.
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References [1] W. Stallings, High-Speed Networks: TCP/IP and ATM Design Principles, New Jersey, USA, Prentice Hall Inc., 1998. [2] N. Giroux, S. Ganti, Quality of Service in ATM Networks, New Jersey, USA, Prentice Hall Inc., 1999. [3] C. Partridge, P. P. Carvey, E. Burgess et.al, A 50 Gbit/s IP Router, IEEE/ACM Transactions on Networking, vol.6, no.3, pp.237-248, June 1998.
[4] N. McKeown, A. Mekkittikul, V. Anantharam, J. Walrand, Achieving 100% Throughput in an Input-Queued Switch, IEEE Trans. Commun., vol.47, no.8, pp.1260-1267, August 1999. [5] J. S. C. Chen, T. E. Stern, Throughput Analysis, Optimal Buffer Allocation, and Traffic Imbalance Study of a Generic Nonblocking Packet Switch, IEEE Journal on Selected Areas in Commun., vol.9, no.3, pp.439-449, April 1991. [6] P. Giacomazzi, Maximum Throughput Analysis of a Datagram Switch for Broadband Networks, IEICE Trans. Commun., vol.E81-B, no.2, pp.354-362, February 1998. [7] H. Akimaru, K. Kawashima, Teletraffic: Theory and Applications, 2nd edn, Berlin, Germany, Springer-Verlag, 1999. [8] Z. Sahinoglu, S. Tekinay, On Multimedia Networks: SelfSimilar Traffic and Network Performance, IEEE Communications Magazine, vol.37, no.1, pp.48-52, January 1999. Peter Homan graduated in 1995. He received his M. Sc. and Ph. D. degrees in the field of telecommunications from the University of Ljubljana, Slovenia, in 1998 and 2001, respectively. At present, he is employed as a Senior Researcher at the Faculty of Electrical Engineering in Ljubljana. His previous work involved development of the telecommunication signalling software (CCS No. 7), with emphasis on intelligent networks (IN). His current work and study focuses on IP, B-ISDN and ATM networks, with a particular emphasis on quality of service (QoS) issues. He is also a member of the IEEE and an associate member of the IEICE. Janez Beˇster graduated in 1979. He received his M. Sc. and Ph. D. degrees in the field of telecommunications from the University of Ljubljana, Slovenia, in 1982 and 1995, respectively. Currently he is Head of the Laboratory for Telecommunications at the Faculty of Electrical Engineering in Ljubljana and Assistant Professor for subjects, such as Telecommunication Basics II, Commutation Systems and Networks, Communication Networks and Services, Design, Modelling and Management of Telecommunication Networks and Intelligent Networks. Twenty years of his research and development activities, as well as teaching, have focused on the field of planning, realization and management of telecommunication systems and services, together with the application of information technologies in education. His current work involves research and engineering in the fields of IP, ATM, TM (Telemanagement) and IIN (Integrated Intelligent Networks). He is also a member of the IEEE and ACM as well as an associate member of the IEICE. Tomaˇz Slivnik received his B. Sc., M. Sc. and Ph. D. degrees in the field of Electrical Engineering from the University of Ljubljana, Slovenia, in 1971, 1973 and 1975, respectively. In 1975, he was granted a B. Sc. degree in Mathematics from the University of Ljubljana. Currently he is Professor of Mathematics and Electrical Engineering at the Faculty of Electrical Engineering in Ljubljana. His research interests include mathematical analysis, electromagnetic field calculations, microprocessor applications as well as analysis of telecommunication networks. He is also a member of the IEEE. Andrej Kos graduated from the University of Ljubljana, Slovenia, in 1996 and was awarded his M. Sc. degree in the field of telecommunications in 1999. At present, he is employed as a Senior Researcher at the Faculty of Electrical Engineering in Ljubljana and is currently working on his Ph.D. He has extensive research and industrial experience in the design and analysis of advanced telecommunications systems and networks. His current work and research are focused on the next generation element and network designs, especially in the field of packet switching and Internet protocol suite, including multiprotocol label switching and asynchronous transfer mode networks. Other fields of his expertise include mobile communications, telemanagement and telecommunication signalling software (CCS No. 7). He is also a member of the IEEE and TM Forum.
