Capacitive Power Transfer System with Reduced Voltage ... - MDPI

applied sciences Article

Capacitive Power Transfer System with Reduced Voltage Stress and Sensitivity Tarek M. Mostafa 1, * 1 2

*

ID

, Dai Bui 2

ID

, Aam Muharam 1 , Reiji Hattori 1 and Aiguo Patrick Hu 2

ID

ASEM, Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Fukuoka 816-8580, Japan; [email protected] (A.M.); [email protected] (R.H.) Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New Zealand; [email protected] (D.B.); [email protected] (A.P.H.) Correspondence: [email protected]; Tel.: +81-90-6303-7345

Received: 13 June 2018; Accepted: 9 July 2018; Published: 12 July 2018

Featured Application: In this paper, we introduce a wireless power transfer system based on electric field coupling (capacitive coupling) with less voltage across the coupling interface and circuit quality factor by using a DC–DC converter, which resulted in a safer and less sensitive system while maintaining sufficient delivered power and high efficiency. The introduced system has a wide application range with different power needs and transmission distances, such as charging mobile devices including mobile phones, pads, laptops, drones, cameras, and wireless sensors. The system use can also be extended to supplying power to robots, smart walls, screens, lighting, indicative signs, and oil and gas applications. Abstract: This paper introduces a DC–DC buck converter on the secondary side of the capacitive power transfer system to reduce the voltage and electric field across the interface, and to reduce the circuit Q, and thus the system sensitivity. The system is mathematically analyzed to study the improvement in sensitivity and voltage stress. The leakage electric field emissions around the plates are investigated by simulation. The analytical and simulation results show that by reducing the duty cycle of the buck converter at a constant output power, the voltage across the plates can be significantly reduced and the circuit becomes less sensitive to the variations in parameters. Experimental results demonstrated that Q and the voltage stress over the capacitive interface are reduced by changing the duty cycle of the buck converter. For delivering 10 W of power, the maximum voltage stress across one pair of the coupling plates is reduced from 211 V in the conventional system without using a DC–DC converter, to 65 V and 44 V at duty cycles of 30% and 20%, respectively. The system achieves an end-to-end power efficiency of 80% at an output power of 10 W and a duty cycle of 30%. Keywords: capacitive wireless power transfer; DC–DC buck converter; quality factor; voltage stress; wireless power transmission

1. Introduction Since the 1890s, efforts have focused on the wireless transfer of power [1], and the most successful approach has been inductive power transfer (IPT), which is based on magnetic field coupling. Inductive power transfer has been widely used for powering industrial machines [2,3], charging mobile devices [2,4] and electric vehicles [5,6], and powering biomedical implants [7]. However, IPT has clear limitations with regard to high eddy current losses to the surroundings especially with metals, high standing losses, and complicated design, requiring bulky and expensive magnetic materials and electromagnetic interference (EMI) shielding [8,9]. Also, given its nature, IPT is unable to transfer power across metal barriers. Capacitive power transfer (CPT), a technology that uses a Appl. Sci. 2018, 8, 1131; doi:10.3390/app8071131

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varying electricelectric field tofield transfer power, has beenhas introduced as a goodasalternative to IPT forto near uses a varying to transfer power, been introduced a good alternative IPTfield for power transfer due to its unique features, such as design flexibility of coupling structure, ability to near field power transfer due to its unique features, such as design flexibility of coupling structure, transfer across electrically isolated metal barriers, low standing losses and EMI,and andEMI, low and cost ability topower transfer power across electrically isolated metal barriers, low standing losses and weight [10–14]. Capacitive power transfer can be used in various applications, such as integrated low cost and weight [10–14]. Capacitive power transfer can be used in various applications, such as circuits (IC) [15], biomedical devices [16], consumer electronics [11,12,17–19], and electric integrated circuits (IC) [15], biomedical devices [16], consumer electronics [11,12,17–19], andvehicles electric (EVs) [20]. vehicles (EVs) [20]. The conventional conventional CPT CPT system system is is illustrated illustrated in in Figure Figure 1, 1, where where the thecapacitive capacitive interface interface is istypically typically The in the the range (pF) when thethe plates are are almost touching withwith an insulation layer in range of ofhundreds hundredsofofpicofarads picofarads (pF) when plates almost touching an insulation in between and 1–2 mm air gap, and few tens of picofarads when there is a wide air gap, e.g., 150 mm layer in between and 1–2 mm air gap, and few tens of picofarads when there is a wide air gap, e.g., to 300 mm air gap is usually considered for EV charging applications [21]. This results in a high-quality 150 mm to 300 mm air gap is usually considered for EV charging applications [21]. This results in a factor and voltage across the capacitive interface. For interface. example, For if theexample, operating frequency f is high-quality factor stress and voltage stress across the capacitive if the operating 1 MHz, the load resistance R is 12.3 Ω, the capacitive interface C = C = 2C = 1 nF and the tuning c1 c2 c L resistance RL is 12.3 Ω, the capacitive interface Cc1 = Cc2 = 2Cc = 1 nF and frequency f is 1 MHz, the load 2 ∼ inductor L is 50.7 µH, which provides quality [22] Qconv[22] of 8/π (sqrt(L/C c )) = c32 2RL (sqrt(L/C the tuning inductor L is 50.7 μH, which the provides thefactor quality factor Qconv R ofL 8/π )) ≅and 32 provides the maximum voltage stressstress acrossacross the single pair ofpair the of capacitive interface Vc_conv V ofc_conv 320of V and provides the maximum voltage the single the capacitive interface for an AC input voltage V of just 20 V. Consequently, practically attaining tuning is challenging, in_conv Vin_conv of just 20 V. Consequently, practically attaining tuning is 320 V for an AC input voltage and the system is highly sensitive to coupling and variation load change. voltage challenging, and the system is highly sensitivevariation to coupling and The loadhigh change. The stress high across the coupling interface increases the probability of dielectric breakdown and sparks occurrence. voltage stress across the coupling interface increases the probability of dielectric breakdown and In addition, systemIn safety becomes an issue as becomes the related field emissions around the sparks occurrence. addition, system safety anleakage issue aselectric the related leakage electric field plates increase beyond the safety margins will be detailed 4. Theseinmatters in emissions around the plates increase beyondas the safety margins in as Section will be detailed Section result 4. These lower efficiency, decreased ability to deliver power, and increased difficulty in offering commercially matters result in lower efficiency, decreased ability to deliver power, and increased difficulty in acceptedcommercially systems. offering accepted systems.

Figure 1. The conventional capacitive power transfer (CPT) system. Figure 1. The conventional capacitive power transfer (CPT) system.

Previous studies introduced a partial solution for the previously mentioned issues [10,21,23–25]; Previous studies introduced a partial solution forissues the previously mentioned issues [10,21,23–25]; however, no comprehensive design overcomes both simultaneously. For instance, one pulse however, no comprehensive design overcomes both issues simultaneously. For instance, pulse switching active capacitor (OPSAC) was proposed to overcome the sensitivity issue [24]; one however, switching capacitor and (OPSAC) was proposed to overcome the sensitivity issue [24]; however, the systemactive is complicated the voltage stress across the coupling interface is high. Tuning the the system is complicated and the voltage stress across the coupling interface is high. Tuning the operating frequency [25] is an effective method to mitigate the sensitivity issue and even with a highoperating frequency [25] is an effective method to mitigate the sensitivity issue and even with quality factor, the system can still transfer the power with high efficiency, but by changing thea high-quality factor, the system can still transferchallenging the power with efficiency, but by changing the frequency, following the regulations becomes and high the design is complex, costly, and frequency, following the regulations becomes challenging and the design is complex, costly, and cannot cannot avoid the high voltage stress. avoid voltage stress. Inthe thishigh paper, a CPT system with a DC–DC buck converter on the secondary side is introduced In this paper, a CPT withsensitivity a DC–DCand buck on theacross secondary side is introduced to simultaneously reduce system the system theconverter voltage stress the capacitive interface. to simultaneously reduce the system sensitivity and the voltage stress across the capacitive The proposed system can also keep the leakage electric field low, which improves the safetyinterface. of CPT The proposed system can also keep the leakage electric field low, which improves the safety of systems. CPT The systems. rest of the paper is arranged as follows. Section 2 describes the structure of the proposed CPT system. The mathematical model and analysis are covered in Section 3. In Section 4, the leakage electric field simulation is outlined. A prototype is implemented for evaluation in Section 5. The conclusions are drawn in Section 6.

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The rest of the paper is arranged as follows. Section 2 describes the structure of the proposed CPT system. The mathematical model and analysis are covered in Section 3. In Section 4, the leakage electric field simulation is outlined. A prototype is implemented for evaluation in Section 5. The conclusions are drawn in Section 6. Appl. Sci. 2018, 8, x FOR PEER REVIEW

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2. Proposed System Structure

2. Proposed System Structure

The structure of the proposed CPT system is shown in Figure 2a. Switches (S1 –S2 ) construct a The structure of the proposed CPT system is shown in Figure 2a. Switches (S1–S2) construct a half-bridge inverter (full bridge to convert convertDC DCinput input voltage ansignal. AC signal. D ) into half-bridge inverter (full bridgecan canbe be used) used) to voltage (VD )(Vinto an AC Inductor L is placed in series to compensate for the interface, where Cc1 and c2 represent Inductor L is placed in series to compensate forcapacitive the capacitive interface, where Cc1 C and Cc2 the capacitive coupling interface. Diodes (D1 –D the full wave rectifier to obtain voltage. represent the capacitive coupling interface. Diodes (D1 –D4 ) construct the full wave rectifier to DC obtain 4 ) construct The DC–DC buck converter supplies the voltage currentand to the load.to the load. DC voltage. The DC–DC buck converter suppliesand the voltage current

(a)

(b)

(c) Figure 2. The proposed system: (a) CPT system with a DC–DC buck converter; (b) circuit simplification

Figure 2. The proposed system: (a) CPT system with a DC–DC buck converter; (b) circuit simplification by the sinusoidal approximation, and (c) equivalent circuit used for analysis. by the sinusoidal approximation, and (c) equivalent circuit used for analysis.

3. Mathematical Modelling and Analysis

3. Mathematical Modelling and Analysis

For analysis, the system topology of Figure 2a was rearranged assuming the parasitic resistances Forneglected analysis,for theallsystem topology of Figure 2a was the parasitic resistances are components, as shown in Figure 2c. rearranged The inverter assuming in Figure 2a produces a square wave voltage. This voltage is applied to the input terminal of theinverter resonantin circuit. The circuit are neglected for all components, as shown in Figure 2c. The Figure 2aresonant produces a square frequency is tuned to the fundamental component of the inverter square wave, i.e., to the switching wave voltage. This voltage is applied to the input terminal of the resonant circuit. The resonant frequency f. As a result, the resonant circuit current and the resonant circuit output voltage and current have essentially sinusoidal waveforms at the fundamental frequency f, with negligible

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circuit frequency is tuned to the fundamental component of the inverter square wave, i.e., to the switching frequency f. As a result, the resonant circuit current and the resonant circuit output voltage and current have essentially sinusoidal waveforms at the fundamental frequency f, with negligible harmonics. Accordingly, the sinusoidal approximation was first considered where Vin can be obtained from Equation (1), as shown in Figure 2b. The two series interface capacitances were replaced by Cc as shown in Equation (2). The series compensation inductor L is obtained from Equation (3). The equivalent AC load R [26], assuming the rectifier and the buck converter are ideal, is described in Equation (4). Vin =

2V d sin(ωt), π

(1)

Cc1 C c2 , Cc1 + C c2

(2)

1 , Cc ω 2

(3)

Cc = L = R =

8 D2 π 2

RL =

Rload , D2

(4)

where ω is the angular switching frequency; Rload is the effective load resistance at the AC side; which is equal to 81% of the actual load resistance RL at the DC side after the rectifier; and D is the buck converter duty cycle. The values in Table 1 were used as a design example to prove the concept. Table 1. Parameters used for modelling. Parameter

Unit

Value

Pload f Cc1 = C c2 = 2Cc L Rload

Watt MHz nF µH Ω

10 1 2 25 10

The equivalent circuit shown in Figure 2c would not be applicable for analysis if the cross coupling or the leakage capacitance is too high due to the complicated coupling configuration [27] or if the operating frequency is increased to a very high level. In these cases, more accurate modelling [14] for the capacitive interface should be used. To fairly compare the system sensitivity and the voltage stress over the capacitive coupling interface in the proposed system and the conventional system previously described, we assumed that the same amount of power was delivered to the load and the input voltage would change according to the value of the duty cycle (D) of the buck converter. When D was 100% represented the conventional system. Figure 3 shows the needed input voltage for the design example to deliver 10 W to the load depending on D, as shown in Equations (5) and (6): Vin =

Vin_conv . D

(5)

VD =

VD_conv , D

(6)

From Equation (1), we obtain:

where VD and Vin are the DC input voltage and AC input voltage needed to deliver a specific amount of power to the load, respectively. The DC input voltage and AC input voltage for the conventional system are represented by VD_conv and Vin_conv , respectively.

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Figure 3. Input voltage needed to deliver 10 W to the load and the change in the quality factor of the Figure 3. Input voltage needed to deliver 10 W to the load and the change in the quality factor of the circuit Q with different duty cycles D. circuit Q with different duty cycles D.

3.1. System Sensitivity 3.1. System Sensitivity Figure 4 illustrates the frequency response of the output power with different duty cycles. The Figure 4 illustrates the frequency response of the output power with different duty cycles. instantaneous real power transferred to the load is provided in Equation (7) and the average power The instantaneous real power transferred to the load is provided in Equation (7) and the average in Equation (8). By reducing D, the output will have a wider response that is reflected in lower power in Equation (8). By reducing D, the output will have a wider response that is reflected in sensitivity. The quality factor of the proposed system (Q) as expressed in Equation (9) decreases lower sensitivity. The2 quality factor of the proposed system (Q) as expressed in Equation (9) decreases proportionally to D , as shown in Figure 3. By lowering Q, the sensitivity decreases and tuning at proportionally to D2 , as shown in Figure 3. By lowering Q, the sensitivity decreases and tuning at resonant frequency will be more obtainable practically. For a less sensitive system, we recommend resonant frequency will be more obtainable practically. For a less sensitive system, we recommend using Q ≤ 6, which can be easily achieved by choosing D ≤ 50% for the chosen values of this design using Q ≤ 6, which can be easily achieved by choosing D ≤ 50% for the chosen values of this example. The recommended D will change depending on the situation and the system design design example. The recommended D will change depending on the situation and the system parameters. design parameters. 2 Vin DDs s 2 CcCcRR V in 2 2 C L s + C R s + 1 (7) C Lc s + Ccc R s + ,1 Pload P=load = c , (7) Rload 22 R load 2 2 R22 V 2 ω 2C 2 D 22 2 (8) | = Cc cD R 2Vin2in ω 6 , =load , (8) | Pload ||P 2( L 2R R2load ω 2 Rload + Cc 2 L R Rload ω 6 ) 1s L 2 (9) Q =1 Lc = Qconv D ,2 R C Q= = Qconv D , (9) R Cc where s is jω, Pload is the real power delivered to the load for the CPT system with the DC–DC buck where s is added, jω, Ploadand is the real powerthe delivered the load the CPT system with the DC–DC buck converter Qconv denotes quality to factor of thefor conventional system. converter added, and Qconv denotes the quality factor of the conventional system.

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Figure 4. The frequency response of the output power at different duty cycles D.

Figure 4. The frequency response of the output power at different duty cycles D.

By reducing the 4. system sensitivity, the system’s ability to transfer power becomes Figure The frequency response of the output power at different duty cycles D. impervious to parametric variations. Figure the 5 shows the impacts ontransfer output power changes in the Bylarge reducing the system sensitivity, system’s ability to powerwith becomes impervious to By reducing the system sensitivity, the system’s ability to transfer power becomes impervious capacitive coupling interface. For the conventional system, by changing the interface value by only large parametric variations. Figure 5 shows the impacts on output power with changes in the capacitive to large variations. Figure 5 shows thetoimpacts output powerfrequency with changes the 10% of itsparametric original no power will transfer the loadonand resonance will in vary coupling interface. Forvalue, the conventional system, by changing the interface value by only 10% of its capacitive coupling ForConversely, the conventional system, changing interfaceon value only considerably due to interface. the high Q. by using the by DC–DC buckthe converter the by power original value, no power will transfer to the load and resonance frequency will vary considerably due 10% of its original value, becomes no powerimmune will transfer to the load and and resonance frequency will vary receiving side, the system to parameter changes the ability to transfer the to theconsiderably high Q. Conversely, by high usingQ.the DC–DC buck converter on the power receivingonside, the system due to the Conversely, using the DC–DC buck thecan power power increases even under extreme conditions.byFor instance, if D = 10% is converter used, the power be becomes immune to parameter changes and the ability to transfer the power increases even receiving side, system becomes immune to increase parameter and value the ability to transfer transferred with the almost the same amount for any in changes the interface from 250% more the tounder extreme conditions. instance, if D value = 10% used,For theinstance, power transferred almost thebesame power even under extreme conditions. ifconverter Dbe = 10% is aused, thethe power can 55% lessincreases than theFor original interface byisusing DC–DC buckcan as part with of secondary amount for in the interface 250% more 55% less thanfrom the original interface transferred with the same amount forfrom any increase in thetointerface value 250% more to side. Asany such,increase the almost misalignment issue isvalue of less concern. less than the original interface value by using DC–DC buck converter as a part the secondaryissue value 55% by using DC–DC buck converter as a part of the secondary side. As such, theof misalignment side.concern. As such, the misalignment issue is of less concern. is of less

Figure 5. The tolerance of the output power with the change in the capacitive interface value using different duty cycles D. Figure 5. The tolerance of the output power with the change in the capacitive interface value using Figure 5. The tolerance of the output power with the change in the capacitive interface value using different duty cycles D.

different duty cycles D.

By adding the buck converter, the Q value remained low for any value of the interface, as shown in Figure 6, which guarantees the system robustness. On the contrary, the previous system Q is


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By adding the buck converter, the Q value remained low for any value of the interface, as shown in Figure 6, which guarantees thethe system robustness. previous system Q is By adding the buck converter, Q value remainedOn lowthe for contrary, any valuethe of the interface, as shown susceptible to variations in the coupling interface, especially when the coupling capacitance is reduced susceptible variations in thethe coupling when thethe coupling in Figure 6, to which guarantees system interface, robustness.especially On the contrary, previouscapacitance system Q is to lesssusceptible than 0.5tonF. reduced less than 0.5 nF.in the coupling interface, especially when the coupling capacitance is to variations The load can be abe parameter that affects changesthat thatmay may occur to change the change The load can a parameter that affectsthe thesystem system by by changes occur duedue to the reduced to less than 0.5 nF. in thein battery under charge at the DC level, for example. Figure 7 shows that the Q value is stable theThe battery under charge at the DC level, for example. Figure 7 shows that the Q value is stable and and load can be a parameter that affects the system by changes that may occur due to the change low for a wide range of changes in the load, unlike the case without DC–DC buck converter added low for a wide range of changes in the load, unlike the case without DC–DC buck converter added in the battery under charge at the DC level, for example. Figure 7 shows that the Q value is stable and where Q reaches to than some loadvalues. values. areaches wide range ofmore changes in100 the load, unlike the case without DC–DC buck converter added wherelow thefor Qthe to more than 100 forfor some load where the Q reaches to more than 100 for some load values.

Figure 6. The change in the capacitive interface value effect on the Q value.

Figure 6. The change in the capacitive interface value effect on the Q value. Figure 6. The change in the capacitive interface value effect on the Q value.

Figure 7. Q value change with the load. Figure 7. Q value change with the load.

Figure 7.Interface Q value change with the load. 3.2. Voltage Stress Across the Capacitive 3.2. Voltage Stress Across the Capacitive Interface By having the DC–DC buck converter on the secondary side in the proposed system, the 3.2. Voltage Stress Across the Capacitive Interface equivalent AC load with converter decreasingonD the as expressed Equation Therefore, the input By having the increased DC–DC buck secondaryinside in the(4). proposed system, the voltage had to be boosted accordingly per Equation (5) and the power could be transferred with equivalent AC load increased with decreasing D as expressed in Equation (4). Therefore, the input By having the DC–DC buck converter on the secondary side in the proposed system, the equivalent smaller current (I) to the load in the amount ofintransferred power. The current flowing through voltage had to with be boosted accordingly per Equation (5) and the power could be with had AC load increased decreasing D same as expressed Equation (4). Therefore, thetransferred input voltage smaller current (I) to theper load in the same transferred power. The currentwith flowing through to be boosted accordingly Equation (5)amount and theofpower could be transferred smaller current

(I) to the load in the same amount of transferred power. The current flowing through the interface (I) can be found using Equation (10), which can be expressed as a function of the duty cycle and the interface current of the conventional system at the resonance frequency, as shown in Equation (13).

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The reduction in the current through the circuit results in less voltage stress Vc across the one pair of the coupling plates as described in Equations (11) and (12). Figure 8 that shows how Vc varies Sci. 2018, 8, x FOR PEERDC–DC REVIEW converter. The voltage stress across one pair of the coupling 8 of 16 with Appl. the duty cycle of the plates (Vc ) decreases proportionally with D at the resonant frequency, as given in Equation (14). At low can be expressed as a function of the duty the interface (I) can be found using Equation (10), which frequencies, the terms 2 C c L ω 2 and C c 2 ω 2 R2 + L2 ω 2 can be neglected and Vc can be determined, cycle and the interface current of the conventional system at the resonance frequency, as shown in as shown in Equation (15), which explains the high Vc at the low frequencies. According to these Equation (13). The reduction in the current through the circuit results in less voltage stress Vc across results, of having safety issues or the occurrence sparks and dielectric breakdown is thethe oneprobability pair of the coupling plates as described in Equations (11)ofand (12). Figure 8 that shows how muchVlower, and can be totally neglected if D is sufficiently low. c varies with the duty cycle of the DC–DC converter. The voltage stress across one pair of the coupling plates (Vc) decreases proportionally with D at the resonant frequency, as given in Equation C V 2 2 2 2 ω R +L ω, can be neglected and Vc can be (10) (14). At low frequencies, the termsI 2=Cc L ω2 andcCc 2in 2 Cc L sexplains + Cc Rthes high + 1 Vc at the low frequencies. According determined, as shown in Equation (15), which to these results, the probability of having safety issues or the occurrence of sparks and dielectric I Vin breakdown is much lower, and can be totally if D is sufficiently Vc = = neglected , low. (11) 2

2 Cc s 2 Cc L s + 2 Cc R s + 2 Vin v I = , u Cc L s2 + Cc R s + 1 1 1 u . |Vc | = Vin t 2V 2 2 2 I 2 2 2 = c L ω 2+inC c ω , R + L ω Vc1= − 2 C 2 Cc s

2 Cc L s + 2 Cc R s + 2

If the switching frequency = the resonance frequency, 1 1 |Vc | = Vin 2

1

2 Cc L ω2 +Cc 2 ω2 R2 +L2 ω2

.

(10)

(12) (11) (12)

I = I conv D,

(13)

If the switching frequency = the resonance frequency,

Vc = I =VIconv D, D. c_conv

(13)

If the switching frequency « the resonance Vc =frequency, Vc_conv D.

(14)

If the switching frequency « the resonance frequency, 1

Vc ≈

Vin,

1 Vc ≈ 2Vin, 2

(14)

(15) (15)

where Iconv Iand V Vc_convare thecurrent currentflowing flowing through the interface and the voltage a single where conv andc_conv are the through the interface and the voltage across a across single pair pair of the capacitive coupling interface plates for the conventional system, respectively. of the capacitive coupling interface plates for the conventional system, respectively.

Figure 8. The frequency response of the voltage Vc across one pair of the coupling plates at different

Figure 8. The frequency response of the voltage Vc across one pair of the coupling plates at different duty cycles D. duty cycles D.

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4. Electric Field Simulation 4. Electric Field Simulation As discussed in the previous section, the proposed system has lower voltage stress over the As discussed in the previous section,the theelectric proposed has lower voltage plates, stress over the capacitive coupling interface. Accordingly, fieldsystem in between the coupling including capacitive coupling interface. Accordingly, the electric field in between the coupling plates, including the leakage electric field emissions, should decrease as well. In this section, the transient E field analysis the leakage electric field emissions, should decrease as well. In this section, the transient E field in Maxwell software from Ansys, Pennsylvania, USA, was used to simulate the electric field strength analysis in Maxwell software from Ansys, Pennsylvania, USA, was used to simulate the electric field between and around the plates. Figure 9 shows the experimental modelling used as the coupling strength between and around the plates. Figure 9 shows the experimental modelling used as the interface with the same dimensions and materials. Measurement points were assigned between and at coupling interface with the same dimensions and materials. Measurement points were assigned different distances around the plates as listed in Table 2. between and at different distances around the plates as listed in Table 2.

Figure 9. Plates modelling in Ansys Maxwell. Figure 9. Plates modelling in Ansys Maxwell. Table 2. Measurement points coordination. Table 2. Measurement points coordination.

Point A Point AB BC CD DE E

Distance to the Plates (cm) X, Y, Z In the center between Tx1(cm) and X, Rx1 Distance to the Plates Y, Z 2, 0, 0 (in front of Tx1 and Rx1) In the center between Tx1 and Rx1 0, 0, 1 (above Tx1 and Rx1) 2, 0, 0the (in center front ofofTx1 and Rx1) 0, 1 (above center of Tx1 and Rx1) 0, 0, 30,(above the the center of Tx1 and Rx1) 0, 0, 3 (above the center of Tx1 and Rx1) 0, 0, 4 (above the center of Tx1 and Rx1) 0, 0, 4 (above the center of Tx1 and Rx1)

Figure 10 shows that the electric field between the single pair coupling interface plates reduced by D factor, inelectric a reduction the electric field emission to theinterface surrounding as Figure 10which showsresults that the field in between the single pair coupling platesspace reduced Figures 11 and byillustrated D factor, in which results in 12. a reduction in the electric field emission to the surrounding space as illustrated in Figures 11 and 12.


Figure 10.Simulated Simulated electricfield field atmeasure measure pointAAbetween between Tx1and and Rx1. Figure Figure 10. 10. Simulatedelectric electric field at at measure point point A between Tx1 Tx1 and Rx1.

Figure 11.Simulated Simulated electricfield field atmeasurement measurement pointBBin in frontof of Tx1and and Rx1. Figure Figure 11. 11. Simulatedelectric electric field at at measurement point point B in front front of Tx1 Tx1 and Rx1. Rx1.

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Figure 12. Simulated electric field at measurement points C, D, and E above the center of Tx1 and Figure 12. Simulated electric field at measurement points C, D, and E above the center of Tx1 and Rx1. Rx1.

According Institute of Electrical andand Electronics Engineers (IEEE)(IEEE) standard for safety Accordingtotothe the Institute of Electrical Electronics Engineers standard for levels safety with respect to human exposure to radio frequency electromagnetic fields of 3 kHz to 300 GHz [28], levels with respect to human exposure to radio frequency electromagnetic fields of 3 kHz to 300 GHz the field strength emissions for any system should be lower than 614 V/m for 0.03–1.34 MHz to ensure [28], the field strength emissions for any system should be lower than 614 V/m for 0.03–1.34 MHz to safe operation withoutwithout harm toharm the human body. According to Figure 11, for11, thefor conventional CPT, ensure safe operation to the human body. According to Figure the conventional the safe region starts after 2.5 cm in the X and Y directions from the plates by adding a buck converter CPT, the safe region starts after 2.5 cm in the X and Y directions from the plates by adding a buck electric field lower field than lower 614 V/m anywhere the XY plane the plates. 12 shows that converter electric than 614 V/m in anywhere in thearound XY plane aroundFigure the plates. Figure 12 the safe region for the conventional system, where the electric field is acceptable, is 3.5 cm above shows that the safe region for the conventional system, where the electric field is acceptable, is 3.5the cm plates. the system the withsystem a buckwith converter sufficiently low electriclow fieldelectric levels to be levels used above Notably, the plates. Notably, a buckhas converter has sufficiently field safely. The proposed system helpssystem to safely useto CPT technology the need for shielding or to be used safely. The proposed helps safely use CPTwithout technology without the need for living object detection systems. shielding or living object detection systems. 5. Experimental Results 5. Experimental Results A prototype was built, based on parameters listed in Table 3, as shown in Figure 13. The capacitive A prototype was built, based on parameters listed in Table 3, as shown in Figure 13. coupling interface was made of copper boards and the metal faces are covered by the polypropylene The capacitive coupling interface was made of copper boards and the metal faces are covered by the tape (relative permittivity is about 2.5) as a dielectric material. The dimensions of the pickup plates polypropylene tape (relative permittivity is about 2.5) as a dielectric material. The dimensions of the were chosen to suit the back side of an Apple 10-inch iPad, 10 cm × 14 cm each. Four Schottky diodes pickup plates were chosen to suit the back side of an Apple 10-inch iPad, 10 cm × 14 cm each. Four were used to compose the rectifier for its high-frequency abilities, and Litz-wire was used for inductors Schottky diodes were used to compose the rectifier for its high-frequency abilities, and Litz-wire was to reduce skin effect. Duty cycles 20%, 30% and 100% (system without buck converter) of DC–DC buck used for inductors to reduce skin effect. Duty cycles 20%, 30% and 100% (system without buck converter were examined. The input voltage value was determined according to the duty cycle used converter) of DC–DC buck converter were examined. The input voltage value was determined in the DC–DC buck converter for delivering 10 W of power to the load. The frequency was swiped according to the duty cycle used in the DC–DC buck converter for delivering 10 W of power to the from 0.35 MHz to 2.5 MHz to show the frequency responses of the output power and the voltage stress load. The frequency was swiped from 0.35 MHz to 2.5 MHz to show the frequency responses of the across the interface. output power and the voltage stress across the interface. For kilowatt (kW) level high power applications, silicon-carbide (SiC) field effect transistors For kilowatt (kW) level high power applications, silicon-carbide (SiC) field effect transistors (FETs) can be used instead of conventional power metal oxide semiconductor field effect transistor (FETs) can be used instead of conventional power metal oxide semiconductor field effect transistor (MOSFETs) used in this experiment; while at low power high frequency operations at several tens of (MOSFETs) used in this experiment; while at low power high frequency operations at several tens of MHz, gallium-nitride (GaN) FETs provides a good option [29]. MHz, gallium-nitride (GaN) FETs provides a good option [29].

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Figure 13. The system prototype. PWM: pulse-width modulation. Figure 13. The system prototype. PWM: pulse-width modulation. Table 3. Circuit parameters and system specifications. Table 3. Circuit parameters and system specifications.

Parameter Pload freq. Pload freq. Cc1 Cc1 Cc2 Cc2 Duty Cycle Duty Cycle L L Rload Rload Parameter

Unit Unit Watt

MHz Watt MHz nF nF nF nF % % μH µH Ω Ω

Value Value 10 1 10 1 ~2.1 ~2.1 ~1.9 ~1.9 20, 30, 10020, 30, 100 25 25 10 10

Figure power at at different duty cycles. Q Figure 14 14 shows shows the thefrequency frequencyresponse responseofofthe theDC DCoutput output power different duty cycles. reduction is confirmed by reducing the duty cycle of the buck converter as predicted from the Q reduction is confirmed by reducing the duty cycle of the buck converter as predicted from the analysis. analysis. The The main main reason reason for for the the shift shift in in the the response response is is the the change change in in the the value value of of the the total total impedance impedance of the load and the parasitic capacitance of the diodes that constructs the rectifier by of the load and the parasitic capacitance of the diodes that constructs the rectifier by changing changing the the duty cycle. As proved in the analysis section, by reducing Q, the system’s tolerance to misalignment duty cycle. As proved in the analysis section, by reducing Q, the system’s tolerance to misalignment improves, as shown shownin inFigure Figure15. 15.Figure Figure1616shows shows the amplitude voltage stress measured across improves, as the amplitude of of voltage stress measured across the the single pair of the capacitive interface (C c1). A differential probe was used to eliminate the common single pair of the capacitive interface (Cc1 ). A differential probe was used to eliminate the common ground ground effect. effect. The The voltage voltage stress stress is is proportionally proportionally decreasing decreasing with with the the duty duty cycle cycle which which follows follows Equation (14) from the mathematical analysis. The maximum voltage stress across capacitive Equation (14) from the mathematical analysis. The maximum voltage stress across the the capacitive interface ) is reduced to about 65 V at D = 30% and 44 V at D = 20%, corresponding to an output interface (C (Cc1 c1 ) is reduced to about 65 V at D = 30% and 44 V at D = 20%, corresponding to an output power W, while while 211 211 V V is is measured measured for for the the no no buck buck converter converter used used case. case. The power of of 10 10 W, The values values of of the the experimental results of V c is higher than the calculated ones due to the non-ideal components in the experimental results of Vc is higher than the calculated ones due to the non-ideal components in the system so aa higher system and and the the switching switching losses losses which which decrease decrease the the efficiency, efficiency, so higher input input voltage voltage is is needed needed to to deliver 10 W resulting in higher voltage stress across the interface. By using 64 V DC input voltage deliver 10 W resulting in higher voltage stress across the interface. By using 64 V DC input voltage (V (VDD),),the thesystem systemcould coulddeliver deliver10 10W Wof ofpower powerat atthe theduty dutycycle cycleof of30% 30%and andoperating operatingfrequency frequency11MHz, MHz, while the end-to-end system efficiency reached 80%. Figure 17 shows the measured V in, Vc, and Vout. while the end-to-end system efficiency reached 80%. Figure 17 shows the measured V , V , and V . in

c

out

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Figure14. 14.Frequency Frequencyresponse responseof ofthe theDC DCoutput outputpower. power. Figure Figure 14. Frequency response of the DC output power.

Figure 15. 15. The The tolerance tolerance of of the the output output power power with with the the change change in in the the capacitive capacitive interface interface equivalent equivalent Figure Figure 15. The tolerance of the output power with the change in the capacitive interface equivalent series value. series value. series value.


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Figure 16. Frequency response of the voltage across the single pair of the capacitive interface Cc1 Figure 16. Frequency response response of Figure 16. Frequency of the the voltage voltage across across the the single single pair pair of of the the capacitive capacitive interface interface CCc1c1 (amplitude). (amplitude). (amplitude).

Figure 17. Waveforms of the input AC voltage, voltage across the coupling capacitor, and the DC Figure 17. Waveforms of the input AC voltage, voltage across the coupling capacitor, and the DC output17. voltage. Figure Waveforms of the input AC voltage, voltage across the coupling capacitor, and the DC output voltage. output voltage.

6. Conclusions 6. Conclusions 6. Conclusions This paper proposed a novel method for reducing the voltage stress and sensitivity of a CPT Thisby paper proposed novel method for reducing the voltageofstress and sensitivity ofhas a CPT system usingproposed a DC–DCaa buck Mathematical the proposed systemof been This paper novelconverter. method for reducing theanalysis voltage stress and sensitivity a CPT system by using a DC–DC buck converter. Mathematical analysis of the proposed system has been carriedby out to investigate the change in the system’s Q analysis and the voltage stress across thehas coupling system using a DC–DC buck converter. Mathematical of the proposed system been carried outThe to investigate the change in the system’s Q and by theusing voltage stress across the coupling interface. leakage electric field emissions were simulated the Maxwell software package. carried out to investigate the change in the system’s Q and the voltage stress across the coupling interface. Thethat leakage electric field simulated usingconverter, the Maxwell package. It is found by reducing the emissions duty cyclewere of the DC–DCby the software system Q reduces interface. The leakage electric field emissions were simulated bybuck using the Maxwell software package. Itproportionally is found that to byDreducing the duty cycle of the DC–DC buck converter, the system Q reduces 2. Accordingly, thecycle system to the change in thethe system parameters has It is found that by 2reducing the duty of tolerance the DC–DC buck converter, system Q reduces proportionally to D . Accordingly, the system tolerance tothe thevoltage changestress in theissystem parameters has 2 improved. While transferring the same amount of power, reduced proportionally proportionally to D . Accordingly, the system tolerance to the change in the system parameters has improved. While transferring the same amount of power, voltage stress is reduced to D and While the related leakage field around the the plates is drastically shrunkproportionally so the system improved. transferring theelectric same amount of power, the voltage stress is reduced proportionally tobecomes D and safer the related leakage electric field around the plates is drastically shrunk so the system and the probability of dielectric breakdown or spark occurrence becomes much less. to D and the related leakage electric field around the plates is drastically shrunk so the system becomes safer and the probability of dielectric breakdown or spark occurrence becomes much less. The experimental results from a 10 W CPT prototype demonstrated that by adding the buck becomes safer and the probability of dielectric breakdown or spark occurrence becomes much less. The experimental a 10 W effectively CPT prototype demonstrated that bytheadding the buck converter, Q and results voltagefrom stress could be reduced by changing duty cycle. The converter, and voltage stressone could be reduced by been changing thetoduty maximumQvoltage stress across paireffectively of the coupling plates has reduced 65 V cycle. and 44The V at maximum voltage stress across one pair of the coupling plates has been reduced to 65 V and 44 V at

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The experimental results from a 10 W CPT prototype demonstrated that by adding the buck converter, Q and voltage stress could effectively be reduced by changing the duty cycle. The maximum voltage stress across one pair of the coupling plates has been reduced to 65 V and 44 V at duty cycles of 30% and 20%, respectively, compared to 211 V for the conventional system without using a DC–DC converter. By applying 64 V input DC voltage and 30% buck converter duty cycle the system has achieved a system input to output (end-to-end) power efficiency of 80% at an output power of 10 W. Author Contributions: T.M. proposed the idea, obtained the results, and wrote the paper. T.M. and D.B. built the experimental setup. All authors together contributed by drafting and critical revisions. Funding: This research received no external funding. Conflicts of Interest: The authors declare no conflict of interest.

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