Cascaded H-Bridge Multilevel PV Topology for ... - IEEE Xplore

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 8, AUGUST 2016

Cascaded H-Bridge Multilevel PV Topology for Alleviation of Per-Phase Power Imbalances and Reduction of Second Harmonic Voltage Ripple Christopher D. Townsend, Member, IEEE, Yifan Yu, Student Member, IEEE, Georgios Konstantinou, Member, IEEE, and Vassilios G. Agelidis, Fellow, IEEE

Abstract—The cascaded H-bridge (CHB) topology is ideal for implementing large-scale converters for photovoltaic (PV) applications. The improved quality of output voltage waveforms, high efficiency due to transformer-less connection, and ability to employ multiple instances of a maximum power point tracking (MPPT) algorithm are just some advantages. An important disadvantage is the required over-rating to ensure balanced three-phase currents at times of unequal PV generation. Unequal generation occurs due to shading, temperature inhomogeneity, faulty H-bridges, etc. Capacitor voltage balancing under such conditions requires zerosequence voltage injection which increases the required number of series connected H-bridges. However, leakage current and safety requirements often dictate a need for isolation between PV arrays and the cascaded converter. Therefore, this paper proposes a converter topology that avoids the cost of extra series connected H-bridges by extending the function of dc–dc converters that provide isolation. Second harmonic power oscillations seen in typical cascaded topologies can also be eliminated or reduced through use of the proposed topology. Simulation and experimental results are presented that confirm correct operation of the proposed approach. Index Terms—Cascaded converters, control strategy, multilevel converters, photovoltaic, voltage balancing.

I. INTRODUCTION IVEN the growing trend of large-scale grid connected photovoltaic (PV), there is a desire to optimize converter topologies and control structures used to interface PV’s with the wider electrical network. The main goal of the converter is to maximize transfer of energy into the grid while minimizing losses and meeting grid connection standards. Fig. 1 shows the cascaded H-bridge (CHB) converter which could increasingly be utilized to integrate PV’s [1]–[5]. The main reasons for the choice of this topology are: 1) multiple dc links allow separation of PV arrays so that multiple instances of a maximum power point tracking (MPPT) algorithm can optimize the extraction of power; 2) semiconductor loss is significantly lowered, as the switching frequency of each semiconductor device can be reduced close to fundamental frequency,

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Manuscript received September 15, 2015; accepted October 29, 2015. Date of publication November 4, 2015; date of current version March 2, 2016. Recommended for publication by Associate Editor L. Zhang. The authors are with the Australian Energy Research Institute, and also with the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, N.S.W. 2051, Australia (e-mail: [email protected]; [email protected]; [email protected]; vassilios.ageli [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2015.2497707

Fig. 1. Circuit configuration for a CHB PV converter utilizing dc–dc converters.

while output voltage quality remains excellent; and 3) the level number can be increased to allow direct connection of the converter to medium voltages which avoids the lossy and expensive line-frequency transformer [6], [7]. In the topology shown in Fig. 1, second-harmonic voltage ripple appears on each CHB capacitor (C1 ). This occurs because each phase-leg is made up of a single-phase converter that buffers 100 Hz power variations within each fundamental cycle. Inclusion of dc–dc converters in Fig. 1 decouples secondharmonic voltage ripple from output PV array capacitors (Cf ). Second-harmonic voltage ripple would otherwise reduce power extracted from PV arrays due to voltage oscillation around the maximum power point. Alternatively, to minimize power loss due to second-harmonic voltage ripple without dc–dc converters, CHB capacitor sizes must be increased to the point where they make up a very large proportion of total system cost [8]. In all solar installations, there exists a parasitic capacitance between each PV module and ground. Leakage currents, caused by common-mode voltages applied across PV parasitic capacitances, can be increased in cascaded converters due to direct connection of the converter to the medium-voltage grid [2]. Leakage currents can cause safety and protection issues,

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TOWNSEND et al.: CASCADED H-BRIDGE MULTILEVEL PV TOPOLOGY FOR ALLEVIATION OF PER-PHASE POWER

additional losses and potential induced degradation of PV modules [9]. Therefore, leakage current issues can dictate use of isolated dc–dc converters within each converter cell. Various dc–dc converters, including the Flyback converter, have been proposed to decouple second-harmonic voltage ripple and provide isolation. In high-power applications, interleaved Flyback converters could be well suited to increase power ratings while maximizing efficiency [10], [11]. One major issue with cascaded topologies, even with the inclusion of isolated dc–dc converters, is the problem of perphase power imbalances. Grid connection standards typically require the magnitude of each phase current to be equal under nonfault conditions, meaning that an equal amount of power should be delivered to each phase of the grid. Shading effects, temperature inhomogeneity, uneven dust accumulation on PV modules, faulty cells, and manufacturing tolerances cause an unequal amount of power to be developed by PV arrays connected to each phase leg. Previous solutions suggest injecting a zero-sequence voltage to exchange any excess energy between phase legs without unbalancing the three phase currents [12]– [14]. However, the significant disadvantage of this technique is the need to increase the voltage rating of the converter to allow sufficient voltage overhead for the zero-sequence component. In a worst-case scenario, when only one phase-leg’s PV arrays produce full power, the zero-sequence injection triples the number of required series connected H-bridges [13]. Such an over-rating would result in unjustifiable converter cost. With the aforementioned issues in mind, Essakiappan et al. [15] propose a cascaded connection of ac–ac (cycloconverter) cells to implement a PV converter. Each row (or “zone”) uses a medium-frequency transformer with three secondaries to feed an input to each cascaded ac–ac H-bridge. The primary of each transformer is modulated by a dc–ac H-bridge which takes as input two series-connected PV arrays. The topology in [15] magnetically couples each phase such that energy storage components (capacitors) appear common to all phases. Therefore, second-harmonic capacitor voltage ripple is inherently eliminated. Elimination of this ripple can avoid use of large electrolytic capacitors typically responsible for reduced converter lifetime compared to PV modules [16]. Instead, longer lasting metalized polypropylene film capacitors could be used. Common storage elements accessible to each phase also eliminates need for zero-sequence voltage injection. One problem with the topology proposed in [15] is the complicated magnetic design and its implications on the converter’s mechanical complexity. The number of active components is also very high due to the ac–ac conversion stage requiring bidirectional switches. Extra active components increase not only converter cost but also semiconductor losses. This paper proposes the topology concept demonstrated in Figs. 2 and 3. In these two embodiments: 1) alleviation of perphase power imbalance; and 2) reduction of second-harmonic ripple, is achieved by controlling extraction of power from dc– dc converters whose inputs are parallel connected. It is shown in this paper that simple control techniques, coupled with the proposed topology, are capable of achieving these two goals. It is possible to create many alternate embodiments of the topology

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Fig. 2. Part-row connection—CHB PV converter utilizing isolated dc–dc boost converters whose inputs are parallel connected. Dotted lines infer connection to the same color-dotted lines.

Fig. 3. Full-row connection—CHB PV converter utilizing isolated dc–dc boost converters whose inputs are parallel connected. Colored-dotted lines infer connection to the same color-dotted lines.

by parallel connecting various subsets of dc–dc converter inputs. This paper will focus on the two embodiments shown in Figs. 2 and 3. The embodiment in Fig. 2 will hereby be referred to as the part-row connection while the embodiment in Fig. 3 will be referred to as the full-row connection. The authors have presented the topology concept and some preliminary (simulation-only) results in [17]. This paper thoroughly describes motivation for and details of the proposed topology and control scheme. A comparison is provided to the typical CHB topology in terms of the amount of second

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Fig. 4. Cascaded converter waveforms for various operational conditions (Red—Voltage, Green—Current, Blue—Instantaneous Power). (a) Only active power, (b) Only reactive power, (c) Equal active and reactive power.

harmonic voltage ripple and required over-rating to alleviate per-phase power imbalance. Extensive simulation and experimental results are used to perform the comparison and validate the approach. II. PROPOSED TOPOLOGY This section discusses the proposed topology in terms of required functionality of the dc–dc conversion stages, component count, and differences between the two proposed embodiments. In Figs. 2 and 3, the choice of isolated dc–dc converter utilized in the “dc/dc” blocks is dependent on whether any reactive power support to the grid is required while simultaneously eliminating second-harmonic ripple. To illustrate this point, Fig. 4 shows normalized instantaneous power flows between the grid and a phase leg in any cascaded converter. Note that when generating these waveforms the assumption has been made that voltage drops across connection inductances can be ignored. This is reasonable as connection inductances in multilevel converters are typically small (< 0.1 p.u.). To eliminate second-harmonic voltage ripple on each CHB capacitor, in the proposed topology, the supplied instantaneous power from dc–dc converters must be equal to the instantaneous power being delivered to the grid from that phase. The most common operational condition is that shown in case “a” where the PV converter injects only active power to the grid. During this condition instantaneous power is at all times non-negative. This implies isolated unidirectional dc–dc converters will be sufficient to provide second-harmonic power oscillations, and hence, eliminate second-harmonic voltage ripple. Use of unidirectional dc–dc converters, such as the Flyback converter, will minimize the number of active components in the topology. However, it can be seen from cases “b” and “c” that when reactive power support is necessary the instantaneous power

direction reverses for part of the waveform. Therefore, to achieve complete elimination of second-harmonic voltage ripple, while providing reactive power support, bidirectional dc–dc converters are required. While elimination of second-harmonic voltage ripple is not possible for cases “b” and “c” with unidirectional dc–dc stages it is noted that reduction of ripple is still achievable. This is demonstrated in Section V. In regards to the component count associated with the proposed topology, there is no need to increase the number of active components with respect to the topology shown in Fig. 1. All that is required is a number of extra electrical connections per row. Additionally, these connections could be made in the geographical location of the PV arrays, thereby reducing the number of cable connections between the PV park and the centrally located converter. The main reason for linking only two PV arrays in the partrow connection (see Fig. 2), rather than all three as shown in the full-row connection (see Fig. 3), is to increase the number of independent instances of the MPPT algorithm. It will be demonstrated in Section V that there is a tradeoff between the number of independent instances of the MPPT algorithm and reduction in second-harmonic ripple. This implies the full-row connection will achieve superior reduction in second-harmonic ripple at the expense of one less independent dc link voltage per row. Remark 1: In previously proposed cascaded topologies (see Fig. 1), in cases where isolation between PV arrays and the grid is required, the insulation rating of the transformer used in each dc–dc converter varies according its row number. The closer the dc–dc converter is to the top of the converter (closer to the grid side) the higher the insulation requirements, due to exposure to a larger phase-ground voltage. The proposed topology does not change any of the insulation requirements, i.e., the insulation ratings remain equal to previous cascaded topologies, where each rating is determined by the dc–dc converter’s row number. III. DC–AC CONTROL SCHEME A block diagram of the scheme responsible for controlling the dc–ac side (CHB) of the PV converter is shown in Fig. 5, with the following variable definitions: Qdem Qr Pr Ppv ir Vr l e g

Demanded reactive power from supervisory control; Reference reactive power; Reference active power; Total power entering the converter from PV arrays; Current reference; Target cluster voltage for each phase, where cluster voltage is defined as the sum of capacitor voltages in one phase; Vave l e g Measured average cluster voltage; Vl,x Measured cluster voltage of phase “x”; Reference voltage calculated by the dead-beat controller; vr Measured converter current; isc Measured system voltage and vg Vdc,xj Measured CHB capacitor voltage in the jth H-bridge of phase x.


Fig. 5.

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Block diagram of control for dc–ac conversion stages.

As can be seen from Fig. 5, the control is hierarchical, with the inner part of the structure executing a dead-beat current controller and switching state selection, with the outer level responsible for control of real and imaginary power. The “PQ” block uses instantaneous power theory [18] to decompose active and reactive powers into their constituent α, β current components given by (1) and (2). The reactive power reference is developed by adding the demanded reactive power to the output of a proportional integral (PI) controller, which acts on the difference between demanded and measured reactive power. Addition of demanded reactive power at the PI controller output results in a faster system response under step changes in demanded reactive power. The presence of integral gain corrects steady-state error between demanded and measured reactive power iα ,r

vα ,g Pr + vβ ,g Qr = vα2 ,g + vβ2 ,g

iβ ,r =

vβ ,g Pr − vα ,g Qr . vα2 ,g + vβ2 ,g

(1) (2)

The “leg voltage control” block calculates the required real power to regulate the cluster voltages. The real power current reference is calculated via (3) Pr = 3K1 Vr l e g − Vave l e g − Ppv where K1 is a chosen constant, Vave l e g is the average cluster voltage Vave l e g =

Vl,a + Vl,b + Vl,c 3

(4)

and Ppv is a feed-forward term representing the total power entering the converter via the PV arrays Ppv = vpv,a1 × ipv,a1 + · · · + vpv,aN × ipv,aN + · · · + vpv,b1 × ipv,b1 + · · · + vpv,bN × ipv,bN + · · · + vpv,c1 × ipv,c1 + · · · + vpv,cN × ipv,cN

(5)

where vpv,xj is the PV array voltage on the jth H-bridge in phase x, ipv,xj is the output PV array current on the jth H-bridge in phase x, and N is the number of H-bridges in each phase leg.

Remark 2: Controlling three phase demanded real power via (3) regulates the sum of all capacitor voltages on the dc–ac side of the converter. An additional control mechanism is required to ensure the total voltage is shared evenly between the cascaded phase legs. This mechanism is outlined in Section IV-A. The current controller is based on a popular dead-beat current controller often used in variable speed drive applications [19], [20] to provide excellent dynamic current tracking performance. Other current control techniques, including well-known dq current controllers [21], could also be employed in the proposed topology. The basic equations used to calculate the required output voltages in the dead-beat current controller (on both the alpha and beta axis) are shown in (6) and (7) L k +1 ˆk (i − isc ) + vˆgk +0.5 T r îksc = iksc−1 + T (vrk − vgk −0.5 ) L

vrk +1 =

(6) (7)

where k ∈ I, T is the length of the control interval in seconds, iksc−1 is the sampled instantaneous current vector at time t = (k − 1) T , îksc is the instantaneous predicted current at time t = kT , and ikr +1 is the instantaneous reference current at time t = (k + 1) T . As for the voltage nomenclature, vrk is the actual voltage applied during the interval from (k − 1) T → kT , vrk +1 is the reference voltage that the controller applies from kT → (k + 1) T , vˆgk +0.5 is the predicted instantaneous supply voltage at the midpoint of the control interval from kT → (k + 1) T , and vgk −0.5 is the measured instantaneous supply voltage at the midpoint of the control interval from (k − 1) T → kT . The ˆ symbol denotes a predicted value. Remark 3: Effects of sampling/computational delay are reduced by utilizing predicted values of system voltage (ˆ vgk +0.5 ) in (6) instead of measured system voltages. Remark 4: The “state selection & capacitor balancing” and “PWM Gen” blocks in Fig. 5 are responsible for synthesizing each phase leg’s requested output voltage. The one-dimensional modulation scheme used in this paper is described in [22]. In this scheme, two applied voltage levels per control period are time weighted to achieve the time integral of the voltage reference. The capacitors used to synthesize each voltage are selected

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Block diagram of control for dc–dc conversion stages. Second-order low-pass filters are utilized with a cutoff frequency of 25 Hz.

Fig. 6.

based on evaluation of a cost function. The cost function ensures capacitor voltages and semiconductor losses remain balanced throughout converter operation. Note that traditional modulation schemes for CHB converters such as carrier-based schemes described in [21], [23]–[25] could also be utilized in the proposed topology. IV. DC–DC CONTROL SCHEME The control scheme described in the previous section allows the CHB converter to inject a demanded reactive and active power into a three-phase grid. The control scheme described in this section, and shown in Fig. 6, controls each dc–dc conversion stage in the proposed topology. This section assumes use of a Flyback converter in this stage. The duty cycle, and hence, transferred power, of each Flyback converter is controlled locally within each cell. There is no need for communication between different dc–dc conversion stages. However, each Flyback controller requires eight signals, sent from a central measurement system, to calculate the required duty cycle. The eight signals required in the jth cell in phase x consist of:

Ppv,oth Average active power entering H-bridge cells in the other phase(s) with which this dc–dc conversion stage shares a common dc bus with i.e., for part-row connection vpv,y 1 × ipv,y 1 + · · · + vpv,yN × ipv,yN ; (9) N for full-row connection 1 Ppv,oth = ( vpv,y 1 × ipv,y 1 + · · · + vpv,yN × ipv,yN + 2N · · · + vpv,z 1 × ipv,z 1 + · · · + vpv,zN × ipv,zN ) ; Ppv,oth =

(10) Vl,x Vl,oth

Cluster voltage of this phase and Cluster voltage of the other phase(s) with which this dc-dc conversion stage shares a common dc bus with i.e., for part-row connection Vl,oth = Vl,y for full-row connection

Vl,y + Vl,z . (12) 2 In this paper, each Flyback converter operates in discontinuous conduction mode (DCM). DCM is ensured by limiting the duty cycle to a value determined by output voltage magnitude and turns ratio of the Flyback transformer [26]. As seen from Fig. 6 each dc–dc converter duty cycle is determined by three separate control loops. Loop 1 is responsible for regulating the PV voltage at its requested maximum power point. This loop uses a simple PI controller with a higher bandwidth (x10) than the control loop responsible for regulating total three-phase power injected to the grid (whose bandwidth is determined by K1 in (3)). Ensuring a decade of difference in bandwidths limits control interactions between these loops. Loop 2 eliminates/minimizes second-harmonic voltage appearing at the output of each dc–dc converter i.e., the associated CHB capacitor. The signal Vdc,ave contains no second-harmonic Vl,oth =

Vdc,xj Vdc,ave

Measured H-bridge capacitor voltage at the output of the Flyback converter; Average H-bridge capacitor voltage i.e., c Vdc,ave =

vpv,r

vpv,xj Ppv,x

x=a

N j =1

3N

Vdc x j

;

Requested output PV voltage that extracts maximum power. This signal can be provided from a MPPT algorithm; Measured PV array voltage associated with this cell; Average active power entering H-bridges in this phase i.e., Ppv,x =

vpv,x1 × ipv,x1 + · · · + vpv,xN × ipv,xN ; N

(8)

(11)


voltage component as it is an average over three phases. Therefore, to minimize second-harmonic voltage ripple, loop 2 forms a high bandwidth (>100 Hz) proportional controller that modifies output power from the dc–dc converter such that the CHB capacitor voltage follows Vdc,ave . Loop number 3 will be discussed in the following section. Remark 5: By eliminating second-harmonic voltage ripple control loop 2 facilitates minimization of H-bridge capacitance, which is particularly important under internal H-bridge fault conditions. In the event of a semiconductor failing in an on state, it is possible to cause a shoot-through condition. Under such a condition stored H-bridge capacitor energy is discharged through parasitic semiconductor resistances. The larger the Hbridge capacitor, the higher semiconductor over-rating required to withstand the very high inrush currents. Alternatively, an explosion box can be used to contain destructive forces caused by explosion of semiconductors during shoot-through. Either way, minimization of the H-bridge capacitors simplifies cell protection under internal faults and can significantly reduce cost. A. Per-Phase Active Power Imbalance The proposed topology can avoid zero-sequence injection by adjusting the power which parallel connected dc–dc converters feed into differing phases. Loop number 3 in Fig. 6 is responsible for this power correction between neighboring phases. Consider only the dc–dc conversion stages in the part-row connection, residing in phase x, whose input dc bus is connected in parallel with the bus of a dc–dc conversion stage in phase y. If the cluster voltage of phase x is higher than phase y there is too much active power being fed into phase x. In this case, loop 3 will cause each of the phase x dc–dc conversion stages to reduce their duty cycle. This decreases the active power input to phase x. Now consider the same disparity between cluster voltages but from the point of view of dc–dc conversion stages residing in phase y, whose input dc bus is connected in parallel with the bus of a dc–dc conversion in phase x. Each of these dc–dc conversion stages will increase its duty cycle, which increases active power output to phase y. The accumulated effect of the two groups of independent dc–dc converters is equal power input to phases x and y. The same functionality is implemented for the dc–dc conversion stages connected in parallel between phases y − z and phases z − x to ensure equal power input to all three phases. The same mechanism will also ensure equal power input to all phases when utilizing the full-row connection. Remark 6: For the dc–dc conversion stages that do not share a common dc bus with another cell the following signal definitions are made: Vl,x = Vl,y and Ppv,x = Ppv,y , such that loop number 3 has no effect on the calculated duty cycle. A simple PI controller with a low bandwidth is used to develop the required feedback control action in loop 3. The bandwidth can be low (4 due to parallel connection of multiple dc–dc conversion stages. This confirms the proposed topology is capable of eliminating, or at least significantly reducing, second-harmonic voltage ripple in a practical system. Fig. 17 shows waveforms for the part-row connection with equal PV generation. The part-row connection is created by connecting only the PV simulators associated with phases “a” and “b” in parallel. The phase “c” PV voltage is regulated at a higher value to demonstrate that when using the part-row connection the number of independent dc links is doubled with respect to the full-row connection, the irradiance has been modified on phase “c” to preserve the equal power condition. It can be seen that the part-row connection can still minimize second-harmonic ripple appearing on the CHB capacitors. However, a second-harmonic component appears across each PV simulator. This confirms the simulation results from Section V. Fig. 18 depicts waveforms for the full-row connection with equal amounts of reactive and active power delivered to the grid. Due to the use of bidirectional dc–dc conversion stages it can be

Fig. 19. Experimental waveforms for the full-row connection for equal PV generation on all PV modules with a change in irradiance from 500 to 1000 W/m 2 starting at 0.8 s—Top plot: CHB capacitor voltages, Middle upper plot: PV voltage, Middle lower plot: CHB measured currents, Bottom plot: Reference CHB voltages.

seen that second-harmonic ripple is eliminated from both CHB capacitor voltages and PV voltages. D. Transient Performance Fig. 19 shows waveforms for when the full-row connection is initially injecting 0.6 kW into the grid with equal PV generation. From 0.8 → 1.8 s, the PV simulators emulate a linear increase in irradiance from 500 to 1000 W/m2 . The change in irradiance is performed over a 1 s period to replicate a fast shading event in a practical PV system. During the transient it can be seen that the dc-dc control scheme continues to eliminate second harmonic ripple on both


the CHB and PV capacitor voltages. Only small disturbances are seen in the CHB and PV capacitor voltages before the system returns to steady state operation. The excellent tracking performance is due to the feed-forward power terms in the dc–ac and dc–dc control schemes, as discussed in Sections III and IV. VII. CONTRIBUTIONS This paper describes a novel use of the isolated dc–dc conversion stages typically included in cascaded PV converters. The novel aspect of the topology is parallel connection of multiple dc–dc conversion stages. Development of a control scheme, from well-known and simple feedback and feed-forward techniques, provides the following benefits when applied to the new topology: 1) Each phase leg receives equal active power even under severe partial shading conditions. This eliminates overrating of the converter which was previously needed for zero-sequence voltage injection. 2) Second-harmonic voltage ripple is significantly reduced on CHB capacitors. PV array voltage ripple is also minimized by parallel connecting each dc-dc converter in each row. This can result in significant capacitor size reduction which reduces cost, size, and weight of the PV converter. REFERENCES [1] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. Negroni, “Energybalance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs,” IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 98–111, Jan. 2013. [2] R. Selvamuthukumaran, A. Garg, and R. Gupta, “Hybrid multicarrier modulation to reduce leakage current in a transformerless cascaded multilevel inverter for photovoltaic systems,” IEEE Trans. Power Electron., vol. 30, no. 4, pp. 1779–1783, Apr. 2015. [3] E. Villanueva, P. Correa, J. Rodriguez, and M. Pacas, “Control of a single-phase cascaded h-bridge multilevel inverter for grid-connected photovoltaic systems,” IEEE Trans. Int. Electron., vol. 56, no. 11, pp. 4399–4406, Nov. 2009. [4] B. Xiao, L. Hang, J. Mei, C. Riley, L. Tolbert, and B. Ozpineci, “Modular cascaded h-bridge multilevel pv inverter with distributed MPPT for gridconnected applications,” IEEE Trans. Ind. Appl., vol. 51, no. 2, pp. 1722– 1731, Mar. 2015. [5] Y. Liu, B. Ge, H. Abu-Rub, and F. Z. Peng, “An effective control method for three-phase quasi-z-source cascaded multilevel inverter based grid-tie photovoltaic power system,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6794–6802, Dec. 2014. [6] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodriguez, M. Pe and rez, and J. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010. [7] H. Iman-Eini, J.-L. Schanen, S. Farhangi, and J. Roudet, “A modular strategy for control and voltage balancing of cascaded h-bridge rectifiers,” IEEE Trans. Power Electron., vol. 23, no. 5, pp. 2428–2442, Sep. 2008. [8] J. Sastry, P. Bakas, H. Kim, L. Wang, and A. Marinopoulos, “Evaluation of cascaded h-bridge inverter for utility-scale photovoltaic systems,” Renew. Energy, vol. 69, pp. 208–218, 2014. [9] D. Lausch, V. Naumann, O. Breitenstein, J. Bauer, A. Graff, J. Bagdahn, and C. Hagendorf, “Potential-induced degradation (PID): Introduction of a novel test approach and explanation of increased depletion region recombination,” IEEE J. Photovol., vol. 4, no. 3, pp. 834–840, May 2014. [10] Z. Zhang, X.-F. He, and Y.-F. Liu, “An optimal control method for photovoltaic grid-tied-interleaved flyback microinverters to achieve high efficiency in wide load range,” IEEE Trans. Power Electron., vol. 28, no. 11, pp. 5074–5087, Nov. 2013. [11] B. Tamyurek and B. Kirimer, “An interleaved high-power flyback inverter for photovoltaic applications,” IEEE Trans. Power Electron., vol. 30, no. 6, pp. 3228–3241, Jun. 2015.

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[12] S. Rivera, S. Kouro, B. Wu, J. Leon, J. Rodriguez, and L. Franquelo, “Cascaded h-bridge multilevel converter multistring topology for large scale photovoltaic systems,” in Proc. IEEE Int. Symp. Ind. Electron., Jun. 2011, pp. 1837–1844. [13] Y. Yu, G. Konstantinou, B. Hredzak, and V. Agelidis, “Power balance optimization of cascaded h-bridge multilevel converters for large-scale photovoltaic integration,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 1108–1120, Feb. 2016. [14] C. Townsend, T. Summers, and R. Betz, “Control and modulation scheme for a cascaded h-bridge multi-level converter in large scale photovoltaic systems,” in Proc. Energy Convers. Congr. Expo., Sep. 2012, pp. 3707– 3714. [15] S. Essakiappan, H. Krishnamoorthy, P. Enjeti, R. Balog, and S. Ahmed, “Multilevel medium-frequency link inverter for utility scale photovoltaic integration,” IEEE Trans. Power Electron., vol. 30, no. 7, pp. 3674–3684, Jul. 2015. [16] B. Karanayil, V. Agelidis, and J. Pou, “Performance evaluation of three-phase grid-connected photovoltaic inverters using electrolytic or polypropylene film capacitors,” IEEE Trans. Sustainable Energy, vol. 5, no. 4, pp. 1297–1306, Oct. 2014. [17] C. Townsend, Y. Yu, G. Konstantinou, V. Agelidis, and G. Demetriades, “Capacitance minimisation & alleviation of per-phase power imbalances in cascaded PV converters,” Proc. Int. Conf. Ind. Electron. IECON, Nov. 2015. [18] H. Akagi, E. H. Watanabe, and M. Aredes, Instantaneous Power Theory and Application to Power Conditioning. Hoboken, NJ, USA: Wiley, 2007. [19] D. G. Holmes and D. A. Martin, “Implementation of a direct digital predictive current controller for single and three phase voltage source inverters,” in Proc. IEEE Ind. Appl. Conf. 31st IAS Annu. Meeting, Conf. Rec., San Diego, CA, USA, vol. 2, Oct. 1996, pp. 906–913. [20] R. Betz, B. Cook, and S. Henriksen, “A digital current controller for three phase voltage source inverters,” in Proc. Conf. Rec. IEEEIAS Annu. Meeting, New Orleans, LA, USA, Oct. 1997, pp. 722–729. [21] H. Akagi, S. Inoue, and T. Yoshii, “Control and performance of a transformerless cascade PWM statcom with star configuration,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1041–1049, Jul. 2007. [22] C. Townsend, R. Baraciarte, H. Zelaya De La Parra, G. Demetriades, and V. Agelidis, “Heuristic model predictive modulation in high power multi-level converters,” Proc. Int. Conf. Ind. Electron. Soc., 2015. [23] F. Deng and Z. Chen, “Elimination of dc-link current ripple for modular multilevel converters with capacitor voltage-balancing pulse shifted carrier PWM,” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 284–296, Jan. 2015. [24] B. Li, R. Yang, D. Xu, G. Wang, W. Wang, and D. Xu, “Analysis of the phase-shifted carrier modulation for modular multilevel converters,” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 297–310, Jan. 2015. [25] R. Darus, G. Konstantinou, J. Pou, S. Ceballos, and V. Agelidis, “Comparison of phase-shifted and level-shifted pwm in the modular multilevel converter,” in Proc. Int. Power Electron. Conf., May 2014, pp. 3764–3770. [26] M. Zhang, M. Jovanovic, and F. Lee, “Design considerations and performance evaluations of synchronous rectification in flyback converters,” IEEE Trans. Power Electron., vol. 13, no. 3, pp. 538–546, May 1998. [27] M. Kheraluwala and R. De Doncker, “Single phase unity power factor control for dual active bridge converter,” in Proc. Conf. Rec. IEEE Ind. Appl. Soc. Annu. Meeting, Oct. 1993, vol. 2, pp. 909–916. [28] S. Dutta and S. Bhattacharya, “Predictive current mode control of single phase dual active bridge dc to dc converter,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2013, pp. 5526–5533.

Christopher D. Townsend (S’09–M’13) received the B.E. and Ph.D. degrees in electrical engineering from the University of Newcastle, Callaghan, N.S.W., Australia, in 2009 and 2013, respectively. He is currently with ABB Corporate Research, Väster˚as, Sweden, and The University of New South Wales, Australian Energy Research Institute, Sydney, N.S.W., Australia. His current research interests include topologies and modulation strategies for multilevel converters. Dr. Townsend is a Member of the Power Electronics and Industrial Electronics Societies of the IEEE.

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Yifan Yu (S’13) received the B.Eng. and M.Eng. degrees in electrical engineering from the Harbin Institute of Technology, Harbin, China, in 2010 and 2012, respectively. He is currently working toward the Ph.D. degree at the University of New South Wales (UNSW), Sydney, N.S.W., Australia within the Australian Energy Research Institute. His current research interests include topologies and control strategies for multilevel PV converters.

Georgios Konstantinou (S’08–M’13) received the B.Eng. degree in electrical and computer engineering from the Aristotle University of Thessaloniki, Thessaloniki, Greece, in 2007, and the Ph.D. degree in electrical engineering from the University of New South Wales (UNSW), Sydney, N.S.W., Australia, in 2012. He is currently a Senior Research Associate with the Australian Energy Research Institute and the School of Electrical Engineering and Telecommunications, UNSW. He is an Associate Editor of IET Power Electronics. His research interests include hybrid and modular multilevel converters, pulse-width modulation, and selective harmonic elimination techniques for power electronics.

Vassilios G. Agelidis (S’89–M’91–SM’–FM’16) was born in Serres, Greece. He received the B.Eng. degree in electrical engineering from the Democritus University of Thrace, Thrace, Greece, in 1988, the M.S. degree in applied science from Concordia University, Montreal, QC, Canada, in 1992, and the Ph.D. degree in electrical engineering from Curtin University, Perth, W.A., Australia, in 1997. He was with Curtin University (1993–1999), the University of Glasgow, Glasgow, U.K. (2000–2004), Murdoch University, Perth, W.A., Australia (2005– 2006), and the University of Sydney, Sydney, N.S.W., Australia (2007–2010). He is currently the Director of the Australian Energy Research Institute, School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, N.S.W., Australia. Prof. Agelidis received the Advanced Research Fellowship from the U.K.’s Engineering and Physical Sciences Research Council in 2004. He was the Vice President for Operations with the IEEE Power Electronics Society (PELS) from 2006 to 2007. He was an AdCom Member of the IEEE PELS from 2007 to 2009 and the Technical Chair of the 39th IEEE Power Electronics Specialists Conference in 2008 held in Rhodes, Greece.