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A dual-coil fabrication process with electroplated through-wafer vias is .... SEM cross-sectional view along the center line of the spiral inductor structure shown in ..... devices as electro- hydro- dynamic microfluidic pumps32, and many other devices, ...... in surface mount technology93 and four-level VLSI bipolar metallization ...

INDUCTIVE LINKS WITH INTEGRATED RECEIVING COILS FOR MEMS AND IMPLANTABLE APPLICATIONS

A Dissertation

Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy

by Jie Wu, B.E., M.S.E., M.S.E.E., D.Eng.

_________________________________ Gary H. Bernstein, Director

Graduate Program in Electrical Engineering Notre Dame, Indiana September 2003

© Copyright by JIE WU 2003 All rights reserved

INDUCTIVE LINKS WITH INTEGRATED RECEIVING COILS FOR MEMS AND IMPLANTABLE APPLICATIONS

Abstract

by Jie Wu Microelectromechanical systems (MEMS) is a burgeoning field, and the next stage of development is predicted to be the integration of micro- sensors, actuators and circuits on a single silicon chip. Such microsystems will bring about revolutionary advancement in many fields, especially for implantable, autonomous applications. However, when freeing the chip from wire tethering, one major obstacle is the powering needs of MEMS devices, mainly microactuators, which are dramatically different from those of CMOS integrated circuit (IC) chips. Here we demonstrate that inductive links with integrated receiving coils can provide sufficient voltage or power to many MEMS devices. To further improve the performance of the inductive link, an inlaid electroplating procedure is developed to reduce the internal resistance of integrated receiving coils. Trenches into Si substrates by deep reactive ion etching (DRIE) are used as electroplating molds, and copper coils of centimeter side length

Jie Wu and up to 100 µm in height and 10 µm in width are electroplated. Enhanced outputs are obtained for inductive links with micromachined microcoils. Another application involves transmission of long-duration pulse trains onto an implantable receiving coil. Some medical conditions, such as Parkinson’s disease, already benefit from such pulse trains for deep brain stimulation (DBS) generated by a wired link. Wireless transmission of the pulses is challenging due to the small time constant of the inductive link. Using amplitude modulation, we successfully retrieve pulse trains from a receiving coil with a passive envelope detector, and electroplated coils provide improved performance. For either application, the output from the integrated coil is enhanced at a resonant frequency intrinsic to the inductive link.

Selective driving and signal

transmission are demonstrated for multiple receiving coils with frequency-multiplexed input.

A dual-coil fabrication process with electroplated through-wafer vias is

developed for future monolithic integration of coils with electronics. Combining dual coils with discrete demodulation and switching transistors, biphasic signals are generated across a resistor representing body tissue.

The above results offer

possibilities to replace pulse generators with an external unit in coordination with implanted receiving coils and circuit components.

To my parents…

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CONTENTS

FIGURES…………………………………………………………….........................vi TABLES…………………………………………………………………………….xiii ACKNOWLEDGMENTS………………………………………………………….xiv

CHAPTER 1 INTRODUCTION…………………………………………………..1 1.1

The development of MEMS……………..………………………………....1

1.2

Inductive links…..………………………………………………………….4

1.3

Preliminary results……………………………………………….………...8

CHAPTER 2 LITERATURE REVIEW…………………………………………15 2.1

Power requirements of MEMS devices…………………….…………….15

2.2

Non-contact on-chip power supplies……………………….…………….20

2.3

Integrated inductors………………………………………….…………...28

2.4 Inductive links with integrated coils………………………….……..........39 2.5

Fabrication of low resistance microcoils………….……………………...41

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CHAPTER 3 INLAID ELECTROPLATED MICROCOIL…………………...52 3.1 Fabrication overview………………………………………………………52 3.2 Inlaid electroplating process………………………………………………59 3.2.1

Thick photoresist molding………………………………..............59

3.2.2

Silicon mold forming.…………………………………………….62

3.2.3

Seed layer patterning……………………………………………...69

3.2.4

Copper electroplating……………………………………………..72

3.2.5 Mechanical polishing and Si removal…………………………….76 3.3

Microcoil characteristics………………………………………………….82

CHAPTER 4 INDUCTIVE LINK WITH INTEGRATED RECEIVING COIL ……………………………………....90 4.1 Ideal transformer………………………………………………………….91 4.2

Magnetic coupling………………………………………………………...95

4.3

Magnetostatic FEA simulation…………………………………………..106

4.4

Coupling coefficient measurement……………………………………...111

4.5

Driving coil characterization…………………………………………….116

CHAPTER 5 5.1

INDUCTIVE POWERING………………………………………125

Inductive link setup……………………………………………………...125

5.2 Inductive power delivery…………………………………………..........129 5.3

Inductive link efficiency………………………………………………...136

iv

5.4

Voltage amplification……………………………………………………145

5.5

Link stabilization…………………………………………………...........154

CHAPTER 6

INDUCTIVE WAVEFORM TRANSMISSION………………..157

6.1 Direct waveform transmission……………………………………..........157 6.2

Waveform transmission by amplitude modulation……………………...161

6.3

Rectifier regulation……………………………………………………...171

6.4

Arbitrary waveform generation………………………………………….176

CHAPTER 7

SUMMARY AND FUTURE WORK……………………………182

7.1

Summary……………………………………...........................................182

7.2

Future work – dual-coil design…………………………………….........185

REFERENCES……………………………………………………………………..196 Chapter 1……………………………………....................................................196 Chapter 2……………………………………....................................................199 Chapter 3……………………………………....................................................207 Chapter 4……………………………………....................................................209 Chapter 5……………………………………....................................................210 Chapter 6……………………………………....................................................211

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FIGURES

1.1

Average whole body SAR as a function of frequency for models of an average man in free space for three polarizations, E, H, and K……...…………………8

1.2

Schematic drawing of the proposed inductive link………………….…………9

1.3

Thin film 10-turn copper coil…………………………………………………10

1.4

Oscillograph of input (1) and output (2) voltages for an inductive link with 10turn driving coil and receiving coils, at an air gap of 2 mm……..…………...11

1.5

Power delivery efficiency of test inductive link with a thin film 10-turn receiving coil to different loads………...…………………………………….12

1.6

Schematic cross-sectional view of the proposed on-chip receiving coil……..13

2.1

Gyrator-based active inductors in (a) single-ended and (b) floating configurations…………………………………………………………………29

2.2

(a) A square spiral inductor, (b) a symmetric spiral inductor and (c) a tapered spiral inductor…………………………………………………………….......32

2.3

Schematic representation of substrate currents……………………………….37

2.4

Conventional model for integrated spiral inductors on Si substrates…………38

2.5

Die photo of the VCO presented by J. Craninckx et al., which used four bond wires to implement two inductors………...…………………………………..42

2.6

SEM photographs of vertical bond wire inductors…………...………………43

2.7

Cross-sectional view of a spiral inductor fabrication in a 5-level Al interconnect process…………………………………………………….…............45

2.8

SEM cross-sectional view along the center line of the spiral inductor structure shown in Fig. 2.6……………………………………………..........................46

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3.1

Electroplating-related processes. (a) copper damascene and (b) LIGA………………………………………………………………………….54

3.2

Inlaid electroplating process flow…………………………………………….57

3.3

HEXSIL process……………………………………………………………...58

3.4

Inlaid coil layout……………………………………………………………...59

3.5

Coil mold by AZ 4620P………………………………………………………60

3.6

Reverse image of coil mold by AZ 4620P……………………………………61

3.7

Cracks of AZ 4620P……………………………………………………..........62

3.8

The convex corners of silicon coil mold after (a) 5 minutes and (b) 20 minutes of KOH etching……………………………………………………………….63

3.9

Mask layout with corner compensation structures……………………………64

3.10

Simulated KOH etching results by IntelliSuite™ after (a) 5 minutes and (b) 20 minutes etching………………………………………………….....................65

3.11

Surface profile of trench bottom by DRIE with photoresist mask……………68

3.12

Surface profile of trench bottom by DRIE with aluminum mask…………….68

3.13

(a) Silicon trenches formed by deep reactive ion etching and (b) surface of the sidewalls……………………………………………………………................69

3.14

Photoresist coverage of trench bottom…………………………………..........70

3.15

Optimization of copper etching by various CE-100:DI water ratios…………71

3.16

Scanning electron micrograph of electroplated copper coil. (a) whole coil and (b) local uniformity…………………………………………………………...74

3.17

(a) Outer turns and (b) inner turns of a 20-turn Cu coil electroplated at 2 A and without reverse pulses………………………………………………………...75

3.18

Scanning electron micrograph of plated coil after polishing…………………77

3.19

Surface profile of polished coil……………………………………………….77

3.20

Copper coil damaged by high speed polishing……………………………….78

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3.21

KOH removal of silicon sidewalls (a) along copper lines and (b) under between the opening…………………………………………………………..79

3.22

Electroplated coil after sidewall removal……………………………………..79

3.23

(a) Selective removal of silicon substrate and (b) undercutting of Cu line to form overhang structure………………………………………………………80

3.24

A section of Cu line torn off Si chip to test its adhesion………………..........81

3.25

Equivalent circuit of an integrated coil…………………………………….....82

3.26

Impedance versus frequency of 10-turn thin film and electroplated coils with and without sidewalls…………………………………………………………84

3.27

Impedance versus frequency of 20 turns thin film and electroplated coils with and without sidewalls…………………………………………………………85

3.28

Quality factor of fabricated microcoils……………………………………….88

4.1

Schematic drawing of a transformer……………………………….................92

4.2

Ideal transformer with a load ZL. (a) Schematic; and (b) equivalent circuit with load reflected onto the primary side…………………………………………..94

4.3

Magnetic flux coupled two coils……………………………...........................97

4.4

An inductive link with mutual inductance M…………………………………99

4.5

Equivalent circuits for inductive link in Fig. 4.4. (a) Direct form, (b) an ideal transformer model with the magnetizing inductor on the driver side, or (c) on the receivier side…………………………………………………………….102

4.6

Other equivalent circuit models of inductive links. (a) With current-controlled current sources, (b) with voltage controlled voltage sources, and (c) Tmodel………………………………………………………………………...105

4.7

Three link configurations with the driving coil placed, from left to right: (a) on the large arm, (b) on the small arm and (c) split coil………………………..108

4.8

Simulated magnetic flux density in and around magnetic cores…………….109

4.9

Magnetic flux density in the core and the air gap…………………………...110

4.10

Calculated coupling coefficient versus receiving coil diameter…………….111

4.11

Measured coupling coefficients for three driving coil placements………….113 viii

4.12

Measured integrated coil impedances and curve-fitting to obtain coupling coefficients……………………………………………………………..........115

4.13

Relationship between excitation voltage and current of a driving coil……...117

4.14

(a) Current components and (b) an equivalent circuit model of the driving coil of an inductive link……………………………………………….................118

4.15

Complex permeability of Phillips 3F3………………………………………119

4.16

Equivalent circuit models for coils (a) with an air core and (b) with a ferromagnetic core……………………………………………………..........120

4.17

Impedance of 20-turn split driving coil………………………………...........122

4.18

Equivalent circuit of an inductive link with integrated receiving coil………124

5.1

The Plexiglas fixture with the inductive link in place………………………125

5.2

Measurement setup for power delivery experiment of the inductive link…..127

5.3

The inductive link under test………………………………………………...129

5.4

Output power with different receiving coils and loads……………………...131

5.5

Equivalent circuit of the inductive link for powering……………………….132

5.6

Driving coil voltages and outputs versus frequency for inductive links with (a) electroplated coil and (b) thin film coil……………………………………...133

5.7

(a) Measured and (b) simulated output power for 20/10 test inductive link with tuned driving coil……………………………………………………………135

5.8

(a) Measured and (b) simulated output power for 20/10 test inductive link with tuned driving coil……………………………………………………………136

5.9

The concept of power delivery efficiencies of inductive link……………….137

5.10

Power transfer efficiency for links with various receiving coils and loads…138

5.11

Link equivalent circuit with efficiency definitions………………………….139

5.12

Commonly used equivalent circuit for inductive links……………………...141

5.13

Link efficiency to 50 Ω load with 10-turn plated receiving coil obtained from measurements and calculations…………………………………...................142

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5.14

Quality factors for 20-turn driving coil and 10-turn electroplated receiving coils with and without sidewalls…………………………………………….143

5.15

Link efficiency to 13 Ω load with 10-turn electroplated receiving coil by measurements and calculations……………………………………………...144

5.16

Link efficiency to 13 Ω load with 10-turn thin film receiving coil by measurements and calculations……………………………………………...145

5.17

Circuit representation for voltage gain of inductive link (a) With the parasitics lumped into the load, and (b) with an integrated receiving coil……………..146

5.18

Frequency dependency of voltage gain for test inductive link with open circuit receiver………………………………………………………………………148

5.19

(a) Input and output voltages, (b) voltage gain and phase shift of test inductive link with electroplated 10-turn coil open-circuited………………………….150

5.20

Voltage gain of link with various driving coils………………………...........151

5.21

Schematic of selective driving circuit……………………………………….153

5.22

Input (upper) and output (lower) of the selective driving circuit……………153

5.23

Stagger tuning schematic for inductive links using self-resonance of integrated coil…………………………………………………………...........................155

5.24

Output from the stagger-tuned inductive link in Fig. 5.23…………………..156

6.1

Circuit schematic for direct pulse transmission by inductive link……..........159

6.2

Direct pulse transmission results by inductive link…………………………159

6.3

Amplitude modulation scheme for waveform transmission………………...161

6.4

Outputs of thin film and electroplated coils from 100 kHz to 5 MHz for 200 Ω, 700 Ω and 1200 Ω loads…………………………………………………….164

6.5

(a) Oscillographs of input, carrier and output signals for 200 Ω, 700 Ω and 1200 Ω loads at a carrier frequency of 300 kHz…………………………….165

6.5

(b) Oscillographs of input, carrier and output signals for 200 Ω, 700 Ω and 1200 Ω loads at a carrier frequency of 2.6 MHz…………………………….166

6.6

Comparison of outputs from various receiving coil configurations………...167

x

6.7

The dependency of output levels on receiver capacitance……………..........168

6.8

Equivalent circuit for receiving coil with envelop detector…………………169

6.9

Amplitude modulation transmission of various waveforms………………...170

6.10

Output versus frequency at different input levels for electroplated coils with 200 Ω load with bridge rectification………………………………………...172

6.11

Comparison of outputs at 300 kHz from a 1200 Ω with half-wave rectification (upper) and full-wave rectification (lower)………………………………….173

6.12

Two rectifications with voltage doubling…………………………………...174

6.13

Outputs of thin film and electroplated coils with voltage doubling from 300 kHz to 3 MHz for 200 Ω, 700 Ω and 1200 Ω loads…………………………175

6.14

SPICE simulated outputs for various rectification schemes………………...176

6.15

Circuit schematic for selective waveform transmission……………………..177

6.16

Selective waveform transmission……………………………………………178

6.17

Biphasic waveform generation circuit………………………………………179

6.18

Biphasic waveform obtained at a single load resistor (1 kΩ)……………….180

6.19

(a) Crossover distortion in waveform generation and (b) compensation by input offsets………………………………………………………………………..181

7.1

Schematic drawing of the dual-coil design………………………………….186

7.2

Processing flow of dual-coil design…………………………………………187

7.3

Photoresist application on wafers with vias…………………………………188

7.4

(a) Patterned Al mask from non-conformal photoresist coverage, and the underneath oxide mask is visible; (b) the DRIE result with such masks……189

7.5

Silicon mold for dual-coil with through-wafer vias…………………………190

7.6

Electroplated copper through-wafer via……………………………………..191

7.7

Electroplated dual-coil after polishing………………………………………192

7.8

Released coil with the via going through the wafer…………………………193

xi

7.9

Backside view of through-wafer vias of various sizes………………………194

xii

TABLES

1.1

Electric properties of human tissues……………………………………...........7

2.1

MEMS devices and their activation principles……………………………….16

2.2

Maximum work output per volume and drive conditions for different actuation mechanisms…………………………………………………...........................19

2.3

Summary of actuator analysis by Koeneman………………………………....20

2.4

Magnetic material classification……………………………………………...34

2.5

Inductor characteristics with different structures………………………..........35

3.1

Extracted electrical parameters of thin film and electroplated coils………….87

4.1

Driving coil model parameters with and without Si chip in the air gap…….123

5.1

Physical parameters of the core and receiving coils………………………...126

xiii

ACKNOWLEDGMENTS

First of all, I express my deepest gratitude to my advisor, Prof. Gary H. Bernstein. Thanks to his mentoring, my four years’ graduate study at Notre Dame was far more rewarding than I could ever have expected. I feel most fortunate being exposed to his work ethic, commitment to excellence, acumen and charisma, in addition to professional training. Hard work became easier with his understanding, patience and inspiration, and he may be the only advisor in the world to tell a graduate student to learn to sleep. I am very much obliged to my dissertation committee for their constant encouragement and assistance. Profs. Fay, Seabaugh and Snider have spared precious time out of their already hectic schedules for discussions on my project. Their honest and insightful comments make the dissertation more complete. I sincerely thank Prof. Kosel for help with polishing, and Mr. Vic Quinn, Tabtronics, Inc. for advice on transformer testing. Many thanks go to the faculty, staff and my student colleagues at the Dept. of Electrical Engineering, Univ. of Notre Dame. There are too many names to mention, Tanya Orlova, Yaakov Sloman, Trisha Metz, Shailendra Dubhashi, Xinyu Li, Jinli Wang, Yashan Sun, Yanyang Xu, Nathaniel Crain, … The list goes on.

xiv

Last but not the least, I must thank the sponsors: the Indiana 21st Century Research and Technology Fund and Bayer Corporation. The research would not have been possible without their support.

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CHAPTER 1

INTRODUCTION

In the past few years, considerable attention has been given to the development of microelectromechanical systems (MEMS), and so far the research activity in that field has been concentrated on sensors, actuators, and specific applications of the technology. One area that would benefit from continued development is how to provide power for microscopic sensors and actuators. Therefore, it is the purpose of this project to explore the feasibility of integrating a micro power supply with MEMS devices.

1.1

The development of Micro electro mechanical system (MEMS) In 1959, Richard P. Feynman gave his famous talk, “There’s Plenty of Room

at The Bottom1,” in which he proposed that it should be possible to develop a general ability to manipulate things on an atomic scale with a top-down approach. Ever since then, MEMS has evolved into an interdisciplinary research area, and has been gaining importance, developing in both scope and depth.

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The field of MEMS grew out of the integrated-circuit (IC) industry, and so exhibits many advantages indigenous to IC technologies. Based on downscaling principles, MEMS devices are inherently smaller, lighter and faster in response than their macroscopic counterparts.

With the adoption of advanced lithography and

etching techniques from IC processing, better device-to-device consistency can be achieved for MEMS devices. In addition, MEMS components can be monolithically integrated with electronics to develop systems-on-a-chip. These advantages have made MEMS a winning technology compared with conventional macrosystems or discrete devices. So far, quite a few micromachined devices or microsystems have already successfully established high volume commercial markets, including microfluidic devices in µ-TAS (micro total analysis systems) or nano-litre dosing systems 2 and inkjet print heads; accelerometers and pressure sensors for automotive applications; optical switches and relays, scanner, micro-mirrors; variable capacitors and inductors in microoptics and electronic systems3, 4; data storage systems such as the piggyback actuators of hard disk drives; AFM and STM for ultra high density recording/scanning. Sustained effort has been devoted towards this arena to bring about more and better devices. By combining microelectronic circuitry with micro- sensors and actuators, microsystems with added design flexibility and expanded functionality can be realized. Of special interest is to develop a method to release microsystems from power supply tethering in order to give them some degree of autonomy, and allow implantation of devices in biomedical or other applications.

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Although much progress has been achieved in fabricating discrete MEMS devices, relatively few complete systems-on-a-chip have been demonstrated. One major obstacle to system integration is that most MEMS devices, especially microactuators, have special requirements for their power supplies; some devices require high voltage, e.g. piezoelectric actuators, while some require high input power, e.g. bimorph actuators. It is the purpose of this project to explore the feasibility of integrating a micro power supply with MEMS devices, in order to decrease their overall size, increase their available energy budget, and free them from mechanical and electrical contacts. Micro electricity generation shares many of its mechanisms with microsensors (i.e. converting the changes in physical quantities into electrical signals): mechanical, optical, thermal, ion radiation, magnetic/electromagnetic, chemical and biological signal conversion. Based on the powering requirements of MEMS and implanted devices, using electromagnetic energy emerges as the optimal choice, which is fulfilled in the form of an inductive link. It should be added here that microfabricated coils have recently been adopted as receivers in inductive links5, 6, 7, 8, 9. The motivations are to reduce the size of the receiving side, to improve link efficiency by taking advantage of 3D microfabrication technology, and to integrate the receiver with other micro-devices to establish a more reliable system-on-a-chip.

With an ever-growing arsenal of

micromachining techniques, the fabrication and attributes of integrated receiving coils will continue to improve, which may eventually lead to successful commercialization.

3

1.2

Inductive links Inductive powering is an established field and extensive research has been

performed to analyze and optimize the operation of inductive links10, 11, 12, 13, 14, 15, 16. There exist numerous applications of inductive links to deliver power and data into remote or implanted devices 17 , 18 , 19 , such as RF powered ID tags 20 , inductively powered smart cards21, or non invasive pacemaker battery recharging22, 23, 24, etc. Limited by manufacturing techniques, wire-wound receiving coils are bulkier than those fabricated on chip, and require extra bonding and packaging steps for connections with IC loads, as compared with integrated coils. However, due to the planar fabrication process, integrated coils suffer from less flexible layouts and noticeable parasitic effects, namely parasitic resistance and capacitance. A good analogy can be found in printed-circuit board coils25, 26, but coil parasitics are much more pronounced with integrated coils because of their smaller dimensions. Eddy currents in conductive silicon substrate also cause parasitic effects, which will be discussed in this dissertation. With modern microfabrication technology, integrated coils for inductive powering have been successfully demonstrated18 – 22. However, in these reports, no details of the driving coils or analysis of the inductive link, such as coupling coefficient and efficiency, were provided. Even though the analysis and design of conventional inductive links have progressed to a sophisticated stage, those developed strategies are targeted at links with wire-wound coils and require modifications when

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dealing with links using integrated coils. Therefore, it is the interest of this work to investigate the parasitic effects of integrated coils and their impact on inductive links. In biomedical applications, inductive links are also known as transcutaneous transformers, since energy is transmitted from the external driving coil to the receiving coil inside the body, without wires penetrating the skin. Typically, they are operated at frequencies of optimum efficiency, and there are no special requirements on the waveforms.

However, there exist cases where signals of certain waveform and

frequency are preferred, for instance deep brain stimulation (DBS). Given that typical values of pulse width for DBS are 50 to 90 µs 27 , waveforms would be severely distorted when transmitted directly through a transcutaneous transformer because of small time constants (discussed in section 6.1). So, it is understandable that pulse generators are implanted for such applications. However, it will be shown in the dissertation that using amplitude modulation and demodulation, the pulse trains can be reproduced at the output with high fidelity, irrespective of pulse width. In addition, parasitic capacitance of integrated coils causes inductive links to resonant at a certain frequency, which can be utilized to obtain extra voltage gain. Since transmitting energy and signal inductively is the major topic of the dissertation, it is relevant to mention briefly here the influences of electromagnetic field on media, especially biological effects. Of all the biological effects induced by electromagnetic radiation, the most prominent ones are thermal, in which electromagnetic energy is converted into thermal energy, resulting in tissue heating. Body tissues are basically non-magnetic. There is little direct interaction between

5

magnetic fields and tissues, but time-varying magnetic fields can induce time-varying electric fields. An electric field E passing through a medium of conductivity σ can generate heat at a rate of σE 2 . The biological absorption of EM fields is indicated by a “penetration depth,” which is defined as the distance at which the power density of the propagating wave decreases to 1 e 2 of its value at the surface of the body. Table 1.1 gives electric properties and penetration depth of human tissues, which gives us an idea of the influences of electromagnetic waves on human body at various frequencies. More frequently, a term “specific absorption rate (SAR)” is used to indicate the intensities of the fields within the living body, which expresses the rate of energy absorption and is proportional to the square of the internal electric field intensity28. The average SAR over the whole body is given in Fig. 1.1 for a far-field (plane-wave propagation) exposure, in which E polarization denotes the electric field parallel to the body, H denotes the magnetic field parallel to the body and K denotes the wave moving from head to toe or toe to head29. The values are approximate. It is shown that there is a frequency at which maximum amount of RF power is absorbed in the exposed body. This frequency is called the resonant frequency. For human beings, maximum energy absorption takes place between 30 and 100 MHz, depending on the body size and the environment. Microwave radiation at frequencies above 800 MHz can produce injury to the eye.

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TABLE 1.1 ELECTRIC PROPERTIES OF HUMAN TISSUES30, 31

Frequency (MHz)

Muscle, skin and tissues with high water content

Fat, bone and tissues with low water content

σ (mS/m)

Penetration depth (mm)

σ (mS/m)

Penetration depth (mm)

1

400

913

--

--

10

625

216

--

--

27.12

612

143

10.9 – 43.2

1590

40.68

693

112

12.6 – 52.8

1180

100

889

66.6

19.1 – 75.9

604

200

1280

47.9

25.8 – 94.2

392

300

1370

38.9

31.6 – 107

321

433

1430

35.7

37.9 –118

262

750

1540

31.8

49.8 – 138

230

915

1600

30.4

55.6 – 147

177

1500

1770

24.2

70.8 – 171

139

2450

2210

17

96.4 – 213

112

3000

2260

16.1

110 – 234

97.4

5000

3920

7.88

162 – 309

66.7

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Figure 1.1 Average whole body SAR as a function of frequency for models of an average man in free space for three polarizations, E, H, and K. (The incident wave is a planewave with a power density of 1 mW/cm2.)

The inductive links investigated here operate over a frequency range lower than 10 MHz, where little energy absorption is expected, as evidenced in Table 1.1 and Fig. 1.1. Therefore, it is expected that exposure to electromagnetic fields in this work will involve fewer safety issues than will operation at higher frequencies.

1.3

Preliminary results One of the objectives of the dissertation is to identify and realize a feasible

strategy as a wireless, on-chip power supply to drive a bio-MEMS chip. Among

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several potential powering schemes, for example, micro-gas-turbine, solar cells and thermopiles, inductive powering distinguishes itself from the rest, because it alone combines the advantages of no moving parts, high reliability, efficiency, IC fabrication compatibility and ease of packaging. Besides, inductive links are versatile energy sources; with careful design, they can accommodate almost any energy requirement of MEMS devices, such as high power, high voltage, etc. The proposed inductive powering scheme is schematically shown as Fig. 1.2. An integrated coil is proposed as a medium to inductively couple electric energy onto silicon chips. The inductive link is composed of a wire-wound driving coil around a ferrite core and an integrated coil on a silicon wafer as the receiver. The core consists of two pieces with an air gap to accommodate the chip, and the integrated receiving

Fig. 1.2 Schematic drawing of the proposed inductive link.

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coil can move in and out of the air gap. Through the magnetic field generated in the air gap by the driving coil, energy is inductively transferred to the integrated coil. The receiving coils are designed as square spirals and are fabricated on a silicon wafer using technology compatible with CMOS process. As an initial proof of concept, thin film copper coils of 10-turn were fabricated as follows: thermal growth of oxide on silicon wafers, photoresist application and patterning, e-beam evaporation of 1.2-µm-thick Cu/Cr multi-layer, and patterning into spiral coils by lift-off. An optical micrograph of a fabricated coil is shown in Fig. 1.3. The internal resistance of the thin film coil is 95.5 Ω.

Fig. 1.3 Thin film 10-turn copper coil. (Coil lines are 80 µm wide at 100 µm pitch)

10

Preliminary results of the inductive link are given in Figs. 1.4 and 1.5, all at an air gap of 2 mm. For the inductive link with a 10-turn driving coil, 223.4 Vpp was obtained for an impressed voltage of 253.1 Vpp over the driving coil at 744.9 kHz, as shown in Fig. 1.4. Such a voltage is appropriate for the operation of such MEMS devices as electro- hydro- dynamic microfluidic pumps32, and many other devices, especially if integrated with a simple half- or full-wave rectifier bridge, with or without filtering or regulation 33 .

The power delivery through the coil was also

Fig. 1.4 Oscillograph of input (1) and output (2) voltages for an inductive link with 10-turn driving and receiving coils at an air gap of 2 mm.

demonstrated. Power of 8.11 Wrms was delivered to a 100 Ω load. It can be concluded that the integrated coils are capable of delivering usably high voltage and high power for applications in MEMS systems.

11

The maximum efficiency of power delivery to 100 Ω load is over 40%. However, as the load impedance is reduced, the efficiency goes down, as shown in Fig. 1.6, because the thin film coils have large internal resistance. As the load impedance becomes smaller, more and more energy is consumed by the receiving coil. Since many thermal actuators have low input impedance, e.g. a few ohms for shape memory alloy actuators 34 , reducing the coil internal resistance is critical to improving the efficiency of inductive powering. Therefore, it is our goal to develop a fabrication process to build microcoils with a thickness over several tens of microns,

Load 13 Ω 50 Ω 100 Ω

Power transfer efficiency (%)

40

30

20

10

0 10k

100k

1M

Frequency (Hz)

Fig. 1.5 Power delivery efficiency of test inductive link with a thin film 10-turn receiving coil to different loads.

12

and in the meantime keep the fabrication relatively low cost and compatible with standard CMOS processing. After an extensive literature review on integrated inductors and their fabrication techniques, which is presented in Chapter 2, a fabrication procedure is proposed to build microcoils with the configuration shown in Fig. 1.6. The coils are built into a silicon substrate by patterned electroplating, a fabrication procedure we called “inlaid electroplating.” The details of its development and the characterization of different microcoils will be given in Chapter 3.

Fig. 1.6 Schematic cross-sectional view of the proposed on-chip receiving coil.

With these fabricated microcoils, the proposed inductive link is investigated for its ability to deliver both efficient power and specific waveforms. Chapter 4 examines the magnetic coupling between the driving coil and the integrated coil by both finite element analysis (FEA) simulations and experiments. Based on the special effects introduced into inductive links by integrated inductors, the test inductive link is characterized with techniques modified from conventional methods.

Chapter 5

presents the results on power delivery with the inductive link. An equivalent circuit is 13

developed for the test inductive link and used to calculate the link efficiency. The experimental results on waveform transmission are given in Chapter 6, in which the parasitic capacitance of integrated coils is used to obtain enhanced outputs. Utilizing link resonance, signals can be selectively transmitted to multiple receiving coils with a frequency-multiplexed input. Based on research results in this work, a dual-coil fabrication process with electroplated through-wafer vias is developed for future monolithic integration of coils with electronics. Combining dual coils with discrete demodulation and switching transistors, biphasic signals are generated across a resistor representing body tissue. The above results offer the possibility of replacing implanted pulse generators with an external unit in coordination with implanted receiving coils and circuit components, which is one recommended direction for future work of this dissertation.

14

CHAPTER 2

LITERATURE REVIEW

2.1

Power requirements of MEMS devices To explore the feasibility of a MEMS power supply, it is necessary to

understand the power capabilities and requirements of micro devices. This includes determining the amount of energy required by a micro component to perform a task, the amount of energy needed as output from the power supply, and the amount of energy available from the power supply. Most MEMS devices being pursued can be categorized either as sensors or as actuators. The role of micro sensors is comparatively passive, collecting information from the environment, while that of micro actuators is to control the environment by moving, regulating, pumping, filtering, etc. As a result, micro actuators generally have more exacting power requirements than micro sensors. So in the following discussion, we mainly concern ourselves with the power requirements of micro actuators. To date, a large variety of MEMS devices have been prototyped and fabricated. The actuation mechanism of various integrated MEMS devices mostly fall into the following categories: electrostatic, electromagnetic, piezoelectric, and thermal

15

drive including thermopneumatics, thermal bimorph, and shape memory alloys. Table 2.1 lists some examples of MEMS devices that are realized by various actuation mechanisms.

TABLE 2.1 MEMS DEVICES AND THEIR ACTIVATION PRINCIPLES1 Actuation principle

Typical MEMS devices Micropump,

Piezoelectric hard disk drive servo system Microshutter, micromirror, Electrostatic microscanner, microrelay Electromagnetic

Microrelay, micropump, -valve

Thermomechanic

Microvalve, microgripper Micropump, microvalve,

Thermopneumatic phase conversion inkjet printhead Shape memory alloy

Microvalve, fiber-optic switch

Electrostatic force scales favorably with device dimensions. Therefore the electrostatic drive is a favorite actuation mechanism at the scale typical of MEMS. The major attractive characteristics include simplicity in operation and device construction, low power consumption, and relatively low sensitivity to temperature variations. Electrostatic drivers operate through the attraction of opposite charges, and

16

the actuation force is a function of the applied voltage. Consequently, electrostatic actuators have voltage as the primary input parameter, and often require a relatively high actuation voltage (e.g. >10 V), which is geometry-dependent. It is well known that electrostatic actuators exhibit large input impedances, requiring very low input current at static state (typically nA’s). Therefore, power consumption is typically small for electro-static actuators. Electromagnetic actuation provides a large force that is capable of both attraction and repulsion, because the operation of magnetic actuators depends on the attraction or repulsion between magnetic poles or moving charges and a magnetic field.

Since input current controls the magnitude of the actuation force through

magnetic fields, the operation of electromagnetic drivers requires a significant amount of current (typically mA’s), which translates to power. Piezoelectric actuators utilize the effect that an applied electric field produces an approximately proportional mechanical strain. Potential advantages include high stress (tens of MPa), high bandwidth, and high energy density. Disadvantages include more complex fabrication (sometimes a poling step is necessary, in which dipoles in the crystal are formed by prestressing) and relatively small physical deformation (strains on the order of 0.1% or less).2 Often, high voltages are required for both piezoelectric and electrostatic actuators, the magnitude of which is geometrydependent as well. Electro-thermal actuation can provide a relatively large force, but in general is highly temperature dependent and requires a non-negligible level of power to operate.

17

For most of the thermal drivers, it is the total heat energy that determines the amount of pressure applied to the membrane. Given the same input power, control over the resistance of the electric circuit provides some flexibility in meeting current and voltage limitations for those drivers. With bimetallic strip and shape-memory alloy actuators, the actuation material and electrical resistor are incorporated together. The actuation strength requirements place limitations on the geometry of the metal material and the resistance of the actuators. For this reason, current or power is the important input parameter for these drivers. To compare different actuator mechanisms, it is useful to introduce the term of work output per unit volume3, defined as

W=

Force × Displacement Volume

2.1

It is a useful parameter because it accounts for three of the four critical actuator parameters (response time is the fourth). The work output per unit volume and drive conditions for some actuation mechanisms are summarized in Table 2.2. The power requirements of microactuators are case-specific, as they depend on actuation mechanism, driver geometry, and other specifications of microsystems. A detailed survey of microactuator performance has been conducted by Koeneman4, as shown in Table 2.3, which may give us some general idea of what is to be expected from a micro power supply for an actuator to function as needed. Basically, microactuators require high power density or high voltage (compared to CMOS circuits such as modern microprocessors). It is important to bear this in mind when deciding on an electricity generation scheme. Various micro

18

electricity generators will be discussed in the next section, and their capabilities will be examined against their powering requirements.

TABLE 2.2 MAXIMUM WORK OUTPUT PER VOLUME AND DRIVE CONDITIONS FOR DIFFERENT ACTUATION MECHANISMS5 Maximum work Mechanism

Drive condition output per volume

Magnetic

9.5 x 105 Jm-3

1.5 T or 9.0 x 105 J⋅m-3

Shape-memory alloy

10.4 x 106 Jm-3

1.4 W mm-3

Electrostatic

4 x 105 Jm-3

3 x 108 Vm-1, 1 µm air gap

Piezoelectric

5.2 x 107 Jm-3

3 x 108 Vm-1, 1 µm-thick PZT film

19

TABLE 2.3 SUMMARY OF ACTUATOR ANALYSIS BY KOENEMAN4 Mechanism

Actuation strength

Input power requirements

Electrohydrodynamic

2.5 kPa

700 V

Ferromagnetic film

50 kPa

1.4 A

Piezoelectric

25 kPa

1000 V

Thermo-pneumatic

34 kPa

2.5 W

Thermo-responsive polymer

437 kPa

30 mW

Phase change

100 kPa

1.9 mW

Thermal buckling

100 kPa

3W

Shape-memory alloy

150 kPa

0.12 A

Bimetallic strip

50 kPa

0.5 A

Dielectric heating

4 Pa

10 V @ 4 MHz

2.2

Non-contact on-chip power supplies At present, MEMS devices are usually powered by external macroscopic

power supplies. On one hand, this strategy provides an energy source that is readily available, and generally can satisfy varied power requirements of different devices; on the other hand, such an approach necessitates external power connections. In many

20

applications, external power supplies are not a problem; however, in autonomous and implanted applications, wire tethering is undesirable. Therefore a non-contact on-chip power supply is predicted to be the next breakthrough in the development of MEMS. Additionally, micro power supplies can be distributed throughout a microsystem, permitting local control of each component that might have different power requirements from others, thus reducing the on-chip control system complexity.

Such a power supply should meet the following

requirements: small size, light weight, fabrication compatibility with micro elements, and satisfying the energy needs of MEMS devices. Another point that deserves attention is packaging.

In electronic device

fabrication, processes can be divided into three major groups: device fabrication; packaging (encompassing bonding, wafer scribing, lead attachment, and encapsulation in a protective body), and testing (including package leak tests and electricity integrity). The last two process groups are usually the most costly. In the case of MEMS devices, packaging and testing may become even more difficult and expensive, since oftentimes they are involved in chemical and/or mechanical measurements within a hostile working environment.

Thus, the reliability of interconnections is of paramount

importance under such circumstances; in fact, each interconnection is a vulnerable point. An on-chip power supply may be able to alleviate the packaging problem as it reduces the external connections.

21

The conventional solution for on-chip power supplies is to use energy cells, like batteries or fuel cells. However, a major problem here is that the weight and volume of energy cells tend to be disproportionately large compared with the microsystems they power, (scaling with a cubic dependency on dimension6), making on-chip energy sources (e.g., batteries and fuel cells) not very attractive for powering micro devices. So far, lithium-based batteries generate the highest specific energy of any commercially available battery. If the volume of the packaging is taken into account, energy volume densities of button lithium batteries6 may reach 8.6 x 105 to 1.3 x 106 J/L with physical sizes of 4.8 mm diameter by 1.4 mm high. Micro- batteries and fuel cells built with microfabrication technologies are still in the research stage, and the energy density of the complete, packaged battery so far has not exceeded 2 x 105 J/L, and the energy density of a hydrogen-oxygen fuel cell is even less7, about 6.5 x 103 J/L. For example, the specifications for a recently reported water activated microbattery8 are 1.65 V maximum output voltage and 1.8 mJ capacity for an electrode area of 12 mm x 12 mm, and 0.343 V of open-circuit voltage and 0.5 mW/L of power density for a microbial fuel cell9 with a chip area of 0.51 cm2. From the above summary, micro- batteries and fuel cells are undesirable for many applications due to their relatively large physical sizes, finite amount of energy, limited shelf life, and chemical hazards. Besides, there are some cases where the replacement of an energy cell is not acceptable, and an on-chip regenerating power supply will be more desirable.

22

To date, several on-chip regenerating powering schemes have been proposed, and some of them have already been implemented for their targeted applications. The following sources of energy have been reported for on-chip electricity generation: solar energy, nuclear energy 10 , fluid flow, thermal gradients, bio-electric effects 11 , energy produced by the human body12, mechanical vibration13 or acoustic energy, and electromagnetic fields. Solar energy or light can be converted into electricity through an integrated solar cell array on chip. A hydrogenated amorphous silicon (a-Si:H) solar cell array has already been demonstrated as an on-chip power source for electrostatic MEMS14, 15

. A series interconnected array of 100 single solar cells (a single cell of a triple layer

of p-i-n / p-i-n / p-i-n a-Si:H) occupies a total array area of 1 cm2, and produces an open circuit voltage of 200 volts, with a conversion efficiency lower than 5%. The current-sourcing ability of solar cell arrays is quite limited, so Sakakibara et al. 16 combined a solar cell array with a microwave antenna for devices of different powering needs. A drawback of implementing solar cells is that solar light is intermittent, so a backup power source or storage is often necessary. A photosynthetic electrochemical cell by Lam et al17 provides a different approach of utilizing light energy with stable output. In the light, the cell acts like a self-sustained solar cell by utilizing the natural photosynthetic processes of the blue-green algae Anabaena to convert light into electrical power. In the dark, it functions as a microbial fuel cell catalyzing into electrical power the glucose that it has accumulated during photosynthesis. The cell

23

can deliver an open-circuit voltage of 0.4 V and a power density of 61 µW/L in both light and dark. It takes up an area on the order of cm2 and its output characteristics need improvement for practical applications. Even though the photosynthetic electrochemical cell can operate for a short time without illumination, light sources are still required to generate electricity.

Therefore, for applications where external light

energy is unavailable, such as embedded microsystems, the implementation of lightconverting devices is not recommended. Instead of using incident photons, electrons emitted from radioisotope materials, i.e. nuclear radiation, can be used to generate voltage across p-n junctions, which is known as the betavoltaic or electron-voltaic effect.

A betavoltaic

microbattery has been recently reported by Guo et al.18, which has an open-circuit voltage of 0.128 V and a short-circuit current of 2.86 nA. Because of long life-time, no need for fuel storage, and integrability with microdevices, this is a promising strategy as a portable power supply, once its output power can be promoted to usable levels. Power generation by the alternate heating and cooling of a working fluid, i.e. fluid flow, on a chip has also been attempted, e.g. a micro-gas turbine. A 1 cm diameter by 3 mm thick SiC heat engine19 has been prototyped to produce 10-20 W of electric power while consuming 10 grams/hr of H2. While capable of providing large amounts of power, a micro- turbine suffers from several problems, such as the thermal isolation of heating and cooling sections, minimization of friction, and the difficulty of fabricating a flywheel. Packaging and further downscaling also pose an obstacle to

24

the implementation of a micro-turbine. Another type of micro power generation using combustion is based on thermionic emission. With an emitter (cathode) at elevated temperatures from combustion, electrons can gain enough thermal energy to overcome the work function barrier and be emitted to a cold collector (anode), thus generating electric currents. A first prototype was reported by Zhang et al.20 recently to generate ~ 1 µW power. Its advantage over mechanical engines is there are no moving parts, so it is relatively easy to fabricate, but its performance needs to be improved to be useful. Energy can be extracted from heat and temperature difference also by the thermoelectric Seebeck effect, which is used in thermocouples. Such thermo-electric converters are known as thermopiles when an array of miniature thermoelectric converters are connected in parallel electrically and thermally, generating electricity when placed across a temperature gradient. A thermoelectric generator module 21 consisting of 100 Sb-Bi thermocouple strips connected electrically in series and thermally in parallel was developed. The module has a thermoelectric output of 8.4 mV/K and is capable of generating a voltage of 0.25 V at a temperature difference of 30 K. The module has an overall dimension of 16 x 20 x 0.05 mm, which is relatively large.

Using micromachining techniques, a 3-D polysilicon based thermoelectric

generator of 1 cm2 in size was realized by Strasser, et al.22, which produces 5 V output voltage and 1 µW power over a temperature drop of 5K. The major disadvantage of thermo-electric converters is the very low conversion efficiency. Another interesting way to generate power is to utilize kinetic energy from movement, as used for several decades in wristwatches, or vibration.. Such a micro

25

electric generator was first proposed by Williams and Yates23, in which the conversion of mechanical energy is achieved either through variable parallel-plate capacitors with fixed-charge in electrets24, 25 or by the inductive interaction of a magnetic mass with a planar pick-up coil.

Piezoelectric materials were also suggested as a possible

transduction mechanism26, 27. Mechanical energy can be captured capacitively through re-distribution of electric charges between two variable capacitors, and the output magnitude depends on the charge implanted in the electret. The implantation of electrets is still under active research. Results by Boland et al.28 give an effective charge density of – 2.8x10-4 C/m2. The output is still on the order of µW. More success was obtained with electromagnetic transduction.

The output power was

predicted to produce power proportional to the cube of the frequency of vibration, producing 1 µW at 70 Hz and 0.1 mW at 300 Hz with a typical device of around 5 mm x 5 mm x 1 mm, assuming a deflection of 50 microns. However, due to the spring stiffening effect, Yates et al. 29 generated a maximum RMS power of only 0.3 µW at a resonant frequency of 4.4 kHz. With optimized spring design, Ching et al.30 produced from a 1 cm3 generator a 4.4 V peak to peak output voltage, which gave a maximum RMS power of 830 µW with a load of 1 kΩ. The external vibration was from 60 to 110 Hz with ~200 µm amplitude.

Similarly, Amirtharajah et al. 31 used an

electromagnetic transducer to convert acoustic energy for a low power signal processing system, which consumes 18 µW power. The incident acoustic field was calculated to be 114 dB, which makes the implementation impractical for most environments.

26

In the foregoing mechanism, mechanical energy was captured via electromagnetic fields. Energy can be transmitted electromagnetically through many formats. One strategy for on-chip electricity generation is to build an electric motor, which in turn generates electricity. Suzuki et al32 built a micro-generator based on this principle: two pairs of exciting coils produce a low frequency rotating magnetic field, which is applied to the implanted magnet. Then, a micro-generator is driven by the rotation of the magnet. With exciting current of 0.48 A at 16.7 Hz, a maximum power of 14 mW is obtained. The excitation frequency is limited to 16.7 Hz because of the mechanical stress of the generator. The most common strategy is to build an on-chip inductor, inductively coupling power to integrated devices. Its on-chip implementation involves only a passive receiving coil. After integration of coils with microdevices, there will be no exposed contacts to corrode and no risk of electric leakage. The increased reliability and safety are important for implanted biomedical applications. In addition, inductive links can deliver signals to implanted devices. The outputs are readily adjustable from the macro, driving side, rendering inductive links versatile. Inductive links have demonstrated many advantages over other powering schemes, and this scheme along with integrated receiving coils is chosen for powering micro devices in this dissertation.

The following section will review the

implementation of integrated coils.

27

2.3

Integrated inductors The receiving coil of the inductive link is virtually an inductor, so, for the sake

of completeness, it is relevant to provide some background on integrated inductors. Integrated passive devices, especially inductors, are less developed in Si integrated circuits than active devices such as transistors. One major reason is the scaling. Active devices can be scaled down, consuming less chip real estate, and still preserve their electrical properties, whereas passive devices have to rely on material properties and geometries to maintain their values, thus occupying large chip area. High quality factor (Q) integrated inductors are even harder to build due to loss mechanisms such as conductive substrates and ohmic losses from thin metal strips. As a result, inductances are sometimes emulated using on-chip active devices to increase integration density.

Fig. 2.1 shows general forms of implementing

inductors through gyrators with inductance given in the figure33. Because the purpose of building an integrated coil is to intercept magnetic flux, which can be achieved only through passive coils, active inductors will not be discussed further in this work.

28

Figure 2.1 Gyrator-based active inductors in (a) single-ended and (b) floating configurations. (Adopted from Ref. [33])

29

Integrated coils do not have a mainstream Si process, and much experience has been borrowed from the development of monolithic microwave integrated circuits (MMIC) on GaAs. However, it is more challenging to build microcoils of high quality factor on Si substrates due to the following differences between the Si and GaAs technologies: GaAs is semi-insulating, resulting in negligible substrate losses, and thick electroplated gold interconnects are typically used in GaAs MMIC, leading to lower ohmic losses in microcoils, as compared with aluminum metallization in Si technology. The advent of copper damascene34 technology offers a two-fold reduction of interconnect resistance, thicker metal layers for a given pitch and the vias between the mater layers can be wider than tungsten vias used in conventional Al VLSI interconnects.

Besides this, a multitude of measures have been experimented to

improve the performance of Si integrated coils, which will be mentioned later in this section. Passive inductors can be configured as loop, meander, spiral or solenoid geometries. The inductance of passive inductors is composed of self inductances of metal lines and mutual inductances between metal lines. The mutual inductance is positive when the currents flow in the same direction in the lines and negative for currents in the opposite directions. Consequently, because of positive mutual coupling between metal lines, spiral and solenoid inductors tend to provide higher inductance given the same overall length of metal lines. In Chapter 4 and later it will prove to be important to understand the equivalent circuit for modeling the integrated inductors, including parasitic resistances and

30

capacitances. For this reason, it is useful to review several issues in determining intrinsic electrical properties, and how these parameters are distributed on the physical device.

Generally, integrated spiral inductors are used to receive magnetic flux

incident through chips, so here the discussions focus on square spiral inductors. Figure 2.2 shows a square spiral inductor and its variations. Because of the close proximity of metal lines and conductive substrates, electrical energy is stored between the lines, leading to parasitic capacitance. The parasitic capacitance and resistance are distributed throughout the integrated inductors, but not uniformly. Problems arise when it is necessary to center-tap an inductor for applications such as in differential circuits. For a simple spiral such as in Fig. 2.2(a), a symmetric center point for the “inductive” center is different from those for the “resistive” center and “capacitive” center. Therefore, symmetric structures like the one in Fig. 2.2(b) have been proposed35. This structure possesses an electrical center (common node) that is critical to differential circuits, as such centers can be grounded or connected to supplies without distorting differential signals.

If two inductors are used for

differential circuits, some separation is required to reduce the negative magnetic coupling between the two coils, so the circuits will be less compact. With differential excitation at Ports 1 and 2, the voltages on adjacent conducting strips are 180° out of phase, however, current flows in the same direction along each adjacent conductor. The design is claimed to produce an improved Q because of reduced impact from the substrate shunt parasitics and still mutually enhanced magnetic fields by the parallel groups of conductors. Figure 2.2(c) shows a tapered spiral inductor. The metal pitch

31

and width are reduced from the outside to the inside in order to increase the open area inside the spiral. The reason for tapering is that the magnetic field is the strongest in the center of the spiral36, so current constriction caused by eddy currents is the most serious for the inner turns.

At operating frequencies, conductor width that can

effectively reduce resistive loss might be smaller for inner turns than for outer turns. Therefore, tapered coils are proposed to move the metal lines towards the outer edges in order to increase coil inductances, while maintaining a possibly low resistance, hence an optimal quality factors.

Note tapering is most effective in improving

inductor quality factor when current constriction dominates the loss mechanisms, e.g. for inductors on insulating substrates.

(a)

(b)

(c)

Fig. 2.2 (a) a square spiral inductor, (b) a symmetric spiral inductor and (c) a tapered spiral inductor. (Adopted from Ref. [33, 35]) Current constriction in the metallization is more pronounced at high frequencies, which are also known as skin and proximity effects.

The current

distribution in metal layers is affected by electromagnetic fields generated by itself or

32

other nearby devices. Time-varying currents in the conductors generate time-varying magnetic fields that in turn penetrate the conductors and produce opposing electric fields within the conductors. As a result, currents tend to accumulate at the outer layer or skin of conductors. For an isolated conductor, the magnetic fields originate from the conductor itself (the self-inductance). This increase in AC resistance is known as skin effect, and the effective depth of penetration δ of the current or the skin depth is expressed as: δ =

ρ πfµ

2.2

where ρ, µ and f represent resistivity in Ω-m, permeability in H/m, and frequency in Hz. In a multi-conductor system, a conductor is affected by magnetic fields from its neighboring conductors in addition to the self-magnetic field. Therefore part of its AC resistance is attributed to proximity effects, the effect of nearby conductors, which may add to or subtract from skin effect, depending on whether the nearby-magnetic fields enhance the self-magnetic field.

With spiral inductors, proximity effects

increase the AC resistance further. Table 2.437 gives magnetic susceptibilities χ of different types of materials, which is related to relative permeability µr as µ r = 1 + χ µ0 , and it can be seen that most materials used in microfabrication

(paramagnetic and diamagnetic) behave as vacuum to magnetic field. With Eq. 2.2 and Table 2.4, effective dimensions of metallization can be roughly determined at operating frequencies. Further increase of conductor size beyond these will not reduce ohmic losses significantly.

33

TABLE 2.4 MAGNETIC MATERIAL CLASSIFICATION Category

χ/ µ

Examples

Ferromagnetic

107 to 102

Ni, Fe, Co, NiFe, NdFeB

Ferrimagnetic

104 to 10

Fe3O4, ferrites, garnets

Antiferromagnetic

SMALL

MnO, NiO, FeCO3

Paramagnetic

10-3 to 10-6

Al, Cr, Mn, Pt, Ta, Ti, W

Diamagnetic

-10-6 to -10-3

Ag, Au, C, H, Cu, Si, Zn

Superconducting

-1

YbBa2Cu3Ox

The thickness of metallization in microelectronics is typically around 1 micron, so skin effect becomes noticeable only at frequencies higher than a few gigahertz. For lower frequency applications, reducing ohmic losses in the coil is still an effective method to improve the quality factor Qmax, which is defined as the ratio of magnetic energy stored in the coil to the energy losses in one oscillation cycle. Table 2.5 summaries the characteristics of inductors mostly fabricated by Burghartz et al.38 – 45 The coil inductance increases with coil area and turn numbers. For the first three inductors, with the same coil area and turn numbers, the maximum quality factors increase with the coil thicknesses. It can also be noted that the metal thickness does not have any appreciable noticeable impact on the coil inductance.

34

TABLE 2.5 INDUCTOR CHARACTERISTICS WITH DIFFERENT STRUCTURES Coil structure

Area (µm2)

Turns

L (nH)

Qmax

fSR (GHz)

4 µm Cu on Quartz38

226 x 226

3

1.5

60

>20

2.5 µm Cu on Sapphire39

226 x 226

3

1.45

40

>20

M3/M2/M1 on p-- Si40

226 x 226

3

1.45

24

>20

suspended M241

~ 200 x 200

4

1.1

28

84

M3/M2/M1 on p-- Si42

226 x 226

4

2.1

9.3

~20

M2 on perforated GND43

~ 280 x 280

6

8

7

3.5

Multilevel spiral on p-- Si44

226 x 226

8

6.8

7.8

5.6

M2 on p-- Si45

230 x 230

9

9.7

3

2.5

M1= metal level 1

Another concern with the integration of a spiral inductor is the conductive nature of silicon substrates, which causes energy losses and poses frequency limitations. The resistivity of Si substrates varies from 10 kΩ-cm for lightly doped Si (1013 atoms/cm3) to 0.001 Ω-cm for heavily doped Si (1020 atoms/cm3). There are several loss mechanisms associated with conductive silicon substrates. First, electrical energy is coupled to the substrate through displacement current. This displacement current causes potential variations across the dielectric isolation, and thereby inducing conduction currents through the substrate to nearby grounds, either at the surface of

35

the substrate or at the back. Second, induced currents flow in the substrate due to the time-varying magnetic fields penetrating the substrate. These magnetic fields produce time-varying solenoidal electric fields which induce substrate currents, known as eddy currents.

Other loss mechanisms can be lumped into radiation.

The schematic

representation of substrate currents is shown in Fig. 2.346, and a lumped equivalent circuit of integrated coil is given in Fig. 2.4 with ground at the back of the substrate47. In Fig. 2.4, L0 is coil inductance, R0 is coil series resistance, CS is the capacitance between coil lines, COX represents the distributed capacitance between the coil and the substrate, and Rsub and Csub account for the signal and energy dissipated in the substrate.

36

Fig. 2.3 Schematic representation of substrate currents. Dashed lines denote eddy currents and solid lines denote displacement currents. (Adopted from Ref. [46])

To reduce the substrate loss, common methods employed are to use high resistivity silicon 48 , sapphire substrates 49 , or glass 50 , selectively etch the substrate underneath 51 , suspend the inductor 52 , insulate the inductor from the substrate with thick polyimide53 or oxidized porous silicon54. Other schemes are also developed such as blocking eddy current in the substrate with p-n junctions55 or a patterned metal ground plane53, or disordering the lattice of the Si substrate with ion-implantation56. These strategies are not well suited for IC integration, therefore the design and fabrication procedures of Si inductors are still largely application-specific.

37

An

Fig. 2.4 Conventional model for integrated spiral inductors on Si substrate. (Adopted from Ref. [47])

interesting observation by Burghartz57 is that “for the same fabrication process a small inductance value typically combines with a higher Qmax than a large inductance, and

vice versa.” The supporting data are given in the lower half of Table 2.4. It is surmised to be “a result of the substrate losses: an increase of the number of turns in the spiral coil or an increase of the coil area results in an increased magnetic flux” into the substrate. Substrate losses become relatively significant only at high frequency, as it can be calculated that the skin depth of silicon exceeds 50 mm at our maximum operating frequency of 10 MHz for 10 Ω·cm substrate, but metal resistance plays an important role for all frequencies. As a result, minimizing coil resistance has a higher priority with our project, and the dissertation will focus on how to reduce metal resistance.

38

2.4

Inductive links with integrated coils Among the great diversity of on-chip powering strategies, inductive links stand

out as reliable, efficient and versatile. As a result, much effort has been devoted to this area, and many designs have been proposed and experimented with. So far, the inductive links being pursued can be classified into two major groups: fully integrated transformers and loosely coupled inductive links. As the name implies, fully integrated transformers have their driving coils (or primary coils), receiving coils (or secondary coils), and, in some cases, cores, all integrated on the same substrate, which is not necessarily silicon. Fully integrated transformers are mainly used for on-chip DC-DC converters58, 59, 60, 61, 62, 63, 64, 65, 66, and obviously need physical connections to external power supplies. One exception is an opto-electric transformer proposed by Kimura et al67, in which a p-n junction photocell is monolithically integrated with a multilayer spiral coil transformer. The power is provided by a laser diode (LD) or light emitting diode (LED), converted by the photo-cell into photo-current, then delivered to the load via the miniaturized transformer.

Clearly, no physical contact is made between the transformer and

external power sources, however this design does not show much advantage over a solar cell array. The low efficiency in converting optical energy into electricity is an intrinsic weakness of opto-electrical devices.

Integrating a transformer with the

photo-cell only changes the output voltages or currents. In this case the maximum power that could be generated was 10.83 mW.

39

Oftentimes, wireless power delivery onto a chip is achieved by inductively coupling electromagnetic energy to an integrated coil. The driving coils can be wirewound, and there are no physical contacts between the integrated receiving coils and the driving coils, and magnetic cores if any. By inserting the receiving coils into the magnetic paths or fields produced by the driving coils (and magnetic cores), energy is coupled onto the chip. Some applications incorporate ferromagnetic materials with the integrated receiving coils to increase electromagnetic coupling68. Integrated receiving coils can find a wide range of applications for telemetry and implantable devices. Von Arx and Najafi69 have fabricated a receiver chip that transmitted 15 mW of DC power to a 2.5 ohm load over a distance of 3 cm, and supplied 3 mA DC at 4V to an integrated microsystem. The integrated receiving coil was about 10 µm thick, built from electroplated copper with an electroplated NiFe core underneath it. At sizes of 2 mm by 10 mm and 10-turn, the coil had 2.70 µH inductance and 10 ohm resistance. Another attempt was made by Dudenbostel, et al70. The output voltage of their transformer at the secondary terminals was 15 Vpp at 5 mm distance from the primary and 8 Vpp at 7.5 mm. Their coil had 38-turn, 6.3 µH inductance, and 18 ohm resistance. Through external discrete diodes and capacitors, Takeuchi et al.71 used the outputs from the integrated coil to drive an electrostatic actuator. These experiments demonstrated IC fabrication compatibility and the ability to drive a circuit. It is an established fact that integrated coils have significant parasitic capacitances, which form LC tank circuits with coil inductances, causing the coils or

40

the circuits involving the coils to resonant at a certain frequency. This property has been utilized to transform an integrated coil into a capacitive sensor72, 73, 74, 75. With appropriate coil configurations and/or coating of chemical sensing materials, the coil parasitic capacitances can be altered with changes in temperature, pressure, humidity, complex permittivity, biological growth, etc. The variations in coil impedances are remotely interrogated with antennas via inductive coupling between the integrated coils and the antennas. These are a different type of application for integrated coils in inductive links, and the monitoring methods are passive and well suited for in situ and

in vivo applications. However, it is not the interest of this dissertation to pursue passive sensing via inductive links. In the future, passive telemetry76 or signaling77 may very well be combined into our inductive powering setup, and these applications will serve as very helpful references with respect to determining resonant frequency passively.

2.5

Fabrication of low resistance microcoils As discussed previously, integrated inductors suffer from significant resistive

loss due to the inability of planar fabrication to produce metallization of large cross sectional area. So far, no standard process to fabricate integrated inductors has been established in CMOS technology yet, and consequently the research has developed in several directions. Bond wires are commonly used in IC fabrication for electrical connections between chips and their packages.

Because of their large cross sectional area

41

Fig. 2.5 Die photo of the VCO presented by J. Craninckx et al., which used four bond wires to implement two inductors. (Adopted from Ref. [84])

(conventional bond wires are made of gold with a diameter of about 1 mil or ~25 µm), they have been experimented as on-chip inductors78, 79, 80, 81 82, 83. Figure 2.5 is a die photo of a voltage-controlled oscillator in which four bond wires were bonded across the chip to implement two inductors84. The DC inductance of a straight wire with circular cross section can be estimated as85:

Lself =

µ0l  2l   ln − 0.75  2π  r 

2.3

where Lself is the inductance in Henries, l is the wire length in meters and r is the radius in meters as well. It is assumed in the equation that the effects of nearby conductors are negligible, that is, the return current is far away. According to this equation, the inductance of a typical bond wire is about 1 nH/mm. With this method,

42

the bond wire has to stretch over a long distance, so achievable inductance is limited by chip dimensions. Another approach is to employ vertical bond wire loops and bond pads to realize lateral coils on-chip82, as shown in Figs. 2.6 (a) and (b). This design also places electromagnetic fields in parallel to the substrates, thus reducing eddy currents.

(b) Fig. 2.6 SEM photographs of vertical bond wire inductors: (a) type I and (b) type II. (Adopted from Ref.[82])

43

Kim et al. obtained Q=16.5 and 3.4 nH for (a) and Q=18 and 5 nH for (b). Despite bond wires’ low resistivity and ready availability in any IC technology, they have many disadvantages. The routing of bond wire inductors is cumbersome and bond pads are required, which are typically 100 µm by 100 µm. The controllability and consistency of bond wire inductance is also problematic. Therefore this technique is not widely employed. Another option is to utilize multilevel metallizations in IC technologies: shunting several levels of metallization in parallel to reduce the metal resistance86. Currently, this method is the dominant technique for fabricating integrated coils. Presently, IC technology routinely utilizes 5 or 6 levels of interconnects. The top layer metal is generally the thickest, around 1 – 2.5 µm, and the lower layers are typically around 0.7 – 1.0 µm. The interconnects are embedded in a dielectric layer, which is typically 4 – 7 µm thick. Several layers of metal can be shunted together to reduce the specific resistance of the metal lines. For the inductor shown in Fig. 2.7, the metal layers M3 – M5 were shunted to reduce coil series resistance, and the layer M1 was left out to reduce capacitive coupling to the substrate. Corresponding to Fig. 2.7, Fig. 2.8 gives a cross-sectional view of the fabricated inductor87. In VLSI techniques, tungsten (W) is typically used as vias, and its resistivity is about three times as high as that of Al. Therefore, this approach has limited effectiveness. At high frequencies, shunting multilevel interconnects is even less effective in reducing resistance because significant eddy currents are induced in different metal

44

Fig. 2.7 Cross-sectional view of a spiral inductor fabrication in a 5-level Al interconnect process. (Adopted from Ref. [86])

layers due to their close proximity, which leads to current constriction88. In addition, the interlayer capacitance is large, which is undesirable for high-frequency applications. Currently, research on achieving low-resistance microcoils focuses on fabricating metal strips with low specific resistivity.

Besides adopting gold and

copper as metallizations, increasing metal volume is of special interest.

Several

representative coil fabrication methods are available using IC processes, and they are briefly described below:

45

Fig. 2.8 SEM cross-sectional view along the center line of the spiral inductor structure shown in Fig. 2.7. (Adopted from Ref. [86])

1. Metal coils are formed by etching metal films masked with coil patterns89, 90. Since anisotropic etching of metal is hard to achieve, this method is not suitable for fabricating coils with high aspect ratios. Besides, to be IC process compatible, metal films are usually sputtered91 on the substrate and limited to less than 10 µm thickness. 2. A seed layer is deposited and patterned into coils, then a thick metal layer is formed by electroplating from the patterned seed layer. This method is also not suitable for forming high aspect ratio coils, since the plating rate is isotropic in the plating solution.

46

3. A seed layer is deposited first; on the seed layer, a coil mold is formed from an insulating mask material, which can be photoresist or polyimide; then metal layers are formed in the coil mold by electroplating. Subsequently, the mold is removed, the seed layer on the bottom of the mold is also removed, and again the space between the conductors is filled with insulating material. So far, this is the most popular and successful method for the fabrication of thick metallic microstructures92. Since it is highly desirable that the fabrication of coils is IC compatible, electroplating becomes a strong candidate. This deposition technique is characterized by low cost, low deposition temperature, a high geometric conformity and the possibility of achieving thick layers. It finds a wide range of applications such as fabrication of thin-film recording heads and microelectronic circuit bumps for tape automated bonding. Presently, this technique is being applied to the fabrication of MEMS devices. The success of electroplating depends on a number of specific requirements. These include a suitable seed layer, a compatible mold and the control of the deposit properties. It is not trivial to build a mold that can retain its form and adhere well to the substrate in the aggressive electrodeposition solution throughout the process; in fact, finding/creating appropriate molding materials and mold-forming techniques is the core difficulty and still under intense research. Presently, two kinds of materials, i.e. photoresists and polyimides, are widely used as molds in microelectronic

47

technology. Some exotic methods, like stenciling, have also been reported to be used in surface mount technology93 and four-level VLSI bipolar metallization designs94. The maximum thickness of electroplated material is limited by the thickness of the mold, which in turn is determined by lithographic technology.

To generate

microstructures of a few hundred microns thick, the best known technique is LIGA95 (German acronym for Lithografie, Galvano-formung, Abformung, i.e. lithography, electroforming, and molding). The key step in the process is to expose a thick (1001000 µm) layer of an X-ray sensitive photoresist, usually PMMA with an X-ray source such as a synchrotron. LIGA process can achieve extremely high aspect ratios, up to 100, for thicknesses of 300 µm or more. However, synchrotron exposure is critical to obtain thick molds, and its availability seriously hinders the exploitation of this technique. A second process, known as the LIGA-like process, uses UV optical lithography equipments for both negative and positive tone resists 96 , but the mold thickness is usually limited to less than 20 µm. Multiple coatings are required to achieve thicker layers, and microstructures with thicknesses of 80 µm have been realized97 . A negative tone resist, SU-8, can be spun up to 1 mm thick, but it is insoluable in most chemicals after development. Therefore, the removal of SU-8 obstructs its application in electroplating. As a matter of fact, SU-8 itself is often used as a microstructure material.

Recently, Ghantasala et al.

98

reported a process

removing SU-8 electroplating molds by excimer lasers, with which the removal of large area material is still a problem.

48

Besides photoresists, polyimides can also be employed as electroplating molds too. The conventional procedure is to pattern photoresists over polyimides, then dry etch unwanted polyimide through the photoresist openings, thus forming the mold. The requirements of lithographic equipment are much less stringent for this method. In addition, UV-exposable, negative-working, photosensitive polyimides, which have spun-on thickness in excess of 60 µm for a single coat, are now commercially available. Frazier and Allen99 have successfully created a new molding process using photosensitive polyimides, and fabricated high aspect ratio microstructures with height up to 50 µm. Although the properties of polyimide molds are inferior to that achieved through the LIGA process (thickness less than 50 µm, and aspect ratio less than 10), it is more likely to be accepted as a micromachining process than LIGA due to its relatively low cost and freedom from ion-bombardment. Of the above-mentioned molding techniques, polyimide molds by UV lithography are commonly employed to fabricate 3-D microcoils. Since electroplating is quite capable of making contacts between different levels of metallizations, multilevel microcoils with single layer thickness of up to 40 microns100 have been realized. So far, the realized microcoils utilize gold or copper metallization. Although a large number of metals and metal alloys are electrodeposited in conventional electrodeposition processes (about 17 metals are commonly electroplated from aqueous solutions: Cr, Fe, Co, Ni, Cu, Zn, Ru, Rh, Pd, Ag, Cd, In, Sn, Ir, Pt, Au and Pb), only a few of these have properties that make them useful in microstructure

49

electrodeposition. Nickel, copper and gold are the most popular ones. Copper is a better conductor than all metals except pure silver, and because of its merits in realizing high-quality, multilevel interconnections, its electrodeposition has been a hot topic in the ULSI industry. Gold excels not only in electrical resistivity, but also in chemical resistance. For microcoil fabrication, conductivity is of primary concern, which explains the dominance of copper and gold. In electroplating, arrangements have to be made for applying an external potential, passing current through the seed layers, as well as etching of the seed layers. The last requirement eliminates a lot of otherwise viable molding materials. Electroless plating can get around these problems, and may become a valid candidate for making metallic microstructures under some circumstances. Some experiments with copper electroless plating have been carried out by Bhansali and Sood101. They used Pd implantation to selectively seed a copper film on Si, and 1.7 µm thick copper microcoils were realized as a result. Electroless plating suffers from the following disadvantages: first, it is difficult to obtain a thick film because of the large stress in the film, second, a surface activation treatment such as Pd implantation is necessary when an electrical insulator is used as a substrate, the adhesion between the layer and the substrate is weak, and finally, the plating velocity is less controllable than electroplating. Based on the above discussion, a novel process to fabricate thick microcoils can be proposed, in which electroplating will be incorporated because it is relatively easy and inexpensive to implement, and silicon substrates will be used to form the

50

molds for electroplating that can stand chemical attack from electroplating solutions. Microcoils fabricated with this process will have larger parasitic capacitance than ones fabricated with polymer/polyimide molds. The resistivity of bulk copper is 1.67 µΩcm, and that of electroplated copper is slightly higher, between 1.94 µΩ-cm and 2.05 µΩ-cm102. As copper is diamagnetic, its permeability is only slightly less than that of vacuum, 4π × 10-7 H/m (or V·s/A·m), c.f. Table 2.4. According to Eq. 2.1, the skin depth δ of copper is approximately 71.2 µm at 1MHz, and 22.5 µm at 10 MHz. Our inductive link is projected to operate at frequencies no higher than a few MHz. The skin depth of silicon is more than 50 mm at 10 MHz. If the receiving coils are around 50 µm thick, their resistances can be reduced to a few ohms at low frequencies and do not increase significantly over the entire range of operating frequencies. As the proposed inductive link works in the low frequency range (less than 10 MHz), parasitic capacitance of the receiving coil is not expected to degrade the link performance noticeably, which will be verified by a comparison of link performance using coils with and without sidewalls. The design, fabrication and characterization of microcoils will be given in following chapters.

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CHAPTER 3

INLAID ELECTROPLATED MICROCOILS

3.1

Fabrication overview

Microelectromechanical systems (MEMS) is a technology of miniaturization that has been largely adopted from the integrated circuit (IC) industry to miniaturize systems including electrical, mechanical, optical, fluidic, etc. The downscaling of systems is accomplished through microfabrication technologies1, both conventional IC processes and materials: photolithography, thermal oxidation, dopant diffusion, ion implantation, CVD, evaporation, sputtering, wet etching, plasma etching, reactive-ion etching, silicon dioxide, silicon nitride, aluminum, etc.; and micromachining processes and materials, which include bulk micromachining, e.g. anisotropic wet etching of single-crystal silicon, deep reactive-ion etching (DRIE), HEXSIL, surface micromachining, LIGA2 and LIGA-like techniques (x-ray lithography, micromolding, electroplating); other non-lithographic precision microfabrication techniques, such as excimer laser micromachining, ion beam milling

3

, micro electro discharge

machining4,5, micro ultrasonic machining6, diamond milling, plasma beam machining, electron beam machining; innovative material deposition methods such as laser-

52

assisted chemical vapor deposition, micro stereo lithography

7

, localized

electrochemical deposition8, spin casting; and materials not traditionally used in IC manufacturing: low-stress LPCVD films, thick-film polymer and polyimide, electrodeposition photoresist, piezoelectric films such as PZT, magnetic films such as Ni, Fe, Co, high temperature materials such as SiC and ceramics, sheet glass, plastics such as PVC and PDMS, etc. The field of MEMS embraces enormous breadth and diversity, so it is impossible to present each process in detail here. Since our goal is to build an integrated coil of low resistance with a CMOS compatible process, electroplating-related processes emerge as strong candidates. There exist various procedures to obtain electroplated metal micro-structures, such as copper damascene and LIGA, as shown in Fig. 3.1 (a) and (b). A detailed discussion of the processes follows. Copper damascene is already adopted for interconnect fabrication by many IC manufacturers9, 10, 11. Figure 3.1 (a) briefly illustrates the damascene process: a copper seed layer is deposited over a pre-structured substrate, then the sample is immersed into a copper electroplating solution for plating. Surface topology leads to a nonuniform distribution of plating electric field.

As a result, copper tends to be

preferentially deposited at higher places and sharp corners, rather than into the trenches or vias where it is desired to be. In copper damascene, this problem is resolved by using additives, which are also preferentially deposited at places of strong electric field. The additives inhibit the growth of copper. As a result, copper grows faster in the trenches and vias than on the surface. This technique is called “super

53

filling” in copper damascene.

Since copper is also deposited on the surface, a

polishing step is required afterwards. Due to the finite selectivity of the super filling technique, the plating thickness of vias is limited to several micrometers, so as not to impose too great a task to polishing, and that thickness suffices for IC interconnects.

(a)

(b)

Fig. 3.1 Electroplating-related microfabrication processes: (a) copper damascene and (b) LIGA. (blue: silicon, orange: copper, grid: dielectrics)

54

Metal microstructures of large thicknesses are typically obtained through LIGA2 processes, either X-ray or UV LIGA, as shown in Fig. 1(b). A metal seed layer is deposited over a flat substrate, then a polymer or polyimide mold is formed above the seed layer. Presently, two kinds of materials, i.e. photoresists and polyimides, are widely used for electroplating molding as discussed in section 2.5. With these two materials, it is in no way trivial to form a mold that retains its form and adheres well to the substrate in the aggressive electrodeposition solution throughout the process. In the subsequent electroplating step, metal will be electrodeposited only where the seed layer is exposed to the plating solution. After electroplating, the mold is removed and the whole metal microstructure is immersed in the metal etchant to remove the seed layer. Note that the microstructure is not protected during the etching. Because of its height, it is impossible to implement photolithography steps at this stage, and the metal structure remains only due to its sheer volume. For this reason, LIGA is mainly used as a molding technique, and it is limited for integrating metal structures with other microdevices because of the lack of lithography method after electroplating. In addition, LIGA requires special lithography equipment, and X-ray LIGA causes ionradiation to microdevices, which is another great obstacle towards the integration of microstructures with microdevices. The above two processes cannot meet the criteria of our process, i.e. to increase metal thicknesses to several tens of micrometers and be IC compatible. Therefore, an “inlaid electroplating” procedure is developed in-house based on our available facilities. The process is schematically shown in Fig. 3.2. Silicon is to be

55

used as the molding material because of its mechanical strength and chemical stability. Hence, the molds will be etched into silicon substrates by either wet or dry anisotropic etching, which are already mature technologies (Fig. 3.2 (a)). Patterned electroplating is adopted here, i.e. the seed layer is patterned prior to electroplating. Since the copper seed layer is left only at the bottom of the molds (Fig. 3.2 (c)), copper grows from the trench bottom up. The copper structures can be over several tens of micrometers thick, limited only by the depth of the molds, which is similar to LIGA. Unlike damascene, the inlaid electroplating process may confine the copper within the mold by controlling the plating thickness (Fig. 3.2 (d)), so subsequent polishing is not mandatory if no front-side lithography is required afterwards.

Nevertheless, the

process can choose to overfill the trenches, let copper electroplated above the surface (Fig. 3.2 (e)), use a mechanical polishing step afterwards to planarize the surface, and potentially integrate metal structures with electronics (Fig. 3.2 (f)). Also, silicon can be selectively removed from some areas to realize stand-alone structures (Fig. 3.2 (g)), or to fine tune the electrical properties of the coil (parasitic capacitance).

56

Fig. 3.2 Inlaid electroplating process flow.

The inlaid electroplating process bears a resemblance to the HEXSIL process12, 13

developed at the University of California, Berkeley in that both processes adopt

deep trenches etched in silicon wafers as molds. However, HEXSIL is a template replication process for stand-alone polysilicon structures, (filling the trenches by depositing sacrificial oxide and polysilicon, etching the sacrificial layer and releasing the template-molded polysilicon) whereas our inlaid electroplating process is used to obtain metal microstructures. A schematic of the HEXSIL process is shown in Fig. 3.3. The next section will present more fabrication details on the inlaid electroplating process.

57

Fig. 3.3 HEXSIL process. (Adopted from Ref.[13])

58

3.2

Inlaid electroplating process

For inductive on-chip powering, an integrated coil is used to intercept electromagnetic energy. As a larger area enclosed by the receiving coil can improve the power transfer efficiency, the receiving coil is designed to encircle the devices it powers, which can reasonably cover an area of many square millimeters. Also to minimize coil resistance, copper is adopted as the metallization (its conductivity is second only to silver). Therefore, the receiving coil is designed as a 10- or 20- turn square spiral, 14 mm on a side, and the copper lines are 80 µm wide on a 100 µm pitch, as shown in 3.4. The substrates are ~575-µm-thick, 4-inch single-crystal silicon wafers, doped n-type with resistivity ~ 10 Ω⋅cm.

Fig. 3.4 Inlaid coil layout.

3.2.1 Thick photoresist molding One of the most important steps in an electroplating process is to build a reliable mold that can stand the aggressive electroplating solution throughout the process. In microelectronic electroplating, photoresists are commonly adopted as the molding material because of the readily available patterning techniques and

59

equipment. Therefore, thick photoresist was tried first to build a mold for our lowresistance microcoils. AZ 4620P from HOECHST was used, which can be coated to about 20 µm thick depending on the spin speed. It cannot provide as deep a mold as is desired, but the thinking is that the experiences with thick photoresist processing and thereby fabricated microcoils might shed light on future process design. Building the electroplating mold with AZ 4620P was unsuccessful, due to the lack of adhesion between the mold and substrate, as shown in Fig. 3.5. The sidewalls of the mold moved even when the pattern was blown dry. The thickness of the mold was only 5 µm at a spun-on rate of 4000 rpm. The poor adhesion is believed to be caused by the large lateral aspect ratio of the coil mold (14 mm long and 20 µm wide),

PR

PR

Fig. 3.5 Coil mold by AZ 4620P (5 µm thick).

60

since the reverse image of the coil mold, as shown in Fig. 3.6, does not exhibit any adhesion problems. Applying AZ 4620P thicker than 5 µm reveals other problems, such as cracking, as shown in Fig. 3.7. There could be a number of reasons for the cracks: stress built up during baking, or insufficient exposure. Prolonged exposure (more than 20 minutes) is impractical with our Cobilt contact aligner, as its light path is not highly collimated.

The effort on photoresist molding was thus concluded with those

problems unresolved.

Wafer surface

Wafer surface

PR

Fig. 3.6 Reverse image of coil mold by AZ 4620P.

61

Fig. 3.7 Cracks of AZ 4620P.

3.2.2

Silicon mold forming From the experiments with photoresist molds evolves the idea of silicon

molding: coil-shaped trenches etched into silicon substrates and used as electroplating molds later on. This process falls into the category of silicon bulk micromachining, which can be realized by either anisotropic wet etching or dry etching. Anisotropic wet etching of single crystal silicon is achieved by exploiting the selective etching of different crystal planes in single crystal silicon. The mold layouts have to be aligned to certain crystal orientations and compensation structures need to be incorporated for convex corners. There are a variety of chemicals available, such as alkaline aqueous solutions of KOH, NaOH, LiOH, CsOH, NH4OH, and quaternary ammonium hydroxides 14 .

Commonly used solutions are KOH, EDP (ethylene

62

diamine pyrocaterchol) and TMAH (tetramethyl ammonium hydroxide), which all preferentially etch (110) crystal planes to (111) in silicon, thus forming an inverse pyramid with well-defined {111} sidewalls (at angles of 54.74° to the surface) and a (100) bottom. A heated 33 % wt. KOH solution at 90 °C was used in our experiments, with an etch rate greater than one micron per minute and around 100:1 selectivity to the SiO2 mask. One major problem with anisotropic wet etching is the undercutting of convex corners due to the revelation of faster-etching planes at the corners, such as {411} planes15. Figures 3.8 (a) and (b) show the evolution of convex corners after 5 minutes and 20 minutes of etching. With 20 µm wide sidewall, the convex corners will be consumed by KOH in 10 minutes. As an aside, the sidewalls in Fig. 3.8 (b)

(a)

(b)

Fig. 3.8 The convex corners of silicon coil mold after (a) 5 minutes and (b) 20 minutes of KOH etching.

63

appear wider than in Fig. 3.8 (a) because the etched sidewalls are not vertical by KOH, and if the etching continues, the sidewalls will converge and limit the trench depth. Convex corners can be preserved by incorporating corner compensation structures which are added to the corners in the mask layout.

Commonly used

structures are square corner compensations, as shown in Fig. 3.9.

Using the

IntelliSuite™16, a processing simulator, KOH etching with the mask of Fig. 3.9 is simulated as shown in Fig. 3.10.

The simulated etching progress is similar to

experimental results for convex corners without compensation structures, and a 50 µm x 50 µm square is shown to protect the convex corners for about 20 minutes KOH etching.

Compensation structure

Fig. 3.9 Mask layout with corner compensation structures.

64

(a)

(b)

Fig. 3.10 Simulated KOH etching results by IntelliSuite™ after (a) 5 minutes and (b) 20 minutes etching.

Corner compensation requires a significant amount of space around the corner, making the design less compact. With KOH etching, the etch depth is limited by the dimensions of the open area. This feature combined with slanted sidewalls make it difficult to build an electroplating mold with sufficient cross-sectional area. Another drawback is the rough surface exposed by KOH etching, which worsens with etch depth. Therefore, wet etching was not chosen to build the silicon mold. In addition, the potassium ion (K+) is an extremely fast-diffusing alkali metal ion, detrimental to lifetime in MOS devices, and is thus incompatible with CMOS processing. Next, dry etching of the silicon molds was investigated, also known as deep reactive ion etching (DRIE) process. The molds were targeted to be 60 µm deep,

65

etched by an Alcatel A601E with the Bosch process (patented by Robert Bosch GmbH17). The Bosch process achieves high etching anisotropy by alternating etching and passivating processes. The Alcatel utilizes two RF power sources in the system: one generates and controls a high density plasma for high etch rates; the other controls the bias potential of the plasma relative to the wafer, i.e. the ion bombardment energy. A fluorinated gas (SF6) flows in the chamber first to etch the silicon. After a few seconds, SF6 is pumped out and C4F8 is pumped in. C4F8 forms a thin Teflon-like passivation layer on the wafer, including the bottoms and sidewalls of the previously etched holes. Then SF6 is pumped in again. The passivation at the bottoms is removed by ion-bombardment, and the fluorine attacks the silicon there. High aspect ratio structures are thus realized. Since the anisotropic etching of silicon does not depend on ion bombardment alone, the process has a high selectivity for photoresists and is relatively insensitive to the nature of the photoresists, even hard baking of photoresists is not required prior to etching. With our experiments, image reversal photoresist AZ 5214E about 2.5 µm thick was used in negative tone to mask the silicon wafers. No special photoresists or lithography techniques are required for patterning. There exists a large parameter space for the etching tool to obtain the desired silicon etch rate, selectivity to mask materials, uniformity, surface morphology, etc.18, 19, 20

The right recipe depends on the mask design, masking material, the requirements

on feature profiles, and so on. In our Alcatel A601E, the standard Bosch process is designed for a 4 inch Si-wafer with no more than 10% open area. The process flows

66

SF6 at 300 sccm for 7 seconds to etch silicon with ion assistance at 80 W, then switches to C4F8 at 130 sccm for 2 seconds for surface passivation. The plasma generator operates at 1800 W. For our mask, contact pads are put at the wafer edges to facilitate later electroplating, and “streets” providing electrical path to the coils are also incorporated into the layout, as shown in Fig. 3.4. Consequently, our pattern has approximately 38% open area with an unevenly distributed feature density. Because of this, several complications arise for the etching process: the loading effect (the dependence of local etch rate on the amount of etchable surface area), incomplete removal of passivation material which gives rise to micro-columns or “grass,” and reduced selectivity to the photoresist. Etching our pattern with the original recipe causes excessive polymer residue and a rough exposed surface. The surface roughness was measured to be as much as 7 µm. By reducing the flow rate of C4F8 (from 130 to 120 sccm), and increasing ion bombardment bias (from 80 W to 90 W), surface roughness, micromasking and grass formation are suppressed. Meanwhile, the selectivity to the photoresist is maintained by increasing the chamber pressure slightly. The surface roughness of the trench bottom is controlled within about 1 µm, as shown in Fig. 3.11. The surface roughness may be reduced further by lowering chamber pressure, to assist in the transport of reactants and products into and out of etched features. However, this leads to an increase in ion density, and thus reduced selectivity to the photoresist mask, which becomes insufficient for the trenches to reach the desired depth. Since the etching

67

selectivity to metals is almost infinite, an aluminum mask was also adopted for trench etching. The surface profile of trench bottom with Al mask is shown in Fig. 3.12. The surface roughness is within 200 Å. The only difference between etching recipes for Figs. 3.11 and 3.12 is the chamber pressure. The latter is lower.

Fig. 3.11 Surface profile of trench bottom by DRIE with photoresist mask.

Fig. 3.12 Surface profile of trench bottom by DRIE with aluminum mask.

A range of depth from 50 to 100 µm was realized for the silicon molds. Scanning electron micrographs of etched trenches are shown as Fig. 3.13 (a) and (b), in which the sidewalls were 20 µm wide. Fig. 3.13 (b) is a blow-up of the etched Si

68

sidewalls, showing the scallop structure on a submicron scale (~ 0.3 µm), which is produced by the two-step etching and passivation process.

(a)

(b)

Fig. 3.13 (a) Silicon trenches formed by deep reactive ion etching and (b) surface of the sidewalls. (Left: the trenches are 50 µm wide, right: the scallops are on 0.3 µm scale.)

3.2.3 Seed layer patterning After thermal growth of silicon dioxide for isolation, a 1-µm thick Cu/Cr seed layer was e-beam evaporated over the microstructures.

Since it is desirable for

electroplating to happen only at the trench bottom, the seed layer elsewhere was removed.

Lift-off cannot be used here because of non-conformal coating of

photoresists over 3-D microstructures. It is common knowledge that it should not be possible to plasma-etch copper because it does not form a volatile fluoride, chloride, etc. Therefore, the seed layer needs to be removed by wet-etching. The two most

69

common chemistries for wet etching copper are ferric chloride with some HCl and ammonium persulfate (APS). However, there are some obstacles when patterning the seed layer with wetetching. One problem is to completely protect the metallization at the bottom of the trenches with photoresists.

3-D topologies and centrifugal force when spinning

photoresists cause the photoresist to deplete at some sites, as shown in Fig. 3.14. In

Fig. 3.14 Photoresist coverage of trench bottom.

addition, the roughness of exposed silicon at the bottom of the trenches makes the photoresist coverage worse. The problem was resolved by using photoresist AZ 4620P again (for high viscosity) spun on at 2000 rpm. With this spin rate, AZ 4620P can be coated thick enough at all sites without obvious edge beads. The pattern was exposed by the Cobilt contact aligner for 5 minutes, with the same mask as the trenchetching, and developed with dilute AZ 400K:water (1:4). Other problems are the geometry-dependent etch rate of copper wet etching21. Smaller features tend to have higher etch rates, and the coil layout has uneven feature density. Also the adhesion between copper and photoresist is less than desirable22.

70

Consequently, the etching progress of copper needs to be closely monitored, and severe undercut can happen with prolonged etching. In addition, most copper wet etchants are developed for microelectronic applications. Therefore, much effort was devoted towards finding an optimal etchant with an etch rate that is fast enough to remove large area of copper and minimize etchant seeping under the photoresist, but not too fast to lose control. Three copper etchants, CE-100, -200, APS 100, from the Transene company, Inc. 23 were investigated at different concentrations for various thicknesses of copper and compared for their results. An example is given in Fig. 3.15 for etching 0.8 µm Cu with CE-100, as 1:1 CE-100 gives the least undercutting, which is indicated by the amount of brown color under the photoresist mask. The etching endpoint was determined visually when the copper in the big open area was etched away.

Undercut (a)

Cu under PR (b)

(c)

Fig. 3.15 Optimization of copper etching by various CE-100: DI water ratios. (a) 1:2, (b) 1:1 and (c) straight. (Red: Cu masked by photoresist, brown: exposed Cr.)

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After copper patterning, adhesion layer chromium still needs to be patterned, wet etching by Transene’s AC 1020. The photoresist was post-baked for 10 minutes before wet etching.

The chromium etching was facilitated by grounding the

metallization during the etching to eliminate any electrochemical reactions.

3.2.4 Copper electroplating Copper acid electroplating is employed in our process. The electroplating solution is composed of sulfuric acid mixed with copper sulfate and a leveling agent, polyethylene glycol (Copper Gleam PCM+ from LeaRonal, Inc.24 ). The bath was operated at room temperature under air agitation. The electroplating process is controlled using a current source, and the solution agitation is bubble-assisted. The wafer with patterned seed layer is electrically connected to a negative potential, referred to as the cathode, relative to a positive electrode consisting of the electroplated metal, referred to as the anode.

Both the cathode and anode are

immersed in the conductive plating solution containing cupric ions. Electroplating is an electrochemical reaction that happens under the influence of electric current. When sufficient bias is imposed over the anode and cathode, a current will flow from the anode to the cathode. At the cathode, Cu2+ is reduced to Cu. Cu 2 + + 2e − → Cumetallic .

Through the electroplating solution, the current is conducted by the flow of positive ions, Cu2+.

At the anode, an oxidation reaction occurs, Cumetallic → Cu 2 + + 2e − ,

balancing the current flow at the cathode and maintaining electrical neutrality in the

72

solution. All the cupric ions removed from the solution at the wafer cathode are replaced by dissolution from the solid copper anode. The main difficulty is achieving plating uniformity. By Faraday’s law of electrolysis, the amount of electrodeposition is proportional to electric charge passed, which scales with current density at the site. Due to the uneven distribution of electric fields, electroplating in microelectronics applications tends to lack uniformity. There is more material electroplated at sites closer to the wafer edge, and more at the outer part of a coil than at its inner part. Because patterned electroplating is adopted in our process and the electrical path to inside turns has to trace through all the coil lines, there is an electrical potential drop between the two coil ends arising from the resistance of the seed layer (a few hundred ohms). Consequently, the problem of plating uniformity is aggravated with our coil design.

Measures were taken to

improve plating uniformity, including depositing a thicker seed layer, lowering plating current, incorporating a current “thieving” ring 25 , and interspersing reverse pulses during plating, which serves to remove non-uniformities. Figures 3.16 (a) and (b) show an electroplated copper coil inspected in a scanning electron microscope (SEM). The rightmost bar is 100 µm in Fig. 3.16 (a), and 10 µm in Fig. 3.16 (b). The plating uniformity at a chip scale, as determined by surface profilometry, is controlled to within 7 microns between the innermost and outermost copper lines, corresponding to a coil length of over 500 mm. electroplated copper is reasonably flat and well contained within the sidewalls.

73

The

100 µm

(a)

10 µm

(b) Fig. 3.16 Scanning electron micrograph of an electroplated copper coil. (a) whole coil and (b) local uniformity.

74

As a comparison, Figs. 3.17 (a) and (b) show the topologies of electroplated copper at the outer turns and inner turns of a 20-turn coil, with the rightmost bar representing 10 µm.

Because it was plated at a relatively large current, ~ 2 A

compared with ~ 0.8 A in Fig. 3.16, and no reverse pulses were used, there is obvious difference in copper thickness.

10 µm

10 µm

(a)

(b)

Fig. 3.17 (a) Outer turns and (b) inner turns of a 20-turn Cu coil electroplated at 2 A and without reverse pulses.

As a summary for the inlaid electroplating process, large lateral aspect ratio molds can be realized by using silicon as molding material, which has good mechanical properties and is chemically stable. Electroplated copper is confined within the mold by growing copper only from the trench bottom up and controlling the plating thickness (as shown in Fig. 3.16 (b)). The plating uniformity is the weakness of the process, but can be overcome by pains-taking efforts to optimize the reverse-

75

pulse plating procedure. The metal thickness is limited only by trench depth, which by DRIE can easily go beyond 100 micrometers.

3.2.5 Mechanical polishing and Si removal The subsequent polishing is not mandatory if no front-side lithography is required afterwards, but enables the integration of metal structures with electronics. The inlaid electroplating process can include a polishing step after electroplating to produce a flat wafer surface. In our experiments, copper is overplated above the wafer and polished back to obtain a leveled surface. The polishing was done by lapping films on a rotating wheel. The chips were attached facing down onto a fixture which makes horizontal movement during polishing. To avoid chemical disposal associated with chemical slurries, lapping films of different grit sizes were used to obtain a fast polishing rate and smooth surface. Lapping films with grit size of a few microns quickly brought the copper close to the silicon surface, then finer films of 0.1 µm grit produced a smooth surface for succeeding lithography. A part of a finished copper coil is shown in Fig. 3.18, with its surface profile shown in Fig. 3.19. By surface profiling, an approximate 70 nm step is observed between the outermost turn and the silicon surface. The steps are less for inner turns as more copper is electroplated at outer turns. The surface roughness is well acceptable for photolithography. A hard-learned lesson here is that inlaid copper coils are not as strong as they appear. With too fast a speed of the rotating wheel for a high polishing rate, the

76

10 µm

Fig. 3.18 Scanning electron micrograph of plated coil after polishing. (rightmost bar: 10 µm)

Fig. 3.19 Surface profile of the polished coil.

copper lines were torn away from the substrate, as shown in Fig. 3.20.

It is

understandable when realizing that copper yields more easily and sooner than silicon, and long, thin silicon sidewalls cannot stand lateral grinding force.

77

Fig. 3.20 Copper coil damaged by high speed polishing.

The copper coils can be released from the silicon substrate by etching away unwanted silicon. At first, a KOH solution was tried to remove the sidewall, with results shown in Figs. 3.21 (a) and (b). As can be seen in Fig. 3.21 (a), slanted Si walls were formed against the copper lines, which are supposed to be {111} planes. Only at convex corners can silicon be removed from and under copper lines (Fig. 3.21. (b)), which are defined by {411} planes. It is not graphically shown here, but KOH etching cannot effectively remove silicon between copper lines, as the Si etch depth is limited to 14 µm by {111} planes.

78

100 µm

(a)

(b)

Fig. 3.21 KOH removal of silicon sidewalls (a) along copper lines and (b) under between the opening.

Therefore, silicon was removed by reactive ion etching using SF6. A released electroplated copper coil is shown in Fig. 3.22 with silicon sidewalls between copper

100 µm

Fig. 3.22 Electroplated coil after sidewall removal.

79

lines removed. It can also be seen from Fig. 3.22 that the copper lines are free of voids. Voids occur when the seed layer is defective or there is conducting materials on the sidewalls of molds, especially for vertical sidewalls. The integrity of copper lines indicates that the seed layer on the bottom of trenches is continuous, i.e. wellprotected during wet etching. Since the wafer surface is planarized, photolithography can be used to remove silicon substrate locally as shown in Fig. 3.23 (a). The remaining silicon substrate can serve to anchor the copper coil. The flakes in the figure are silicon dioxide film which is peeling off. The silicon dioxide film can be seen more clearly in Fig. 3.23 (b), in which the oxide film is intact around the copper structure. Also the silicon can be removed from under the copper to further reduce parasitic capacitance or for other purposes.

oxide

(a) (b) Fig. 3.23 (a) selective removal of silicon substrate and (b) undercutting of Cu line to form overhang structure.

80

Fig. 3.24 A section of copper line torn off the Si chip to test its adhesion.

The electroplated copper is of low stress and adheres well to silicon molds. When tearing copper lines off the silicon substrate to test its adhesion, part of the silicon was torn away with the copper, as shown in Fig. 3.24. A new fabrication procedure termed “inlaid electroplating” has been presented in this section, to electroplate metal structures of large dimensions within a silicon substrate.

With silicon as the molding material, many problems associated with

molding can be readily resolved. Inlaid electroplating possesses the potential for further integration, and can also fabricate stand-alone metal microstructures after silicon removal. The electrical properties of coils with and without sidewalls are investigated in the next section to determine their effects.

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3.3

Microcoil characteristics

The fabricated microcoils are characterized using a simplified equivalent circuit as shown in Fig. 3.25. An inductor (LS) and a resistor (RS) in series account for

Fig. 3.25 Equivalent circuit of an integrated coil.

coil self-inductance and DC resistance, and the capacitor (CS) in parallel accounts for capacitive coupling between the copper lines and the conductive substrate. Compared with the model in Fig. 2.4, the impact of the substrate is lumped as a capacitor shunting the coil and absorbed into Cs in Fig. 3.25. There are two reasons for the treatment: the substrate is floating, so conventional analysis of capacitance does not apply; and the inductive link operates only up to several megahertz, rendering energy dissipation in the 10 Ω·cm substrate negligible. Hence, the three-element model will be used for analysis of the integrated coils and inductive links in the dissertation. The inductance of a spiral integrated coil can be calculated using the following equation26: L = 10 − 7 ×

(OD + ID ) ⋅ (OD − ID )2 ×  ln OD + ID + 0.2235 OD − ID + 0.726  , p2

 

OD − ID

82

OD + ID

 

3.1

where L is in Henries, p is the coil pitch in meters, and OD and ID are the outer and inner diameters of the coil in meters, respectively. From Eq. 3.1, it can be seen that coil inductance increases with its area and turn number, which are functions of p, ID and OD.

Also, the coil inductance has no dependency on its thickness, as the

parameter does not appear in Eq. 3.1. This agrees with the experimental results by a number of researchers summarized in Sec. 2.3. With p=100 µm, OD=14 mm, ID=12 mm for 10-turn, or 10 mm for 20-turn coils, L is then calculated as 3.44 µH for 10turn and 9.81 µH for 20-turn coils. The calculated values will be compared with measurements. The coil resistance can be calculated using R = ρ

l , where S is the crossS

sectional area of the metal line. The copper resistivity is 1.67 µΩ-cm, and that of electroplated copper is slightly higher, between 1.94 µΩ-cm and 2.05 µΩ-cm27. Using 10-turn coils as an example, with an average side length of 13 mm and a crosssectional area of 1.2 µm x 80 µm for thin film coils and 54 µm x 80 µm for electroplated coils, their resistances were calculated to be 92.7 Ω for thin film coils and 2.47 Ω for electroplated coils. For reasons stated previously (floating substrate and low-frequency operation), the coil capacitance is not determined analytically. The impedances of microcoils are measured with an Agilent 4294A impedance analyzer over the frequency range from 40 Hz to 110 MHz. The fabricated coils have 10- or 20-turn of square spirals. The impedances of thin film coils are also presented here for comparison. Their fabrication process is given in Sec. 1.3. The 10-turn thin

83

film coils are 1.2 µm thick, and 20-turn coils are 0.8 µm thick. The impedance versus frequency characteristics were obtained for both thin-film and electroplated coils, with and without Si sidewalls, of 10 and 20-turn, as shown in Figs. 3.26 and 3.27. Two frequencies are important to the frequency characteristics of coil impedance: the resonant frequency f0, defined as the frequency at which the real part of the impedance

Imaginary impedance (Ω)

is maximum, and the zero-reactance frequency fz, defined as the frequency at which

1000 500

electroplated coil with sidewalls without sidewalls

0 -500 -1000 1k

Real impedance (Ω)

thin film coil

2500 2000

10k

100k

electroplated coil with sidewalls without sidewalls

1M

10M

100M

thin film coil

1500 1000 500 0 1k

10k

100k

1M

10M

100M

Frequency (Hz)

Fig. 3.26 Impedance versus frequency of 10-turn thin film and electroplated coils with and without sidewalls.

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the imaginary part of the impedance is zero. Knowledge of f0 and fz, or ω0 and ωz, can be used to determine the values of the model elements in Fig. 3.25.

Imaginary part (Ω)

1000

impedances of 20-turn coils

500 0 -500

1k

Real part (Ω)

2000 1500

10k

100k

1M

10M

electroplated coil with sidewall without sidewall

thin film coil

1k

1M

100M

1000 500 0 10k

100k

10M

100M

Frequency (Hz)

Fig. 3.27 Impedance versus frequency of 20-turn thin film and electroplated coils with and without sidewalls.

Because the total coil impedance of the equivalent circuit can be written as ZS =

(

R S + jω L S − R S C S −ω 2 L2S C S

(1 − ω

2

2

LS C S

85

) + (ωC 2

S RS )

2

),

3.2

the following two relationships are obtained between f0, fz and RS, LS and CS by setting the differentiation of the real part to zero and equating the imaginary part to zero as well: 2ω02 L2S CS − 2 LS + RS2CS = 0 ,

3.3

ωZ2 L2S CS − LS + RS2CS = 0 .

3.4

For the equivalent circuit in Fig. 3.25, RS is the coil DC impedance and can be measured easily; therefore LS and CS can be determined as: LS =

(

RS

,

3.5

). −ω )

3.6

2 ω02 − ωZ2

CS =

( (2ω

)

2 ω 02 − ω Z2 RS

2 0

2 Z

Equations 3.5 and 3.6 can be used to extract LS and CS. Finding f0 and fz and using Eqs. 3.5 and 3.6, the element values in Fig. 3.25 can be approximately determined. As an example, f0=9.5 MHz and fz=8.9 MHz for 10turn thin film coil. With RS measured as 95.5 ohm, LS and CS are calculated as LS=3.23 µH and CS=77.3 pF.

Using curve-fitting, the model elements can be

extracted and summarized in Table 3.1. The measured coil resistances agree with the calculated values. The slight difference may well be attributed to the simplification of the model and measurement error. Also the agreement of the resistance values implies that the electroplated copper is void-free.

86

TABLE 3.1 EXTRACTED ELECTRICAL PARAMETERS OF THIN FILM AND ELECTROPLATED COILS R ( Ω)

Coil type

L (µH)

C (pF)

10-turn

20-turn

10-turn

20-turn

10-turn

20-turn

Thin film

95.5

275.8

3.4

9.6

65.0

114.8

Plated w/ sidewalls

2.56

5.95

3.4

9.6

128.0

243.6

Plated w/o sidewalls

2.59

7.72

3.4

9.7

70.5

128.7

As expected, with increased thickness, the coil resistance goes down and its parasitic capacitance goes up. The metal thickness does not have an obvious influence on the coil inductance, as expected. Consequently, coil self-resonance occurs in close frequency proximity for thin film coils and electroplated coils without sidewalls, and at lower frequency for electroplated coils with sidewalls, as seen in both Figs. 3.26 and 3.27. The quality factors of microcoils are also measured and given in Fig. 3.28. The quality factors are almost identical at lower frequencies, following the curve of

ωLS

Rs

, as the example given in Fig. 3.28 for 10-turn coils. Probably related to coil

self-resonance, the quality factors of microcoils without sidewalls reach the maximum

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at a higher frequency than those of microcoils with sidewalls, and since Q follows

ωLS

Rs

, coils without sidewalls have higher maximum quality factors than those with

sidewalls. The maximum quality factors, Qmax, are 34.4 and 24.7 for 10-turn coils

40

30

10-turn coils with sidewalls without sidewalls 20-turn coils with sidewalls without sidewalls

Q

ωL/R for 10-turn coils 20

10

0 100k

1M

Frequency (Hz)

Fig. 3.28 Quality factor of fabricated microcoils.

without and with sidewalls, 13.5 and 11.4 for 20-turn coils without and with sidewalls, respectively. Typically it is hard for RF Si integrated coils to obtain Q higher than 10, but our coils are different from those RF inductors as our coils are of large dimensions, operate at relatively low frequencies for power delivery. Large size leads to a large inductance (µH range compared with nH for RF coils), and energy

88

dissipation in the Si substrate plays a minor role at low frequencies (