CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS

CHAPTER 7 BUILDING BLOCKS OF INTEGRATED‐CIRCUIT AMPLIFIERS Chapter Outline 7.1 IC Design Philosophy 7.2 The Basic Gain Cell 7.3 The Cascode Amplifier 7.4 IC Biasing 7.5 Current‐Mirror Circuits with Improved Performance

NTUEE Electronics – L.H. Lu

7‐1

7.1 IC Design Philosophy Integrated circuits More and more electronics circuits are integrated in a single chip  More complicated functions  Smaller size and lower cost  Suitable for mass‐production Implementation cost depends on device area rather than device count  Large/moderate‐value resistors should be avoided  Larger/moderate‐value capacitors should be avoided  Preferable to use transistors due to chip‐area consideration

Design philosophy The design philosophy for ICs is different from that of discrete‐component circuits  Realize as many of functions as possible by using transistors only  Rely on device matching or size ratios for circuit design  Active loads are typically used for amplifier designs


7‐2

7.2 The Basic Gain Cell The CS and CE amplifier with current‐source loads Active‐load CS amplifier:  Equivalent circuit Rin  

Avo   g m ro Ro  ro

 Intrinsic gain ID  2  n Cox (W / L)  I D VOV / 2 V V L ro  A  A ID ID gm 

A0 

2V  L V  2 nCoxWL VA  A  A VOV / 2 VOV ID

Intrinsic gain is only 20 to 40 V/V for a MOSFET in a modern short‐channel technology For a given technology: larger A0 as VOV decreases and L increases For a given transistor: A0 increases as VOV and ID decrease Gain levels off at very low currents as the MOSFET enters the subthreshold region operation where it becomes similar to a BJT with an exponential current‐voltage characteristics


7‐3

Active‐load CE amplifier:  Equivalent circuit Rin  r Avo   g m ro Ro  ro

 Intrinsic gain A0  g m ro 

I C VA VA   VT I C VT

Maximum gain obtainable in a CE amplifier (assuming an ideal dc current source) Technology‐determined parameter Independent of the transistor junction area and the bias current for a given fabrication process VA ranges from 5 to 35 V for modern IC fabrication process VA ranges from 100 to 130 V for high‐voltage process Intrinsic gain ranges from 200 to 5000 V/V


7‐4

Output resistance of the current‐source load The current source can be realized by using a PMOS in saturation  The output resistance is no longer infinite due to channel‐length modulation 1 W   p Cox   VDD  VG  | Vtp |2 2  L 2 |V | ro 2  A 2 I I

Voltage gain of the CS amplifier with a current‐source load Av 

vo   g m1 (ro1 || ro 2 ) vi

 The voltage gain is reduced due to the finite output resistance of the current‐source load  The gain is reduced by half if Q1 has the same Early voltage as Q2 does (ro1 = ro2)


7‐5

Increasing the gain of the basic cell The gain is proportional to the resistance at the output It can be effectively increased by raising the output resistance of the gain cell Adding a current buffer:  Passes the current but raises the resistance level  The only candidate is CG or CB amplifier  Placing CG (or CB) on top of the CS (or CE) amplifying transistor is called cascoding

Gain enhancement:  It is not sufficient to raise the output resistance of the amplifying transistor only  A current buffer is also needed to raise the output resistance of the current‐source load


7‐6

7.3 Cascode Amplifier The MOS cascode Circuit topology:  Putting a CG (Q2:cascode transistor) on top of CS (Q1:amplifying transistor)  The cascode transistor passes the small‐signal current gm1vi to the output node while raising the resistance level by a factor of K Small‐signal analysis  Transconductance Gm  g m1

io

gm2v1

v1

v1/ro2

gm1vx vx

v1/ro1

g m1v x  v1 / ro1  g m 2 v1  v1 / ro 2  0 io  g m 2 v1  v1 / ro 2  0


7‐7

 Output resistance Ro  ro1  ro 2  g m 2 ro 2 ro1  g m 2 ro 2 ro1 K  A02  g m 2 ro 2 gm2v1

ix g m 2 v1  v1 / ro1  (v x  v1 ) / ro 2 ix  g m 2 v1  (v x  v1 ) / ro 2

v1 (vx‐v1)/ro2 ix

Voltage gain of the cascode amplifier with an ideal current source Avo 

vo  Gm Ro   g m1ro1 g m 2 ro 2   A01 A02   A02 vi


7‐8

The cascode amplifier with a cascode current‐source load  The output resistance of the cascode current‐source load Ro  ro 3  ro 4  g m 3 ro 3ro 4  g m3 ro 3 ro 4

 Voltage gain of the amplifier Av 

vo   g m1 ( Ron || Rop ) vi

  g m1 ( g m 2 ro 2 )ro1 || ( g m 3ro 3 )ro 4   

1 2 A0 2


7‐9

Distribution of voltage gain in a cascode amplifier The cascode amplifier gain can be characterized as  Av1: voltage gain from vi to vo1  Av2: voltage gain from vo1 to vo Av  Av1 Av 2  Rin 2  

v gs 2 i

vo1 vo  vi vo1



1 RL  ro 2 RL   1  g m 2 ro 2 g m 2 ro 2 g m 2

Av1 

vo1   g m1 Rd 1   g m1 (ro1 || Rin 2 ) vi

Av 2 

Av Av1

v1 v1/RL

gm2vx

g m 2 v x  (v x  v1 ) / ro 2  v1 / RL ix  g m 2 v x  (v x  v1 ) / ro 2

ix vx

(vx‐v1)/ro2


7‐10

Summary table of gain distribution with small‐signal parameters gm and ro Av   g m ( g m ro2 || RL )

Av1   g m (ro || Rin 2 )

Av 2 

Av Av1

Output resistance of a source‐degenerated CS amplifier


7‐11

Double cascoding Even higher output resistance can be achieved in MOSFET circuits by double cascoding Requires higher supply voltage as one more CG transistor is stacked in the gain stage Double cascoding is required for the current‐source load to realize the advantage in voltage gain

The folded cascode Folded cascode utilizes a PMOS as the cascode transistor The dc current of Q2 is I2 and the current of Q1 is (I1 ‐ I2) The voltage limitation due to stacking of NMOS transistors can be alleviated Small‐signal operation is similar of NMOS cascode


7‐12

The BJT cascode Consists of a CE and a CB transistor  Equivalent circuit:  Input resistance: Rin  r 1

 Transconductance: Gm 

g m1 ( g m 2  ro21 )  g m1 ( g m 2  r21  ro11  ro21 )

io v1/r2

vx

gm2v1

v1

v1/ro2 v1/ro2 g m1v x  v1 / ro1  v1 / r 2  g m 2 v1  v1 / ro 2  0 io  g m 2 v1  v1 / ro 2  0

gm1vx

v1/ro1


7‐13

 Output resistance: Ro  ro 2  (ro1 || r 2 )  g m 2 ro 2 (ro1 || r 2 )  g m 2 ro 2 (ro1 || r 2 ) Ro

max

 g m 2 r 2 ro 2   2 ro 2

Double cascoding with a BJT would not be useful (Ro won’t be further raised by double cascoding) v1/r2

ix gm2v1 vx v1 (vx‐v1)/ro2

v1/ro1

 Open‐circuit voltage gain: Avo 

Similar to MOS with ro1||r2

vo  Gm Ro   g m1 ( g m 2 ro 2 )(ro1 || r 2 ) vi

For gm1 = gm2 = gm and ro1 = ro2 = ro Avo   g m ( g m ro )(ro || r ) | Avo |max   ( g m ro )  A0


7‐14

BJT cascode amplifier with a cascode current source

Output resistance of an emitter‐ degenerated CE amplifier


7‐15

7.4 IC Biasing Basic MOSFET current source MOSFET current mirror  Widely used for ICs with good device matching  Q1 and Q2 are identical and in saturation: I D1  I REF 

V V 1 W  k n   (VGS  Vtn ) 2  DD GS R 2  L 1

I O  I D 2  I REF

 Current gain or current transfer ratio: IO I REF



(W / L) 2 (W / L)1

Effect of VO on IO  Current mismatch due to channel‐length modulation IO 

 V V (W / L) 2 I REF 1  O GS (W / L)1 VA2 

  


7‐16

MOS current‐steering circuits Current sink: pulls a dc current from a circuit Current source: pushes a dc current into a circuit All transistors should be operated in saturation Current mismatch exists for a finite VA (channel‐length modulation)


7‐17

Basic BJT current mirror The case of infinite  :  Current is proportional to the area of EB junction IO I REF



I S 2 AE 2  I S 1 AE1

The case of finite  :  Q1 and Q2 identical: IO I REF



1 1

2



 Current transfer ratio m (with infinite output resistance): IO I REF

 1

m m 1



 Current transfer ration m (with finite output resistance): IO I REF

 1

 V  VBE m  1  O m 1  VA 2



  


7‐18

BJT current steering Provides current source and current sink by using BJT devices VCC  VEE  VEB1  VBE 2 R 1 I1  I 4 REF 1

I REF 

 pnp

I2 

I3 

I1 

1 1

5

 npn 2

1

4

I REF

 pnp 3

1

I REF

5

I REF

 npn


7‐19

7.5 Current‐Mirror Circuits with Improved Performance The constant‐current source Used both in biasing and as active load Performance improvement of current mirrors  The accuracy of the current transfer ratio of the current mirror  The output resistance of the current source

Cascode MOS current mirrors The output resistance is raised by a factor of gm3 ro3 (the intrinsic gain of the cascode transistor) The minimum voltage at the output of the current source is Vt + 2VOV (VOV for basic current source)


7‐20

A bipolar mirror with base‐current compensation Base‐current compensation by an additional transistor Q3 The current transfer ratio is much less dependent on  IO I REF

1

 1

2

 (   1)

1



1

2

2

Output resistance Ro  ro 2

The Wilson current mirror Improving the current transfer ratio and output resistance The current transfer ratio: IO I REF

 2    I C 1        1  1  2 1      2 2   2  1    1    2 1  1 2 I C 1  1      (   2)        1 


7‐21

ix

 Output resistance: Ro 

vx   3  r 1    1ro 3  e1   3 ro 3 ix  2 2 2 

Comparison with cascode current mirror  Reduced ‐dependence for the current transfer ratio  Output resistance is approximately reduced by half  Requires an additional VBE like the cascode mirror

3ix/2

ix/2

ix/2

(3/2+1)ix

vx

1/gm1

The Wilson MOS mirror Similar to the bipolar Wilson mirror  Output resistance: Ro  g m 3 ro 3ro 2 

1  g m 3 ro 3 ro 2 g m1

Modified circuit to avoid systematic current error resulting from the difference in VDS between Q1 and Q2


7‐22

The Widlar current source Allows the generation of a small constant current using relatively small resistors Advantageous in considerable savings in chip area for integrated circuits Circuit performance  Output current: I VBE1  VT ln REF  IS

  

I  VBE 2  VT ln O   IS  I VBE1  VBE 2  VT ln REF  IO

   I O RE 

 Output resistance: Ro  [1  g m3 ( RE || r )]ro


7‐23