Characterization and Modeling of NonLinear

Characterization and Modeling of Non-Linear Inelastic Behavior of Organic Packages at Component and System Levels Tieyu Zheng*, Min Tao, Patrick Nardi, Mitul Modi, Sandeep Sane, Ibrahim Bekar Intel Corporation 5000 W. Chandler Blvd, M/S CH5-157, Chandler, AZ 85226 Email*: [email protected] Abstract Organic substrates in electronic packaging are made of laminated dielectric and plated copper layers surrounding a fiber-reinforced glass core. Their constituent materials have typically been assumed to be linear elastic for simplicity in the microelectronic packaging analysis. However, the viscoelasticity of dielectric materials and the viscoplasticity of copper in the substrates impact the substrate behavior and in some cases must be considered. This paper presents a series of investigations on the non-linear time-dependent behavior of organic packages through experimentation and finite element analysis (FEA), including characterization and model validation of substrate core, modeling simplification and case study of packages during the package assembly process, and package substrate behavior in the system stack. 1. Introduction Organic substrates have been widely used as the carriers of silicon die in electronic packaging. Organic substrates have laminated structure with alternating dielectric and conductive layers (called “build-up layers”) surrounding a central fiberreinforced glass “core” layer (Figure 1a). Dielectric layers behave viscoelastically. Conductive layers, mainly made of copper, behave elastic-plastically and viscoplastically. The buildup dielectric and core layers contain intricate patterns of micro-vias and plated through holes (PTHs) vias, respectively (Figure 1b). The conductive layers contain networks of traces, pads, and etc for signal routing, power delivery and grounding (Figure 1c). To study the package assembly process or package-socket interaction, substrates have been modeled as linear elastic with moduli and coefficients of thermal expansion (CTE) derived from modeling [1,2] or experimental measurement [3,4]. It provides a good estimate on substrate warpage or deflection in many cases with good computation efficiency. However, as the response is limited to linear elastic behavior, it does not account for plastic or time-dependent behavior of the substrates. Increasing complexity in electronic packaging and reliability requirements for end-user conditions require more accurate characterization and modeling to predict the mechanical behavior of package during the assembly process or in the system stack under enabling load. This paper reviews a series of investigations of the packages using organic substrates after considering the nonlinear inelastic characteristics of related materials. The viscoelasticity of substrate core was characterized and implemented into a FEA material card. Results of three-pointbend tests on the actual core were compared to a FEA model using the viscoelastic material card to validate the models. Plasticity of copper was considered and the simplification of

978-1-4244-2231-9/08/$25.00 ©2008 IEEE

buildup layers containing both dielectric and copper is presented. Two cases of package assembly with lower stress and short heating duration were studied with the above modeling methodology. The package substrate response under high enabling load in long isothermal bake tests was monitored and the corresponding finite element analysis was performed with considerations of the viscoelasticity of the core and buildup dielectrics, and the viscoplasticity of the copper. Solder Resist

Conductive Layers

Core Buildup Dielectric

(a)

(b)

(c) Figure 1 Schematic of organic substrates: (a) laminated structure; (b) cross section showing the local structures; (c) layout of routings in the conductive layers.

753

2008 Electronic Components and Technology Conference

2. Characterization and Modeling of Substrate Materials The material properties of each layer in a substrate can be characterized or modeled independently. The properties can be homogeneous across each layer or inhomogeneous with consideration of the routing structure in each later for more accurate estimation. Then the substrates can be constructed by stacking up the layers as in Figure 1a with their designated elastic, plastic, viscoelastic and viscoplastic properties. The orthotropy is maintained from the nature of the lamina. 2.1 Substrate core The temperature and time dependent moduli of the substrate core material were measured by DMA dynamiccyclic test over a temperature range of 100 to 250ºC. Figure 2 shows a typical set of DMA test results. The curve clusters in Figure 2a represents the components of the complex moduli of the viscoelastic material as functions of the test temperatures: the storage modulus E’ (shown as the blue curves), the loss modulus E” (green curves) and the phase angle φ (red curves). The curves in the same cluster were results for different frequencies. The peak of the phase angle corresponds to the glass transition temperature of the substrate core material [5].

(a)

The master curves in Figure 2b can be generated by fitting Figure 2a to Williams-Landell-Ferry (WLF) relation with the shift factors [5] calculated as below: log aT = −

C1 (T − To ) , C 2 + (T − To )

(1)

where T0 is the reference temperature, C1 and C2 are the calibrated parameters. The storage modulus in Figure 2b and the characterized reference temperature and parameters can be used directly to construct a viscoelastic material deck with combined testing data in ABAQUS/Standard [6]. To validate the feasibility of using the viscoelastic material model generated by DMA in the mechanical modeling at high strain levels, three-point-bend relaxation tests were performed. The experiments were conducted on a conventional load frame with an environmental chamber at temperatures of 25°C, 150°C and 165°C. At each temperature, the sample was loaded in displacement control in 1 mm increments. At each displacement step, sample dwell time was 45 minutes.

Finite element modeling was conducted with respect to the loading conditions, with the material properties determined from DMA testing results as described earlier to capture the load relaxation. Figure 3 shows a comparison between modeling (dotted curves) and three-point-bend test (solid curves) results. About 5% deviation in load magnitude was observed in the 165°C sample, which could be attributed to specimen geometry. Overall, the load magnitudes and relaxation trends for modeling and test results are in good agreement. These results validate the modeling methodology. It can be observed In Figure 3 that the temperature effect on the core relaxation is more pronounced than the time effect for these test conditions. From 25 to 165°C, the sample load reduces by approximately 40%; while dwelling at 165°C for 45 minutes caused the material to be relaxed for only about 10%. This suggests that unless the package is subject to high loading (tensile or compressive strain > 0.2%), and/or high temperature (close or beyond its glass transition temperature), with a substantial time duration, the temperature dependant linear elastic material properties are adequate for most package mechanical simulation needs. 0

5000

10000

15000

20000

25000

30000

0

25c -test -0.5

165c - test 165c-model

-1

25c-model Load (N)

-1.5

(b) Figure 2 DMA measurement results of virgin core material: (a) storage modulus, loss modulus and phase angle in the temperature domain; (b) master curves of storage (red) and loss modulus (blue) in the frequency domain after WLF fitting with reference temperature of 165°C.

150 - test 150c -model

-2 -2.5 -3 -3.5 -4

Time (s)

Figure 3 Comparison of FEA model using viscoelastic material deck with relaxation of three-pointbend test

754


Figure 4 shows the comparison of experimental results with FEA using different types of elements. Mesh density was maintained constant across all three models with three layers in the thickness direction. The simulated load relaxation curve using 2nd order brick elements almost overlaps that using 1st order incompatible elements but the former takes 4 times longer to compute. When using continuum shell elements, only 13% of the time needed by 2nd order brick elements was required but the relaxation curve suffers larger errors. Thus, 1st order brick elements are recommended to look at the substrate core relaxation or creep.

Though copper creep or relaxation is not considered in most analysis due to lower stress level or short loading duration, it may be significant when the stress level is higher or the loading duration is long. It’s reported that the electroplated copper could exhibit creep behavior at the temperature of bake tests of packages. A time hardening creep law by fitting of NIST reported data was reported in literature [8] and employed in this paper to study the package substrate behavior under concentrated enabling load in computer systems in the bake test of long duration:

ε creep =

3.5

Normalized Load

3.0

C1 ⎛ C ⎞ σ C2 t C3 +1 exp⎜ − 4 ⎟ C3 + 1 ⎝ T ⎠

(3)

where the stress σ is in Pa, time t is in second, and temperature T is in °K. C1=3.1×10-13; C2=1.1; C3=-0.8; C4=140.

2.5 2.0 1.5 1.0 0.5 0.0 0

5000

10000

15000

20000

25000

30000

Time (s) 2nd Order Brick

1st Order Continuum Shell

1st Order Incompitable Brick

Exp.-1

Figure 4

Effects of using different types of elements

2.2 The buildup dielectric layers The polymeric dielectric material in the buildup layers does not have reinforced fibers as in the core so it should relax faster than the core layer. Since the thickness of the buildup layers is usually 5 to 10 times less than that of the core layer, creep or relaxation of buildup dielectric layers can be neglected in considering package deformation if there is no presence of high load at elevated temperature for a long duration, such as during the package assembly process. Only temperature dependant linear elastic properties were used to the buildup layers in the model for package assembly process study. In the situation of packages subject to high enabling load and long bake test as in the system, viscoelasticity of the buildup dielectric layers was considered in the FEA model. 2.3 The conductive layers Conductive layers are mainly constructed of electroplated copper embedded with dielectric material. A kinematic hardening material model was adopted for the electroplated copper layers with CTE of 16.5 ppm/°C. The volume fraction of dielectric material in the conductive layers needs to be taken into account in order to obtain a more realistic estimation of the in-plane properties of the conductive layers. With substrate homogenization tools, the copper density at each layer can be calculated on the basis of the substrate design [4]. The in-plane effective elastic modulus and CTE can further be calculated as the volumetric average of copper and the buildup dielectric [7]:

2.4 Simplified buildup layers One disadvantage of this method is that it could be computationally expensive because the properties of each layer need to be assigned separately therefore each layer has to be meshed separated as well. For complex substrate designs, the total layer count from front side to the back side could be more than 30, which drives the total degree of freedoms in the FEA model at least hundreds of times higher than the case where a homogeneous property is assigned to the entire substrate and only a few layers of mesh are needed along the thickness direction. A numerical simplification based on the properties of representative volume elements was conducted to derive the effective buildup layer properties. The representative volume elements consisting of the desired layer stack-ups with designated properties were subject to uniaxial loading along the in-plane and out-of-plane directions of the layers. Figure 5a shows the calculated properties of the effective representative volume elements of the buildup layers from its constituting layers at the room temperature. The temperature dependant hardening properties can be obtained in the similar way conducted at different temperatures with material properties from the lamina at the corresponding temperatures (Figure 5b). Figure 5c shows that a 16-layer stack-up of solder resist, copper and dielectric materials can be simplified and represented with 2 layers of elements. However, this method has not been extended to create the effective creep law of the effective layers yet.

E = Σ ( v i E i ) / Σ (v i )

α = Σ(α i vi Ei ) / Σ( Ei vi )

(2)

755


3.1 Predicting BGA package dynamic warpage Understanding the package warpage behavior at not only room temperature but also solder ball reflow temperature (230~250°C for lead-free solders) becomes more and more important to the success of surface mounting (SMT). Due to lack of knowledge in the inelastic material properties of the substrate at high temperature for modeling input, currently shadow moiré measurement of package dynamic warpage from the room temperature to the reflow temperature is highly relied upon in industry for predicting and validating the SMT capability of BGA packages [9]. With characterization of substrate core viscoelasticity and incorporation of buildup layer plasticity in the current study, more accurate FEA prediction of package dynamic warpage upon temperature change became feasible. The dynamic warpage of a bare die BGA package with the size of 40×40mm and die-to-package aspect ratio of 0.4 was modeled with 2 sets of substrate properties: (1) viscoelasticity in core layer and kinematic hardening in copper layers; (2) homogeneous linear elasticity based on laminate theory in the entire substrate. The results were then compared to the average of shadow moiré measurement results on 10 packages. Figure 6 showed the shapes of warped package at 25°C and 230°C predicted by modeling method (1) and Figure 7 shows the comparison of package peak-to-valley warpage between the modeling results and experimental measurement results. Using material model (1) with nonlinear inelastic properties in the substrate could achieve prediction accuracy of 5%; while using material model (2) with homogeneous linear elasticity in the substrate overpredicted the dynamic warpage by 17%.

2000

True Stress -s1 (M Pa)

1800

BU-x-25c-se

1600

Cu-25c-se

1400

ABF-25c-se

1200

SR-25c-se

1000 800 600 400 200 0 0

0.01

0.02

0.03

0.04

True Strain -e1

(a)

True Stress -s1 (M Pa)

1600 1400

x-25c-se

1200

x-150c-se x-125c-se

1000

x-250c-se

800 600 400 200 0 0

0.01

0.02

0.03

Die center

0.04

Die center

True Strain -e1

(b)

(a) (b) Figure 6 Package warpage shapes at: (a) room temperature after assembly; (b) reflow temperature for surface mounting.

(c) Figure 5 Effective representations of the properties of multiple buildup layers: (a) effective build-up layer modulus calculated from constituting layers at room temperature; (b) temperature dependant effective buildup layer modulus; (c) simplification of buildup layers in finite element analysis. 3. Results and Discussions Two package assembly processes were studied in this paper to show the effects of considering the viscoelasticity of the substrate core and the plasticity of the conductive layer. One case of packages in systems under highly concentrated enabling load and long bake test was studied to show the need to include the time-dependent material properties in the FEA model in order to reflect the behavior nature better.

1.4 1.2 1 0.8 0.6 0.4 0.2 0

1

Model with Homogeneous Linear Elasticity

Normalized Warpage Change During Reflow

core Plated

Model with Core Viscoelasticity

A

Measurement with Shadow Morie

Effective Buildup layer

Sol der

Figure 7 Comparison of package dynamic warpage during reflow between shadow moiré measurement and FEA predictions. Adopting substrate nonlinear inelastic properties improved FEA prediction accuracy to be within 5% from the measurement

756


entire test period. Figure 10 shows the schematic of the test fixture which represents the typical system stack of LGA packages with concentrated load applied on the steps of the integrated heat spreaders of the packages. The residual package warpage was measured after disassembling the package from the fixture at each test readout and monitored throughout the test. After measuring the residual warpage at each readout the package was re-assembled into the test fixture and the bake test was continued toward the next readout. FEA was employed to model the response of the package loaded in the test fixture during the bake test. The substrate was modeled as a laminated composite with homogeneous layers of which the core is viscoelastic. Because the buildup layers experience very high strain due to the locally concentrated load and the test during is several hundred hours, it was suspected that the viscoelasticity of the buildup dielectric and viscoelasticity of the copper could also contribute to the substrate behavior. The substrate was assumed to be flat at the beginning of analysis and the effects of residual stresses during assembly were not considered. 1st order incompatible brick elements were employed for the substrate core and the buildup dielectric layers. 1st order reduced-integration brick elements were employed for the conductive layers which are assumed to be 100% copper so that the empirical copper creep law can be applied. Perfect bounding between neighboring layers was assumed and no structural damage during bake was considered. Concentrated loading areas

Post Epoxy - Incoming (um)

3 2.5

Post IHS-INC, w/ Clip Force (um)

1. Processor installation

Post IHS-INC, Clip Force Removed

3. Closed

2 1.5 1 0.5 0

ar el as Li ti c ne su ar bs el tr as at ti c e, 0l su bf bs tr Vi at sc e, o 8l su bf bs Vi tr at sc e, o 0l su bf bs tr at Te e st ,8 da lb f ta ,8 lb fC F

Flatness Normalized to Measured EOL Li ne Flatness

3.2 Capturing clip force effect on package warpage Even though mechanical modeling has been applied in capturing bare die warpage after assembly with certain success, linear elastic material model for the substrate is not sufficient to capture the process conditions associated with assembling the packages with integrated heat spreaders. Accounting for viscoelasticity of the substrate core and plasticity of build-up conductive layers, the package warpage associated with the curing temperature and the applied clip force can be better represented. Figure 8 compares the modeling results of different substrate material properties with the testing data. The linear elastic substrate properties were measured using a tensile test on cut parts of the substrate. The nonlinear inelastic substrate model was constructed using the method described in part 2 of the paper. With a linear elasticity assumption of the substrate, the effect of the clip force cannot be captured as seen in the first and second sets of columns in Figure 8. With the viscoelasticity in core and plasticity in copper layers, the clip force effect can be captured as shown by column sets 3 and 4 in Figure 8. After the clip force is removed, the package flatness increases slightly due to the fact that no strong plasticity was built in the copper layers with the thermal and mechanical conditions involved in assembly process. Overall, comparing to the testing data collected on the same package, the linear elastic material model over-predicts the warpage after assembly by 15%, while using the nonlinear inelastic material model reduces the error of the FEA prediction to 3%.

Figure 9

LGA775 Socket Socket

Figure 8 Comparison of modeling results with different substrate material properties versus testing data on a package with integrated heat spreader

Package Motherboard

Figure 10 Schematic setup to simulate the concentrated load on package in the bake tests

3.3 Analysis of the Package in the System An enabling force is required to engage a LGA (Land Grid Array) package with its socket in order to maintain electrical contact. Packages are typically loaded at two small areas by the loading mechanism, such as the LGA775 socket that is enabled by a DSL (direct socket loading) mechanism (Figure 9) [10]. This kind of enabling design results in concentrated load on the package substrates. A bake test at 125°C was conducted with a test fixture which had applied a constant load onto the package over the

Sensitivity study was performed to investigate the contributions from three substrate layer materials using the package residual warpage at the first readout (Figure 11). When the substrate core and buildup dielectrics are linear elastic and the conductive layers are elastic-plastic, the simulated residual warpage was only half of the measured value. When the viscoelasticity of the substrate core and/or the buildup dielectrics was considered, the simulated residual warpage was improved with equal contribution from the substrate core and the buildup dielectrics. If the

757


Linear Elastic

Relaxation Relaxation Relaxation Experiment of Core of Core of Core Dielectric Dielectric Dielectric, and Buildup Buildup Dielectric Dielectric and Copper

1.0 0.8 0.6 0.4 0.2 0.0 1

2

3

4

5

Figure 13 Package creep warpage under enabling load and after unloading in the bake test

0.5

0.0 4

Bake Readout FEA Simulation

further

Package Creep Warpage under Enabling Load

1.0

3

needs

Package Residual Creep Warpage

1.5

2

also

Bake Test Readout

2.0

1

sockets

1.2

0

2.5

0

and

1.4

1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0

Figure 11 Contribution of time-dependent effects of substrate core, buildup dielectric and conductive layers to package residual warpage after the package being baked

Normalized Package Residual Warpage

between packages investigation.

Normalized Package Creep Warpage

Normalized Package Residual Warpage

viscoplasticity of the copper is considered further, the simulation overestimates the residual warpage at the first readout with stronger effects than the viscoelasticity of substrate core and the buildup dielectrics but still lower estimates the residual warpage at later readout

Experiment

Figure 12 Comparison of measured residual warpage of package with simulated result with all time-dependent effects of the substrates considered in the bake test Figure 13 shows that the residual creep warpage almost doubles the creep warpage under enabling load, indicating the creep warpage under enabling load could be estimated from the measured residual creep warpage. It is also interesting that the package creep warpage at the loading condition could be less severe than that after unloading. The FEA does not match the experiment very well. There must be other factors impacting the package creep or relaxation behavior in the system. The analysis results are sensitive to the time-dependent material properties so it is critical to characterize them accurately, especially on the viscoelasticity of the buildup dielectric and the viscoplasticity of the conductive layers. The time-dependent interaction

4. Summary and Conclusions The non-linear inelastic behaviors of organic package during assembly process or under enabling load in the system were studied in the paper. The viscoelastic property of substrate core was measured with DMA and the FEA modeling methodology of the core was validated in three-point-bend test with good agreement. The substrate core showed higher temperature dependency but less time dependency, and the relaxation was also more obvious at higher load. Therefore incorporating the non-linear inelastic substrate material properties is more meaningful when high load or high temperature presents in the package assembling process or at the use condition of the package in the system. Comparing modeling the substrate core to be linear elastic, considering viscoelasticity of substrate core reduced the model prediction error from 17% to 5% of the measured values when studying the package dynamic warpage during reflow; incorporating the non-linear inelastic substrate properties reduced the model prediction error from 15% to 3% of the measured values which studying the clip force effect on package. At the system level, more pronounced time-dependent deformation behavior of the package was observed in the bake tests. FEA employing the viscoelasticity of substrate core and/or buildup dielectric, as well as the viscoplasticity of conductive layers of the substrate, improves the modeling accuracy. Contribution of viscoelasticity of the substrate core is similar to that of the buildup dielectric, while the viscoplasticity of the conductive layer may contribute more. In general, current model method lower estimated the residual warpage of the package in the bake tests. More material characterization and analysis study are needed to improve the modeling accuracy.

758


Acknowledgments The authors want to thank Yi He for providing support in DMA measurements. The authors acknowledge Jorge Sanchez and Frank Prieto for providing shadow morie measurements on package dynamic warpage and 3-point bend relaxation tests. References [1] Hutapea P, Grenestedt JL, Modi M, et al., “Prediction of microelectronic substrate warpage using homogenized finite element models”, Microelectronic Eengineering, 83 ( 3) (2006), pp 557-569 [2] Modi M., Kulkarni D., Bao A., Bekar I., Cho S., "Analytical homogenization for microelectronic substrates," Proceedings of the ASME International Mechanical Engineering Congress and Exposition 2007, (2007), Seattle, WA [3] Zhang X., Tee T. Y., “Advanced warpage prediction methodology for matrix stacked die BGA during assembly processes”, 54th Electronic Components and Technology Conference Proceedings, Vol., (2004), pp 1593-600 [4] Zheng T., Du Z., “User direct cyclic and sub-modeling approach to analyze solder joint fatigue relaibility”, Proceedings of the ASME International Mechanical Engineering Congress and Exposition 2008 – 42366, (2007), Seattle, WA [5] Ferry J. D. , Viscoelastic properties of polymers, John Wiley & Son (New York, 1990) [6] ABAQUS/Standard User Manual 6.6/6.7 (2007) [7] Christensen R. M., Mechanics of composite materials, Dover (New York, 2005) [8] Titus P, Salvetti M, “Creep effects in the toroidal field coils of the fire and other burning plasma tokamaks”, Proceedings of Embedded Topical in ANS Winter Meeting , Nov., (2002), Washington DC [9] Mello M. C., Raiser G. F., Mahajan R., Intel Assembly & Test Technology Journal, Vol 1 (1998), Process section, pp 1-20 [10] Pandey V., Subramanian S., Rangaraj S., Byquist T., Zheng T., “Mechanical design and analysis of land grid array (LGA) sockets”, Proceedings of InterPACK’05, IPACK2005–73360, July, (2005), San Francisco, CA, USA

759
