Depletion in MOS Structures. B. Riccb, Senior Member, IEEE, R. Versari, and D. Esseni. Abstract-This paper presents a new technique to characterize.
IEEE ELECTRON DEVICE LETTERS, VOL. 17, NO. 3, MARCH 1996
103
Characterization of Polysilicon-Gate Depletion in MOS Structures B. Riccb, Senior Member, IEEE, R. Versari, and D. Esseni
Abstract-This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented.
I. INTRODUCTION
P
RIMARILY because of insufficient dopant activation due to low-thermal budget processing [ 11, in non-degenerate polysilicon gates of MOS transistors biased into conduction, the finite capacitance C p associated with the depletion layer facing the channel makes the gate-to-source capacitance ( C G S )(hence the transconductance) to decrease and modifies the body effect. Consequently, a technique to extract the electrically active doping concentration in the polysilicon gate ( N p ) is required in order to: a) monitor the technology; b) account for gate depletion in physically-based compact models [2]-[4]. Assuming the gate to be uniformly doped near the poly/oxide interface, C p can be easily expressed in terms of N p , thus the extraction of either of these parameters is essentially equivalent for device characterization. Naturally, Cp could be easily deducted from CGS if the oxide component (CA,,~= Cox. A, where A is the gate area and Cox = c o x / t o z ) was known [5]. However, cannot be simply measured from the gate-to-substratecapacitance (CGB) at large negative VGS bias, as suggested in [6], since nonnegligible effects requiring suitable modeling prevent CGB from saturating for all VGs of practical interest (as clearly indicated also by the experimental results of this work to be shown later). Other methods proposed to determine N p are also unsatisfactory: SIMS technique is destructive and unable to detect only active impurities [3]; the application of a simple Maximum-Minimum Capacitance Method requires the knowledge of (51; the fitting of experimental data by means of numerical simulation critically depends on inherently inaccurate technological information [3]. In such a context, this paper improves the state of the art by proposing a new characterization method to extract Cp and CA,, from CGS measured with the transistor biased in the inversion region of real interest. The application of such a technique to n-channel MOSFET' s realized with convenManuscript received August 10, 1995; revised November 7, 1995. The authors are with the Department of Electronics, University of Bologna, Bologna 40136, Italy. Publisher Item Identifier S 0741-3106(96)01963-5.
tional 0.7 pm CMOS technology is illustrated as a significant example. 11. THE METHOD Let us make VDS= 0, so that CGS = CGD,and assume: 1) uniformly doped polysilicon; 2 ) complete depletion of the gate surface toward the channel; 3) CCS CGD= 2 c G S = [Cs' (CAox)-']-' (i.e. negligible contribution to the total capacitance of either inverted or accumulated layer at the substrate-oxide interface). From points 1 and 2, then it is
+
+
where, 10 denotes the depletion layer width, and the (absolute value of the) total charge IQ01 on the gate electrode, is given by
I&D~
lFB VG S
=
( ~ C G-I-SCGB)dV.
(2)
From (I), since, by definition s d&inv/dV& and, under the conditions of interest for this work, 2 C ~ sFZ dQD/dVGs, it is (3)
(4)
Thus, measuring CGS and calculating the 1.h.s. of (9, a constant value should be obtained in the region where assumptions 1, 2, and 3 made above hold true and nonnegligible polysilicon depletion makes CGS to decrease with VGS:from such a constant value, N p can be easily extracted (while, as shown in the next section, outside the region of validity of the approach of this work, (5) provides erroneous values of N p , higher than the correct ones). Subsequently, measuring also CGB and determining VFB, for instance with the method of [7], Q D can be calculated
0741-3106/96$05.00 0 1996 IEEE
IEEE ELECTRON DEVICE LETTERS, VOL. 17, NO 3, MARCH 1996
104
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2
3
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Fig. 1. Values of N p extracted with the method of this work from the simulated capacitance characteristics of n+-oxide-n++ structures. The dashed lines represent the corresponding nominal doping values. For voltages below ~3 V the analytical approach of this work fails because assumption at point 3 does not hold, while the sharp increase for VGS> 5.5 V in the lower curve is due to the onset of strong inversion at the gate-oxide interface.
r-
Fig. 3. Values of N p extracted from simulated transistor characteristics. Open triangles represent the results obtained by eliminating the effects of the as can be (substrate) inversion-layer capacitance in the case N p = 3 x seen, with ths correction the extracted doping is essentially indistinguishable from the nominal value. For voltages below ~4 V the analytical approach of this work fails because assumption at point 3 does not hold, while the sharp increase for VGS> 5.7 V in the lower curve is due to the onset of strong inversion at the gate-oxide interface.
15
5 1
1
0
-7
i
METAL GATE\ N,=l e+l 9cm9 T, : N,=2e+l 9cmB F NP=3e+19crn"
-5
-3
-1
1
3
5
-
NP=3e+l9cm
K
7
0 5.0 Fig. 2. Simulated characteristics of transistors, with L = 4 p m and to, = 10 nm. The dashed-dotted line is used to indicate the gate-to-substrate capacitance (essentially independent of gate doping), solid lines are used for 2CG.5. The values obtained from calculated 2cGs by eliminating the effects of polysilicon depletion are essentially coincident with the corresponding capacitance of a metal-gate transistor with the same substrate (dashed line).
from (2). Finally, Cp can be computed from (1) and CA,, easily worked out as [(2CGS)-' - ~ ~ ' 1 - l . 111. RESULTSAND DISCUSSION
The procedure outlined in the previous section has been validated by means of extensive 2-D numerical simulations. First, with n+-oxide-n++ capacitors (featuring to, = 10 nm), the N p 's are practically indistinguishable from nominal values (Fig. 1). The calculated net capacitance (CGB-' - C;-')-' is also practically the same as for an equivalent metal-gate capacitor, and slightly different from C A ~because ~ , of the finite contribution of the substrate accumulation layer. Similar results are obtained from the simulation of nchannel MOSFET's (Fig. 2).
7.5 ,T,
10.0
12.5
[nml
Fig. 4. Accuracy of Np values extracted from simulated transistors. The per cent errors is a function of oxide thickness and doping concentrations.
Fig. 3 shows that the Np's calculated for the case of transistors are in good agreement with nominal values (within 73.5%). In particular, the curve with open triangles obtained by applying the method of this paper to the transistor capacitance after eliminating the inversion-layer contribution (extracted from the simulation of a metal-gate structure with the same doping profiles and the same to,) provides a value of N p essentially coincident with the nominal one. Fig. 4 shows the calculated dependence of the error in the extracted Np' s due to neglecting the inversion-layer capacitance C,,, on relevant technological parameters (the dependence on substrate doping has been found to be practically negligible). Assuming C,,, M Qlnv/(2Vth), where Vth denotes the thermal voltage, this error can be roughly estimated to be in the order of [100(2Vth)/(Vcs - V T ) ]in , substantial agreement with the results given by numerical simulations.
RICCO et ai.:CHARACTERIZATION OF POLYSILICON-GATE DEPLETION IN MOS STRUCTURES
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Fig. 5. Results obtained with n+-oxide-p Si capacitors. The solid line represents measured data; filled symbols are used for the net capacitance, obtained by subtracting the effects of polysilicon depletion.
*-----a
2.0 1.5
1
0 1.0
t
u
0.51, 0.0
Fig. 7. Experimental results obtained with transistors and with capacitors 5 the analytical approach realized on the same chip. For voltages below ~ 4 . V of this work fails because assumption at point 3 does not hold, while for VGS > 7 V the sharp increase in the lower curve is due to the onset of strong inversion at the gate-oxide interface.
calculated
lx, ,I \
I
,
-8 -6 -4 -2 0
I
2
4
,
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Fig.
6. Results obtained with n-channel transistors, featuring L = 1pm, W = 700 pm. The solid curves represent measured CGB and (CGS C G D ) (this latter measured by shortening source and drain to the Low Terminal of the CV meter HP 4280). Filled symbols are used for the net capacitance, obtained from experimental data subtracting the effects of polysilicon depletion.
+
As for experiments, devices fabricated with state-of-theart 0.5 pm CMOS technology, featuring to, = 11 nm have been used. The gate polysilicon, 150 nm in thickness, has been doped by implanting P ions per cm2 at an energy of 30 keV. Fig. 5 shows the results obtained from (200 x 800 pm2) capacitors with p-type substrate and an n+ implant ring (essentially a large area nMOSFET structure with shorted source and drain). Fig. 6, instead, illustrates the case of (conventional) transistors. Both capacitors and transistors belong to the same wafer and Fig. 7 shows that the values of N p extracted from the two types of devices are very similar. IV. CONCLUSIONS A novel method has been presented to characterize polysilicon depletion in MOS structures. In particular, using measured
C-V characteristics (including the capacitance first derivative with respect to applied voltage), such a method allows to determine the doping concentration of the polysilicon gate and the capacitance associated with the depletion layer within the gate. The method has been satisfactorily validated by means of 2-D numerical simulation, and results obtained with state-ofthe-art CMOS devices are presented as significant example of application.
ACKNOWLEDGMENT The authors are grateful to SGS-Thomson Microelectronics, Agrate Brianza, Milan, Italy, for providing the devices used for the experiments of this work.
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