Class EF2 Inverters for Wireless Power Transfer Applications Samer Aldhaher, George Kkelis, David C. Yates and Paul D. Mitcheson Department of Electrical and Electronic Engineering, Imperial College London, UK email:
[email protected]
Abstract—Class EF inverters are hybrid inverters that combine the improved switch voltage and current waveforms of Class F and Class F-1 inverters with the efficient switching of Class E inverters. As a result, their switch voltage and current stresses are reduced, and their efficiency, output power and poweroutput capability can be higher than the Class E inverter. These improved features of Class EF inverters over Class E inverters can be beneficial in a wireless power transfer (WPT) via magnetic induction application. This paper demonstrates the application of a Class EF inverter operating at a 6.78 MHz for a 25 W WPT system. A sixth-order piecewise-linear state space model is presented to analyse the inverter and to derive values of its components to achieve optimum switching operation. Experimental results are provided to confirm validity of the state-space model and the design of the inverter and a DC-DC efficiency of 87 % was achieved. Index Terms—Wireless Power Transfer, Class EF inverters, high frequency inverters.
I. I NTRODUCTION Resonant topologies are seen to be the most suitable design choice for a multi-megahertz primary coil driver in WPT system due to their reduced switching losses. One particular topology that has recently been of increasing interest is the Class E inverter. The Class E inverter is capable of operating efficiently at switching frequencies above 1 MHz due to its operation at zero-voltage switching (ZVS) and zero-derivative voltage switching (ZDS) conditions, can deliver more power than other classes for a certain input voltage and is simple to construct because of its low component-count. Class E inverters are well documented in the literature [1], [2] and have been widely used in WPT applications [3]–[5]. It has been reported in [6]–[9] that the efficiency of the Class E inverter can be improved and its voltage or current stresses can be reduced by adding a resonant network either in parallel or series to its load network. The method of adding resonant networks to the load network is used in Class F and Class F-1 inverters, and by applying it to the Class E inverter results in a hybrid inverter which has been referred to as the Class EFn or Class E/Fn inverter. The subscript n refers to the ratio of the resonant frequency of the added resonant network to the switching frequency of the inverter and is an integer number greater or equal than 2. The ‘EFn ’ term is used if n is an even integer and the ‘E/Fn ’ term is used if n is an odd integer. The added resonant network or networks could be in the form of a series LC lumped network that is connected c 978-1-4673-7447-7/15/$31.00 2015 IEEE
in parallel with the load network as shown in [7], [8], [10], [11], or a parallel LC lumped network that is connected in series with the load network as shown in [6], or a combination of both series and parallel LC lumped networks that are connected in series and in parallel with the load network as shown in [9]. A λ/4 transmission line inserted between the supply source and the inverter can also be used as shown in [12], [13]. The concept of combining Class E and Class F or Class F-1 inverters was introduced by Kee in 2002 [9]. In his paper, Kee presented an overview of the Class E/F inverter and a generalised frequency domain based analysis method to determine the voltage and current waveforms for any combination of added lumped LC resonant networks. A subsequent publication by Grebennikov [7] presented closed-form analytical equations for the Class EF and Class E/F inverters with an added series LC lumped network in parallel with the load network as shown in Fig. 1. Design equations were derived specifically for the Class E/F3 inverter based on the assumption that the added series LC resonant network has a large energy storage and the duty cycle is at 50 %. Another publication by Kaczmarczyk [8] presented a piecewise-linear state-space model for the Class EF2 and Class E/F3 inverters with a series LC resonant network in parallel with the load network. The model was solved numerically to obtain the components values for ZVS and ZDS conditions for any desired duty cycle and for any loaded Q’s of the added series LC resonant network and the output network. Kaczmarczyk’s model provided the values of duty cycles that will maximise the power-output capability and showed that maximum power-output capability of the Class EF2 and Class E/F3 inverters is higher than that of the Class E inverter for a given device rating. Other published papers about Class EF and Class E/F inverters use iterative impedance tuning methods [11] and customised RF optimisation software [6] to design and optimise the inverter. This paper will present a Class EF2 inverter to drive an inductive link at 6.78 MHz. A piecewise-linear state-space will be used to analyse the circuit and to derive it’s performance parameters and components’ values for optimum switching operation. The maximum power-output capability and the voltage and current stresses will be investigated and compared to a Class E inverter. The design and implementation of the experimental setup of a 25 W WPT system will be described
Vin
Iin
1 − ωC1 rQ 0 0 A= 1 ωL1 1 ωL3
tuned to 2fs
L1
C3 C1
Q1
L3 Io RL
C2 L2
fs
L1
+
x4
x2
L2 Vin + −
rQ
0
1 ωC1
0
0
0
1 ωC3
0
0
0
0
0
0
0
0
0
0
RL − ωL
0
0
1 − ωL
3
1 ωL2
Fig. 1. Circuit diagram of the Class EF2 driver
1 − ωL
0
B= 0
− x5 C3
2
0
Vin ωL1
0
L3
+ x1 x6 − C1 + x3 − C2
1 − ωC
0
1
3
1 − ωC 1 0 1 ωC2 0 0 0
T 0
0
(5)
C=I D= 0
RL
(4)
(6) T
0
0
0
0
(7)
0
The general solution to Eqs. 1 and 2 is given by Fig. 2. Equivalent circuit diagram of the Semi-resonant Class EF2 driver for state-space modelling
and results will be shown to confirm the accuracy of the analysis and the design. II. M ODELLING AND A NALYSIS A. Sate space modelling The circuit diagram of the Class EF2 inverter that will be studied is shown in Fig. 1. Inductor L3 represents the inductance of the transmitting coil and resistor RL represents the reflected load seen by the inverter of the receiving side circuitry in addition to the equivalent series resistance (ESR) of the transmitting coil. The inverter can be represented by the equivalent circuit shown in Fig. 2 for state space modelling and the analysis will be based on the following two assumptions: Switch Q1 has a zero switching time, a fixed OFF resistance rOFF and a fixed ON resistances rON . • The shunt capacitance C1 absorbs the output capacitance of switch Q1 and is constant. The equivalent circuit can be analysed by the following general state-space representation •
X(ωt) = Xn (ωt) + Xf (ωt).
Function Xn is the natural response matrix, or the zero-input response matrix, and is equal to Xn (ωt) = eAωt X(0)
(1) (2)
where X is the state vector and contains the following seven voltage and current states variables X(ωt) = vC (ωt) 1
T vC2 (ωt)
vC3 (ωt)
iL1 (ωt)
iL3 (ωt)
iL2 (ωt) (3)
and U is the input vector equal to a unit step function. Using KVL and KCL, the matrices A, B, C and D are given as
(9)
where e is the matrix exponential function. X(0) is the initial condition matrix. Function Xf is the forced response matrix, or the zero-state response matrix, and is equal to Z τ Xf (ωt) = eA(ωt−τ ) BU (τ )dτ = A−1 eAωt − I B. 0
(10)
The initial conditions are determined by applying the continuity conditions of the voltages across C1 , C2 and C3 and the currents of L1 , L2 and L3 when the circuit transitions from the ON state (rQ = rON ) to the OFF state (rQ = rOFF ) , hence the following equations are obtained (11) XON (0) = xOFF (ωt) ωt=2π(1−D) XOFF (0) = xON (ωt) . (12) ωt=2πD
By evaluating the above equations, the initial conditions are equal to the following
˙ X(ωt) = AX(ωt) + BU (ωt) Y (ωt) = CX(ωt) + DU (ω)
(8)
−1
AON 2πD
xON (0) −e = xOFF (0) I
AON 2πD − I) A−1 ON (e
I −eAOFF 2π(1−D)
.
−1
AOFF
(eAOFF 2π(1−D )
B. − I)
(13)
For optimal switching conditions, i.e. ZVS and ZVDS, the following states should be equal to the following vC1 (0) = 0
(14)
iL1 (0) − iL2 (0) − iL3 (0) = 0.
(15)
By using Eqs. 4-15 and the Optimisation toolbox in MATLAB, the performance parameters such as maximum switch voltage,
VGS (V)
VGS (V) 0
VDS Vin
VDS Vin
2 1
5
5
VIN (V)
25.35
13.167
3
VDSmax (V)
58.72
46.90
2
IDSmax (A)
1.86
4.35
1
PQ (W)
0.07
0.22
0
D
0.3750
0.5000
cp
0.1323
0.0981
2π
π ωt MOSFET Current
0
π ωt
2π
MOSFET Current
25
4 IDS Iin
3 2
3 2
1
1
0
0 0
2π
π ωt
0
π ωt
2
1
1 Io Iin
2 0
the maximum power-output capability of the Class E inverter is 0.0981 and occurs when the duty cycle is 0.50.
2π
Output Load Current
Output Load Current
Io Iin
2π
MOSFET Voltage
5
4 IDS Iin
25
π ωt
4
3
Class EF2 Class E
RL (Ω)
0
4
0
Parameter Po (W)
2π
π ωt
MOSFET Voltage
5
0
TABLE I C OMPARISON BETWEEN THE C LASS EF2 AND C LASS E INVERTERS
Gate Drive Signal
Gate Drive Signal
C. MOSFET conduction power loss Using KCL and assuming lossless components, the MOSFET’s drain current is
0
−1
−1
−2
−2 0
0
2π
π ωt
π ωt
iDS (ωt) = x4 (ωt) − x5 (ωt) − x6 (ωt).
2π
Inductor L2 Current
If the loaded quality factor of the output network L3 RL is high enough (>10) the output current can be assumed to be sinusoidal, i.e.
2 I L2 Iin
1 0
−1 −2 0
(a) Class E
π ωt
x5 (ωt) = io sin(ωt + φ)
2π
(b) Class EF2
Fig. 3. Comparison of the voltage and current waveforms of the Class E driver and the Class EF2 driver
maximum switch current, input and output powers as well as the components’ values can be obtained for a given coil inductance, reflected load resistance and switching frequency. Fig. 3 shows the voltage and current waveforms of the Class EF2 inverter in comparison with the Class E inverter. B. Power-output capability
Po . VDSmax IDSmax
(16)
Although theoretically the values of L2 and C2 could have any value as long as their resonant frequency is tuned to the second harmonic of the switching frequency. It is therefore of interest to find the values of L2 and C2 , in addition to the duty cycle, that would allow the Class EF2 inverter to operate at its highest power-output capability point. An exhaustive search was been performed and it was found that the maximum power-output capability is 0.1323 and occurs when the ratio of C1 /C2 is 0.867 and the duty cycle is 0.375. In comparison,
(19)
where iDSRMS is the RMS value of the MOSFET’s drain current. In order to compare the conduction loss in the MOSFET’s ON resistance for a Class EF2 inverter with that of a Class E inverter it is necessary to calculate the normalised conduction power loss which is given by [1] PQnorm =
The power-output capability is defined as the ratio of the output power to the maximum voltage and current stresses of the switch. It is an indication of the switch utilization for a certain output power. It can be represented as
(18)
where io = |x5 | and φ = ∠x5 . Eq. 17 can be used to estimate the conduction loss due to the MOSFET’s ON resistance as follows PQ = i2DSRMS rON
cp =
(17)
i2 PQ RL = 2 DSRMS2 . Po rON |x5 |
(20)
By using the values of k and duty cycle that were found previously the normalised conduction loss for the Class EF2 inverter is 0.4542 compared to a value of 1.3648 for the Class E inverter. This means for a given output power and load resistance the conduction loss in a Class EF2 inverter is approximately 66 % less that of the Class E inverter. The reduced conduction loss is due to the fact that the Class EF2 reflects a higher DC resistance to the input voltage source compared to that of the Class E inverter. Consequently the maximum MOSFET drain current is lower than that of the Class E inverter, however the maximum MOSFET drain voltage is increased. Table I compares the Class EF2 inverter and a Class E inverter that are designed to deliver 20 W to a 5 Ω load and both having a MOSFET ON resistance of 0.04 Ω and a loaded QL of 12 at 6.78 MHz.
V L1
C3 C2 C1
C4 L2
Class EF2 Inverter
C5
L3
L4 D1
Inductive Link
D2
C6
Rrect
Class D Rectifier
Fig. 4. Circuit diagram of the complete WPT system. The experimental values of the components are C1 = 257 pF (excluding the MOSFET’s output capacitance), C2 = 667 pF, C3 = 500 pF, C4 = 5 pF (parasitic), C5 = 440 pF, C6 = 200 nF, L1 = 40 µH, L2 = 215 nF, L3 = 1.4 µH, L4 = 1.25 µH, Rrect = 58 Ω 60
4
Theory
Theory Experimental
2
40
Io (A)
v DS (V)
Experimental
0
20
0
−2 0
π ωt
2π
−4
0
π ωt
2π
Fig. 5. Recorded drain voltage waveform
about their improved efficiency, reduced voltage and current stresses compared to the Class E inverter. It was found that the peak voltage across the MOSFET is about 2.3 times the input DC voltage compared to about 3.56 times the input DC voltage for the Class E inverter. The peak MOSFET current is about 2.4 times the input DC current compared to 2.86 times the input DC current for the Class E inverter. Class EF2 inverters have a higher power-output capability and reduced MOSFET conduction losses than Class E and Class D inverters. It was shown that for a given output power and load resistance, Class EF2 inverters have a lower MOSFET conduction power loss than Class E inverters due to their lower MOSFET peak current. Lower conduction losses can be more beneficial especially in a WPT application since the MOSFET conduction loss can significantly affect the overall efficiency. Class EF2 inverters reflect a higher DC load to the voltage source which means its input voltage is higher than that of a Class E inverter and consequently the voltage stresses of Class EF2 are also higher. However, an increased input voltage might be beneficial because the input DC current and ripple will be lower, and the MOSFET’s non-linear output capacitance will have a lower impact of the inverter’s performance. ACKNOWLEDGEMENT
III. E XPERIMENTAL R ESULTS A Class EF2 inverter capable of delivering up to 25 W has been designed and implemented for a 6.78 MHz WPT system. Fig. 4 shows the complete circuit diagram of the implemented WPT system. The inductive link consisted of two coils that were formed of two turns with a diameter of approximately 15 cm and using 4 AWG copper wire. Their inductance was measured to be approximately 1.40 µH and their ESR is approximately 0.21 Ω. The coils were aligned with each other and the distance between the coils was 2 in. In order to measure the output power accurately, a currentdriven Class D rectifier was designed to provide a DC output voltage at the receiver. The Schottky diodes PMEG6030EP (60V, 3A) were used. The load resistance at the output of the rectifier was 58 Ω. The MOSFET SiS892ADN (100 V, 28 A) from Vishay (in a surface mount 1212 package) was used and the gate driver was the UCC27321 from Texas Instruments. The maximum gate drive voltage was set at 7.0 V and the input voltage to the inverter was 23 V. Fig. 5 shows the recorded drain voltage waveform of the MOSFET in comparison with the theoretical waveform and excellent agreement can be seen between the two. The measured output power at the load was 20.5 W and the input power was 23.5 W, therefore the DC-DC efficiency of the WPT system is 87.2 %. A Class E inverter was designed and built for comparison and a lower 84 % efficiency was achieved. IV. C ONCLUSIONS This paper presented a 6th-order piecewise-linear state space model of Class EF2 inverter for WPT applications. The analysis was performed to investigate the initial reports in literature
The authors would like to thank Drayson Wireless Ltd., EPSRC and EDF Energy UK for funding the research. R EFERENCES [1] M. K. Kazimierczuk, RF Power Amplifiers, 2nd ed. Chichester, UK: John Wiley & Sons Ltd, 2015. [2] A. Grebennikov, N. O. Sokal, and M. J. Franco, Switchedmode RF and Microwave Power Amplifiers. Oxford, UK: Academic Press, 2012. [3] S. Aldhaher, P. C.-K. Luk, A. Bati, and J. F. Whidborne, “Wireless power transfer using Class E inverter with saturable dc-feed inductor,” IEEE Trans. Ind. Appl., vol. 50, no. 4, pp. 2710–2718, Jul. 2014. [4] S. Aldhaher, P. C.-K. Luk, and J. F. Whidborne, “Tuning Class E inverters applied in inductive links using saturable reactors,” IEEE Trans. Power Electron., vol. 29, no. 6, pp. 2969–2978, Jun. 2014. [5] M. Pinuela, D. Yates, S. Lucyszyn, and P. Mitcheson, “Maximizing dcto-load efficiency for inductive power transfer,” Power Electronics, IEEE Transactions on, vol. 28, no. 5, pp. 2437–2447, May 2013. [6] A. Mediano and N. Sokal, “A Class-E RF power amplifier with a flattop transistor-voltage waveform,” IEEE Trans. Power Electron., vol. 28, no. 11, pp. 5215–5221, Nov. 2013. [7] A. Grebennikov, “High-efficiency Class E/F lumped and transmissionline power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 6, pp. 1579–1588, Jun. 2011. [8] Z. Kaczmarczyk, “High-efficiency Class E, EF2 , and E/F3 inverters,” IEEE Tran Ind. Electron., vol. 53, no. 5, pp. 1584–1593, Oct. 2006. [9] S. D. Kee, I. Aoki, A. Hajimiri, and D. Rutledge, “The Class-E/F family of ZVS switching amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 6, pp. 1677–1690, Jun. 2003. [10] M. Hayati, A. Sheikhi, and A. Grebennikov, “Effect of nonlinearity of parasitic capacitance on analysis and design of Class E/F3 power amplifier,” IEEE Trans. Power Electron, Feb. 2015. [11] J. M. Rivas, Y. Han, O. Leitermann, A. D. Sagneri, and D. J. Perreault, “A high-frequency resonant inverter topology with low-voltage stress,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1759–1771, Jul. 2008. [12] A. Grebennikov, “High-efficiency Class-FE tuned power amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 10, pp. 3284– 3292, Nov. 2008. [13] J. W. Phinney, D. J. Perreault, and J. H. Lang, “Radio-frequency inverters with transmission-line input networks,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1154–1161, Jul. 2007.
