COE608: Computer Organization and Architecture

COE608: Computer Organization and Architecture Course Management (Winter 2017) 1. Introduction This document provides a summary of the course management while full details are available at the course website http://www.ee.ryerson.ca/~courses/coe608/. The course website is updated regularly and it is the responsibility of the students to check it regularly.

2. Course Objectives The course covers basics of modern computer organization and architectures. The emphasis is on understanding the interaction between computer hardware and software at various levels. The students will learn the concepts of computer technology, performance evaluation, instruction set design, computer arithmetic, data path and control unit design of processors and enhancing performance with pipelining. The laboratories include the design, simulation and implementation of a RISC processor by using Quartus-II development environment and ALTERA DE2 board.

3. Text Book and Other Teaching Material Main Text: David Patterson & John Hennessy, "Computer Organization and Design. The Hardware/ Software Interface", 4th edition or 5th edition 2013, Morgan Kaufmann Publishers, Elsevier Inc., ISBN 978-0-12-374493-7 Useful Text Book for Labs: Z. Navabi, Embedded Core Design with FPGAs, McGraw Hill 2007, ISBN 978-0-07-147481-8 or ISBN 0-07-147481-1 Reference Text: Morris Mano & Charles R. Kime, "Logic and Computer Design Fundamentals", 3rd or 4th edition 2004/2008, Prentice Hall Publisher, ISBN 0-13-140539-X

Half notes, labs and problem sets are available on the course website http://www.ee.ryerson.ca/~courses/coe608/

4. Course Evaluation and Marking Scheme   

Mid-Term Exam: Labs: Final Exam:

30% 30% 40%

5. Additional Instructions and Information   

All the required course specific written reports for labs will be assessed not only on their technical and academic merit, but also on the communication skills of the author as exhibited through these reports. To achieve a passing grade in the course, the student must pass both the theory and lab components. Midterm Exam will also cover the corresponding labs to enforce individual lab attempts.

6. Instructors: Dr. Gul N. Khan Professor - Computer Engineering Phone #: (416) 979-5000 ext. 6084 Consultation Times: Tuesday 1:00PM to 3:00PM, Office: ENG448 E-mail: [email protected] Home Page: http://www.ee.ryerson.ca/~gnkhan Lab Instructors:

Mr. Muhammad Obaidullah, e-mail: [email protected] Mr. Abdullah Siddiqui, e-mail: [email protected] Mr. Rishabh Kumar, e-mail: [email protected]

7. Course Outline and Schedule  

A tentative schedule of Lectures and Labs is provided. There may be some changes in the schedule that will be announced in the class and posted on the course website. http://www.ee.ryerson.ca/~courses/coe608/ For schedule updates, please check the announcement page of the course website regularly.

Mid-term exam is scheduled in week-8 on Tuesday at 3:10 PM - March 7, 2017 Page 1 of 2

Tentative Course/Lab Outline and Schedule Week

II. III.

Laboratory: ENG408

1

Computer Systems Technology  Computer Organization, VHDL

2

Instruction set Design: Instruction representation and Addressing modes.

Lab 1: Quartus-II FPGA Development Environment ---- Submission. (2%)

3

Instruction set Design: Instructions for making decisions

Lab 2: Program counter and Register set design: Design and Simulation.

4

Arithmetic for computers: Arithmetic and Logical operations

Lab 2: Submission. (3%) Lab 3a: 32-bit ALU design and simulation.

5

Arithmetic for computers: ALU Design and Implementation

Lab 3a: Submission. (3%) Lab 3b: 8-bit ALU Implementation on FPGA.

6

Computer Performance: Performance metrics & evaluation

Lab 3b: Demo and Submission. (3%) Lab 4a: Data Memory Module.

7

Datapath: Register transfer, Data path Design

Lab 4a: Submission. (2%) Lab 4b: CPU Datapath design and simulation.

8

Datapath and Control: ASM Chart, CPU Data-path design

Lab 4b: CPU Datapath design and Simulation. Fine-tuning and Submission. (Optional)

9

CPU Control Unit

Lab 4b: Submission. (4%) Lab 5: CPU Control Unit Design.

10

Control Unit: Design and Implementation

Lab 5: Submission. (6%) Lab 6: Integration and simulation of CPU.

11

Pipelining: Data hazards, Stalls and forwarding.

Lab 6: Integration and simulation of CPU

12

Pipelining: Branch hazards

Lab 6: Submission. (7%) CPU Project Demo * Bonus *

13

Catching up and review

Late Submission and * Bonus *

MidTerm

I.

Lectures

All the required course specific written reports (e.g. labs) will be assessed not only on their technical & academic merit, but also on the communication skills of the author as exhibited through these reports. There will be a 5% penalty per day for late submission of labs or project. The students must follow and adhere to the senate policy 60 on Student Code of Academic Conduct. Available at: http://www.ryerson.ca/senate/policies/pol60.pdf Page 2 of 2