Compact Packaging of Optical and Electronic ... - IEEE Xplore

114

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 1, FEBRUARY 2005

Compact Packaging of Optical and Electronic Components for On-Board Optical Interconnects Han Seo Cho, Kun-Mo Chu, Saekyoung Kang, Sung Hwan Hwang, Byung Sup Rho, Weon Hyo Kim, Joon-Sung Kim, Jang-Joo Kim, and Hyo-Hoon Park

Abstract—An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45 mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links. Index Terms—Flip-chip devices, hybrid integrated circuit bonding, indium, optical coupling, optical interconnections, optical polymers, packaging, simulation.

I. INTRODUCTION

A

S THE clock speed of microprocessors has increased above several gigahertz ranges, conventional metal-based electric lines have increasingly becoming a bottleneck limiting Manuscript received January 14, 2004; revised May 3, 2004. This work was supported by the National Program for Tera-level Nanodevices, Ministry of Science and Technology, Korea. The flip-chip bonding study was supported in part by the Center for Electronic Packaging Materials (CEPM), the Science and Engineering Foundation, Korea. H. S. Cho was with the Optical Interconnection and Switching Laboratory, Information and Communications University, Daejeon, 305-714, Korea. He is now with the Samsung Electro-Mechanics Company, Chungcheongnam-do, 339–702, Korea, K.-M. Chu, S. Kang, S. H. Hwang, and H.-H. Park are with the Optical Interconnection and Switching Laboratory, Information and Communications University, Daejeon, 305-714, Korea. B. S. Rho was with the Optical Interconnection and Switching Laboratory, Information and Communications University, Daejeon, 305-714, Korea. He is now with the Korea Photonics Technology Institute, Gwangju 500-210, Korea. W. H. Kim was with the Optical Interconnection and Switching Laboratory, Information and Communications University, Daejeon, 305-714, Korea. He is now with the Fi-ra Photonics Company, Ltd., Gwangju 500-460, Korea. J.-S. Kim is with the Department of Material Science and Engineering, Kwangju Institute of Science and Technology, Kwang-Ju 500-712, Korea, and also with the Samsung Electro-Mechanics Company, LTD, Chungcheongnam-do 339-702, Korea. J.-J. Kim is with the School of Materials Science and Engineering, Seoul National University, Seoul 151-742, Korea. Digital Object Identifier 10.1109/TADVP.2004.842291

the overall data processing speed of electronic systems [1]. Optical interconnection techniques can provide a solution for high-speed interconnects between chips or boards to solve the inherent limits of electrical interconnects in operating speed, dense packaging, and power dissipation [1]–[4]. Three main types of transmission mediums for optical interconnections have been developed: free-space optics; fiber-ribbons; and planar waveguides [1]. The free space optical interconnection approach is difficult to realize because of bulky optics and lack of reliability, although it can utilize the full benefits of two-dimensional (2-D) vertical-cavity surface-emitting lasers (VCSELs) and photodiodes (PDs) for high I/O density [5]. Interconnection approaches using a 2-D fiber-ribbon passing above the board [6] have also a disadvantage in bulky fibers and connectors. In order to achieve a chip-to-chip optical interconnection on boards with high reliability and compactibility, an embedded-waveguide-board has, thus far, been the most appropriate structure. Optical-layer-embedded boards where optical and electrical layers are laminated into one board have been investigated, since they are very compact and can be fabricated using highly compatible processes of conventional printed circuit boards (PCBs) [7], [8]. In board-to-board optical interconnections, optical fiber films laminated on the board have been used [9]. However, they require bulky connectors to interconnect fibers and as such they are not easily applied in chip-to-chip optical interconnections. In this paper, we study an optical interconnection plate where VCSEL and PD arrays, driver and receiver ICs, and a polymer waveguide are hybrid-integrated on the same plate. The chip-tochip optical interconnection is achieved by assembling the optical interconnection plate on PCBs. This approach was developed in an effort to realize a compact and cost-effective process without bulky optics, fiber-ribbons, or connectors. II. ARCHITECTURE DESIGN AND SIMULATION A. Optical Interconnection Plate A schematic of the optical interconnection plate studied in this paper is shown in Fig. 1. Optical devices and electronics ICs required for optical interconnection, such as VCSEL/PD arrays and driver/receiver IC chips, are integrated on the top surface of a transparent substrate. To couple the light beam between the VCSEL (or PD) and the waveguides without a collimating microlens, we used a thin silica glass plate with 270- m thickness as a transparent substrate. The polymer waveguides are formed lithographically on the bottom surface of the plate, and the 45 mirror surfaces are formed using a diamond saw

1521-3323/$20.00 © 2005 IEEE

CHO et al.: COMPACT PACKAGING OF OPTICAL AND ELECTRONIC COMPONENTS

115

Fig. 1. Architecture of the optical interconnection plate designed for chip-to-chip optical interconnection. All the optical and electronic components are integrated on a transparent substrate. The plate is assembled between chips to be data-linked on a printed circuit board.

Fig. 2. Schematics of the ray tracing simulation. (a) The surface source corresponding to the VCSEL aperture emits rays, and some of them are reflected at the mirror plane and guided through the waveguide. (b) The rays guided through the waveguide are reflected at the mirror plane, and some of them are collected at the PD active window.

grooving method [10]. The VCSEL and the PD arrays are flipchip bonded on the glass substrate. The optical interconnection plate is placed between input and output data lines on a conventional PCB that requires an optical link. It is important to note that this architecture is expected to make the alignment procedure quite simple and cheap, as all the alignment steps between optical components are achieved in wafer processes and a flip-chip bonding technique.

Fig. 3. Simulated coupling efficiency of the optical interconnection plate for various core sizes of the polymer waveguide.

maximum of 15 . The rays that hit the mirror plane and satisfy the total internal reflection (TIR) condition are reflected at the mirror plane and guided through the waveguide core. Rays that do not hit the mirror plane or do not satisfy the TIR condition are regarded as a loss. The rays that are propagated through the waveguide and satisfy the TIR condition at the PD side mirror are reflected toward the receiver. The rays collected at the receiver, which has a diameter of 68 m, corresponding to the PD active window, contribute to the received optical power. All other rays that do not satisfy the TIR condition or those that are not collected by the receiver are loss terms.

B. Simulation Method In order to determine optimal dimensions for the polymer waveguide core, the coupling efficiency was simulated with various core sizes and with various misalignment conditions for VCSEL and PD arrays. The simulation program used in this study is based on ray tracing [11]. This method traces the desired number of rays. When the rays pass through the glass substrate and the waveguide, and are reflected at the 45 mirror planes, they follow the laws of optics. They are then collected by the receiver. Thus, the coupling efficiency is calculated by counting the number of rays collected at the receiver. Fig. 2 shows the schematics of the ray tracing. The surface ray source, whose diameter is 10 m, corresponding to the VCSEL aperture size, launches 100 000 rays toward the mirror plane of the waveguide, having a Gaussian intensity profile with full width at half

C. Optimum Core Size Determination by Simulation Fig. 3 shows the coupling efficiencies for various core sizes with the misalignment distances of the PD arrays along the -axis. At no misalignment, the polymer waveguides having core sizes of 80 80 m and 100 60 m show slightly higher coupling efficiencies than the others. As the misalignment distance increases beyond 30 m, the core size of 100 60 m shows better coupling efficiencies than the other core sizes simulated in this study. In lithography processes for polymer waveguide fabrication, it is very difficult to control a core layer thicker than 60 m. Thus, the core dimension of 100 60 m is determined to be optimal in view of not only the coupling efficiencies related with the misalignment tolerances but also in terms of ease of the processes.

116


Fig. 4. (a) Diagram of optical power budget considering the losses at optical elements and interfaces in the interconnection plate. The digits from 1 to 6 in (a) indicate the loss sources numbered in the light path in (b).

D. Power Budget Alignment tolerance for each optical element was determined by considering the power budget diagram shown in Fig. 4. Since the input sensitivities of commercially available multichannel receiver ICs are around 16 dBm for a bit error rate (BER) of at 2.5 Gb/s data rate, the optical power that reaches at the 10 PD should exceed this limit. The digits from 1 to 6 in Fig. 4(a) indicate the sources of the optical power losses as illustrated in Fig. 4(b). One represents the reflection loss at the interface between air and the glass substrate, 2 the coupling loss from the VCSEL array to the mirror plane of the waveguide, 3 and 5 the mirror losses, 4 the propagation loss in the 5-cm-long polymer waveguide, and 6 denotes the coupling loss from the mirror plane to the PD array. The amounts of the optical power drops at the loss sources are simulated values except the propagation loss of the polymer waveguide. The waveguide propagation loss was measured to be 0.25 dB/cm by the cut-back method and detailed experimental procedures are described elsewhere [11]. The solid line in Fig. 4(a) indicates the optical power budget when there is no misalignment in all the optical components, and the received optical power at the PD array was predicted to be 8.4 dBm. In the case of no misalignment, the mirror loss of 1.6 dB at the VCSEL side is slightly higher than that of the PD side, 0.5 dB. This is a result of a portion of the rays launched from the VCSEL aperture to the mirror plane not meeting the TIR condition because of the VCSEL’s divergence angle. Additional simulations were conducted at various misalignment conditions in order to determine the misalignment tolerance. We found that when the lateral misalignments of VCSEL and PD arrays were 20 m, and the mirror angle deviation from the 45 was 1.5 , the optical power represented by the dashed line in Fig. 4(a) decreases to 15.1 dBm at the PD array. This value is just above the receiver’s sensitivity of 16.0 dBm. From these calculations, the misalignment tolerance in packaging the optical interconnection plate shown in Fig. 1 is determined to be 20 m in lateral displacements of VCSEL and PD arrays and a mirror angle deviation of 1.5 . In the simulation method used in this study, the mode coupling between the

Fig. 5. (a) Simplified experimental setup to verify the simulation results by measuring the coupling efficiency and the effect of the misalignment on the coupling efficiency. (b) Results of the measured coupling efficiencies show a good agreement with the simulated ones.

transverse modes emitted from the VCSEL and the eigenmodes of the waveguide are not considered and, hence, the coupling efficiency may be slightly lower than the calculated values. III. EXPERIMENTAL VERIFICATION OF THE SIMULATION RESULTS In order to verify the simulation results for the optical interconnection plate, we measured the coupling efficiency and the effect of the misalignment on the coupling efficiency using the simplified experimental setup as schematically drawn in Fig. 5(a). The light signal was launched and received by multimode fiber blocks, and the polymer waveguide having polished mirror planes at the ends was attached to the back side of the glass substrate of 270- m thick using an epoxy. The input and the output fiber blocks were butt-coupled to the top of the VCSEL and the PD sides, respectively. The coupling efficiency was measured to be 8.9 dB at the best alignment condition. The measured coupling efficiency of 8.9 dB is slightly lower than the simulated value of 8.4 dB. The effect of the misalignment distance of the receiver on the coupling efficiency was measured by moving the output fiber along -axis. The results were shown in Fig. 5(b) with the simulation ones those are for the core size of 100 60 m presented in Fig. 3. The dependence of the measured values on the misalignment distance is nearly close to the simulated ones. Optical crosstalk between neighboring channels was measured to be about 31 dB, which is much better than 15 dB [13] in a free space optical interconnection using microlenses. We are unable to compare the measured optical crosstalk with the simulated one since the optical crosstalk was too low to be


117

Fig. 6. Prototype of the optical interconnection plate on which the VCSEL and the PD arrays, the driver, and the receiver chips are integrated.

detected in simulation based on the ray tracing. Our crosstalk of 31 dB is sufficiently low since the input sensitivities of commercially available multichannel receiver ICs are around 16 dBm. These results indicate that the light signals were successfully transmitted to the receiver through the silica glass plate, mirrors, and the polymer waveguide with a sufficiently low optical crosstalk. IV. FABRICATION OF THE OPTICAL INTERCONNECTION PLATE A. Wafer Processes An optical interconnection plate was fabricated by wafer processes. These processes are used to form the transmission lines, solder bumps for device bondings, and a polymer waveguide on a silica glass wafer. Fig. 6 shows the prototype of the optical interconnection plate fabricated by the wafer processes. The distance between the VCSEL and the PD array is 5 cm. Fig. 7 shows the wafer process sequences for fabrication of the optical interconnection plate shown in Fig. 6. A silica glass wafer with 270- m thickness was used as a substrate. On the substrate, Ti with thickness of 1000 Å is deposited on the backside as alignment keys for the waveguide core patterning, as illustrated in Fig. 7(a), and the metal transmission lines and alignment keys composed of 1000 Å Ti/2000 Å Ni/4000 Å Au layers are then deposited on the front side, as in Fig. 7(b). All the metal film deposition processes were performed by electron beam evaporation. Silicon nitride was deposited using plasma-enhanced chemical vapor deposition as a protection layer on the front side, followed by reactive ion etching to open the metal pads for flip-chip bonding and the window areas of the VCSEL and the PD arrays, as in Fig. 7(c) and (d). The polymer waveguide was formed lithographically on the backside, as in Fig. 7(e). A thermal curable epoxy and the SU-8 photoresist were used as a cladding and a core layer, respectively. Detailed experimental processes for the polymer waveguide fabrication are described elsewhere [12]. After forming the polymer waveguide on the backside, as in Fig. 7(f), indium solder bumps for flip-chip bonding of the VCSEL and the PD arrays were thermally deposited on the front side with a thickness of 6 m. We used indium with a melting temperature of 156 C, because our polymer waveguides are thermally damaged during the flip-chip bonding processes above 180 C. After forming the indium bumps, the silica glass wafer was diced into square optical interconnection plates. 45 mirrors on the polymer waveguide were then formed using a dicing saw with a 90 V-shaped diamond blade [10], as in Fig. 7(g). In the

Fig. 7.

Process sequences for fabrication of the optical interconnection plate.

last step for fabricating the optical interconnection plate, the VCSEL and the PD arrays were flip-chip bonded, as illustrated in Fig. 7(h). The optimum bonding condition was selected from spreading and die shear tests. Detailed experimental results are explained in the following section. B. Low-Temperature Flip-Chip Bonding Using Indium Solder Bumps In our structure, indium bump was selected to prevent thermal damage to the polymeric waveguide, as mentioned above. We first tried 80 Au/20 Sn solder bumps with a melting temperature of around 280 C, which are widely used for optoelectronic devices bonding [14], and found that the polymer film was significantly bent. As low-temperature bump materials, several alloys are used, such as 63 Sn/37 Pb (melting point, 183 C) and 52 Sn/48 In (melting point, 118 C). However, we selected In for several reasons: it has a relatively low melting point (156 C); a good thermal fatigue property; and high thermal conductivity [15], as well as it is lead-free. In order to optimize the flip-chip bonding conditions for the indium solder bumps, four-channel VCSEL arrays were flip-chip bonded on silica substrates with various bonding temperatures and pressures. The size of the VCSEL array was 1000 470 m area and 200- m thick. The bonding temperatures were 100 C, 150 C, 200 C, and 250 C and the bonding pressures were 200, 300, and 500 gf. It should be noted that

118


Fig. 8. Results of spreading tests for indium solder bumps bonded under various pressures and temperatures.

we did not employ the self-alignment method [16] which uses surface tension of melted bumps without applying external bonding pressure. The VCSEL and the PD arrays are so small and long that the samples could be shifted or rotated from the attached positions after placing. Thus, the self-alignment is not helpful in the high-precision flip-chip bonding machine we used which provides an alignment accuracy within 2 m. Therefore, the bonding pressure was maintained during cooling of the samples in our experiments. However, when the bonding temperature was too high above the melting point of In, it was observed that the indium solder spreads to the area near the VCSEL window along the metal pads and lines. To confirm the degree of spreading of the indium solder bumps and to determine the pressure limit, spreading tests were carried out. Because the substrate was transparent silica glass, we observed the spreading of the bumps using an optical microscope from the back side of the wafer. Fig. 8 shows the results of spreading tests. As the bonding temperature and pressure were increased above 200 C and 300 gf, respectively, it was clearly observed that the indium solder spread to the VCSEL windows along the metal pads and lines. This range is marked in Fig. 8 with a white-lined box. Die shear tests were conducted to measure the die shear strengths at various bonding temperatures and pressures. The detailed test method is described elsewhere [17]. The traveling speed of a stylus positioned 5 m above the substrate was 100 m s. The die shear strength is directly related with the interconnect strength between the chip and the substrate. Fig. 9 shows the measured die shear strengths, which clearly increase as the bonding temperature and pressure increases. In the results of the spreading test shown in Fig. 8, the conditions showing severe spreading of the bumps should be excluded to avoid blocking the optical device windows. In the results of the die shear strength tests shown in Fig. 9, the low strength conditions might not be suitable for good device adhesion. The conditions at which the solder bumps spread to the area near the VCSEL windows, as described previously, are marked in Fig. 9 with solid boxes. As mentioned before, the polymer waveguide formed on the bottom side of the fused silica substrate was damaged when bonding was conducted at a temperature of 250 C, marked as a dashed box in Fig. 9. Considering the aforementioned results, we determined the optimum bonding conditions in our study, in terms of providing the strongest

Fig. 9. Die shear strength measured for various temperatures and pressures for the flip-chip bonded test chips using indium bumps.

Fig. 10. Optical interconnection plate packaged with the VCSEL and the PD arrays and the driver and receiver ICs was assembled into the opening of the PCB for data link test. Enlargement of the boxed area in Fig. 10(b) is presented in Fig. 10(a), which shows the VCSEL array flip-chip bonded on the optical interconnection plate and wire-bonded to the driver.

bonding strength without solder bump spreading, to be a temperature of 150 C under a bonding pressure of 500 gf. C. Assembling the Optical Interconnection Plate Into an Evaluating Board After the VCSEL and the PD arrays were flip-chip bonded, driver and receiver ICs were wire-bonded beside the VCSEL and PD arrays on the optical interconnection plate. All array devices and ICs have 1 12 channels with 250- m pitch. Fig. 10(a) shows the VCSEL array and the driver IC chip bonded on the interconnection plate. The wire bonding was conducted at a relatively low temperature of around 90 C. The VCSEL array can be displaced during the wiring bonding if the wire bonding temperature is too high. The optical interconnection plate assembled with all the optical devices and electronics ICs required for optical interconnection was inserted into the opening of the PCB fabricated as an evaluating board, shown in Fig. 10(b). The optical interconnection plate was fixed in the board using a thermal curable epoxy. V. MEASUREMENT RESULTS AND DISCUSSION Fig. 11 shows the measured eye pattern for the evaluation board assembled with the optical interconnection plate at data 1 pseudorandom bit sequence rates of 455 Mb/s with a 2


119

although mirror planes were grooved with sufficiently high accuracy. These rough surfaces and large angle deviation of the mirror might cause the poor coupling efficiency. Note that Au film with thickness of 4000 Å was coated on the mirror surface, however, the mirror loss was little improved. It is expected that more improvement of the mirror surface roughness and the mirror angle accuracy could lead to optical link at high rates up to at least 2.5 Gb/s. VI. SUMMARY Fig. 11. Measured eye pattern at data rates of 455 Mb/s for the evaluation board assembled with the optical interconnection plate.

Fig. 12. (a) Experimental setup for measuring the beam intensity profile and the optical power at the PD side. (b) Measured beam intensity profiles showing a nearly elliptical shape and flat at the peak.

We designed and fabricated the optical interconnection plate for a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. It was fabricated using wafer processes and flip-chip bonding so that the alignment procedures were quite simple and economical. Flip-chip bonding of the optical devices on the optical interconnection plate was performed using indium bumps at the optimized condition in order to avoid thermal damage of the polymer waveguide. Fully packaged optical interconnection plate with the evaluation board showed optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to optical link at higher rates. In a real implementation of the optical interconnection plate, if a thin plastic plate or a flexible transparent film is used instead of the glass plate, handling of the plate could be easier in integration processes of chips and in construction on interconnection boards. REFERENCES

(PRBS) wordlengths. However, we could not obtain an eye pattern at data rates of 2.5 Gb/s. The output light beams were observed by placing a chargecoupled device (CCD) camera on the PD side of the optical interconnection plate after removing the PD array; the experimental setup is schematically drawn in Fig. 12(a). The measured output beam for one of the 12 channels shown in Fig. 12(b) has a nearly elliptical shape. Also, the intensity profiles, drawn with lines on the bottom and left sides in Fig. 12(b), show flattened shapes at the peak. The received optical power was measured by placing a large area detector instead of the CCD camera in Fig. 12(a). The measured optical power divided by the number of channels was 19 dBm. Considering the simulation result of 3.9 dB for the coupling loss from the mirror plane to the PD window at no misalignment condition, the received optical power per channel at the PD window is estimated to be less than 22.9 dBm. This is quite lower than the receiver’s senat rates of 2.5 Gb/s. sitivity of 16 dBm for a BER of 10 Since the output power of the VCSEL array at on-state during modulation was around 2 dBm per channel, the coupling efficiency was about 25 dB. This poor coupling efficiency cannot be explained by misalignments of the VCSEL and the PD arrays since they were roughly measured to be less than 10 m. We could only roughly measure the misalignment distance of the VCSEL and the PD arrays, since the mirror planes on the backside of the optical interconnection plate make it difficult to measure it. We found that the grooved mirror surface of the polymer waveguide was rough and mirror angle was about 41 ,

[1] M. Forbes, J. Gourlay, and M. Desmulliez, “Optically interconnected electronic chip: A tutorial and review of the technology,” Electron. Commun. Eng. J., pp. 221–232, 2001. [2] A. F. J. Levi, “Optical interconnections in systems,” Proc. IEEE, vol. 88, no. 6, pp. 750–757, Jun. 2000. [3] R. Lytel, H. L. Davidson, N. Nettleton, and T. Sze, “Optical interconnections within modern high-performance computing systems,” Proc. IEEE, vol. 88, no. 6, pp. 758–763, Jun. 2000. [4] N. Savage, “Linking with light,” IEEE Spectr., vol. 39, no. 8, pp. 32–36, Aug. 2002. [5] A. G. Kirk, D. V. Plant, T. H. Szymanski, Z. G. Vranesic, F. A. P. Tooley, D. R. Rolston, M. H. Ayliffe, F. K. Lacroix, B. Robertson, E. Bernier, and D. F. Brosseau, “Design and implementation of a modulator-based freespace optical backplane for multiprocessor applications,” Appl. Opt., vol. 42, pp. 2465–2481, 2003. [6] B. Wittmann, M. Johnck, A. Neyer, F. Mererer, R. King, and R. Michalzik, “POF-based interconnects for intracomputer applications,” IEEE J. Sel. Topics Quantum Electron., vol. 5, no. 5, pp. 1243–1248, Sep./Oct. 1999. [7] Y. Ishii, S. Koike, Y. Arai, and Y. Ando, “SMT-compatible large-tolerance “optobump” interface for interchip optical interconnections,” IEEE Trans. Adv. Packag., Manufact. Technol., B, vol. 26, no. 2, pp. 122–127, May 2003. [8] F. Mederer, R. Jager, H. J. Unold, R. Michalzik, K. J. Ebeling, S. Lehmacher, A. Neyer, and E. Griese, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett., vol. 13, no. 9, pp. 1032–1034, Sep. 2001. [9] M. A. Meis, “Opto-electronic backplane technology for cost effective bandwidth management,” in Proc. Electronic Components Technology Conf., 2003, pp. 1073–1079. [10] R. Yoshimura, M. Hikita, M. Usui, S. Tomaru, and S. Imamura, “Polymeric optical waveguide film with 45 -mirrors formed with a 90 V-shaped diamond blade,” Electron. Lett., vol. 33, pp. 1311–1312, 1997. [11] H. S. Cho, W. H. Kim, and H.-H. Park, “A simple method for calculating coupling efficiency in optical interconnection system involving various misalignment parameters,” Opt. Lasers Eng., 2004, to be published.

120


[12] J.-S. Kim, J.-W. Kang, and J.-J. Kim, “Simple and low cost fabrication of thermally stable polymeric multimode waveguides using a UV-curable epoxy,” Jpn. J. Appl. Phys., vol. 42, pp. 1277–1279, 2003. [13] E. M. Strzeleckae, D. A. Louderback, K. Bertilsson, B. J. Thibeault, M. Mondry, and L. A. Coldren, “Free-space optical link realized with microlensed components,” in Proc. Electronic Components Technology Conf., 1997, pp. 376–381. [14] A. R. Mickelson, N. R. Basavanhally, and Y. C. Lee, Optoelectronic Packaging. New York: Wiley, 1997, p. 210. [15] C.-C. Liu, Y.-K. Lin, M.-P. Houng, and Y.-H. Wang, “The microstructure investigation of flip-chip laser diode bonding on silicon substrate by using indium-gold solder,” IEEE Trans. Compon. Packag. Technol., vol. 26, no. 3, pp. 635–641, Sep. 2003. [16] L. S. Goldman, “Geometrical optimization of controlled collapse interconnections,” in Proc. Electronic Components Conf., 1972, pp. 332–339. [17] K.-M. Chu, J.-S. Lee, B. S. Rho, H. S. Cho, H.-H. Park, and D. Y. Jeon, “Optimization of low temperature flip chip bonding for VCSEL arrays for polymeric-waveguide-integrated optical interconnection systems,” in Proc. 9th Microoptics Conf. (MOC), Tokyo, Japan, Oct. 29–31, 2003, pp. 402–405.

Han Seo Cho received the Ph.D. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1999. He worked as a Postdoc with The Johns Hopkins University, Baltimore, MD, until 2001. He was a Research Professor at the Information and Communications University (ICU), Daejeon, Korea. He is currently a Principal Engineer with the Samsung Electro-Mechanics Company, Daejeon, Korea. His research interests include optical material characterization, and designing, optical simulation, packaging of optical interconnection modules for electrooptical printed circuit boards (EPCBs).

Kun-Mo Chu received the B.S. degree in materials science and engineering from Korea University, Seoul, Korea, in 2001, the M.S. degree in materials science and engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003, and he is currently pursuing the Ph.D. degree at KAIST. He is currently a Research Assistant with the Information and Communications University (ICU), Daejeon, Korea. His research interests include optical interconnection architecture and flip-chip bonding technology for electronic and photonic devices.

Saekyoung Kang was born in Korea in 1974. He received the M.S. degree in engineering from the Information and Communications University (ICU), Daejeon, Korea, in 2003, where he is currently pursuing the Ph.D. degree. He has designed and tested many mixed-signal CMOS circuits for opitcal interconnection applications.

Sung Hwan Hwang received the M.S. degree in optical communication engineering from the Information and Communication University (ICU), Daejeon, Korea, in 2001, where he is currently pursuing the Ph.D. degree in optical communication engineering. He has been engaged in research on the driver and receiver IC design of VCSEL and PD arrays for optical interconnection during the M.S. degree. Since 2002, he has developed 12-channel parallel optical modules for very short reach application with the Fionix Corporation, Daejeon, Korea. Currently, he is engaged in research and development on chip-to-chip optical interconnections and optical PCBs.

Byung Sup Rho received the Ph.D. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000. He was a Senior Researcher with the Korea Photonics Technology Institute, Gwangju, Korea, and is currently a Senior Researcher with the Korea Photonics Technology Institute, Gwangju, Korea. He has been studying optical interconnections for chip-tochip and board-to-board data links, including optical material characterization, design, and demonstrations of optical interconnection using electrooptical printed circuit boards. Also, he has been studying optical device packaging with flip-chip bonding techique.

Weon Hyo Kim received the Ph.D. degree in materials science and engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2001. He worked as a Postdoc at the Information and Communications University (ICU), Daejeon, Korea, in 2001. He is currently Chief of Research and Development with the Fi-ra Photonics Company, Ltd., Gwangju, Korea. He has been studying chip-to-chip optical interconnection and planar lightwave circuits.

Joon-Sung Kim received the B.S. degree in materials engineering from Chonnam National University, Gwangju, Korea, in 1998, and the M.S. and Ph.D. degrees in materials science and engineering from Kwangju Institute of Science and Technology (K-JIST), Kwangju, Korea, in 2000 and 2004, respectively. His thesis work involved optical interconnection and optical waveguide devices from organic materials. He is currently with Samsung Electro-Mechanics Company, Ltd., Chungcheongnam-do, Korea. His research areas include optical waveguide devices and optical PCBs.

Jang-Joo Kim received the B.S. and M.S. degrees in chemical engineering from Seoul National University, Seoul, Korea, in 1977 and 1980, respectively, and the Ph.D. degree in materials science and engineering from Stanford University, Stanford, CA, in 1987. From 1986 to 1987, he was a Postdoctoral Fellow with SRI International, Menlo Park, CA. He returned to Korea to join the Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea, as a Senior Member and a Principal Member of Technical Staff from 1987 to 1996. He was a Professor at the Kwangju Institute of Science and Technology (K-JIST), Kwangju, Korea, from 1997 to 2003 and is currently a professor in the School of Materials Science and Engineering, Seoul National University, Seoul, Korea. His research areas include polymer waveguide devices, plastic optical fiber, electroluminescence from organic materials, and organic electronics. He has published more than 100 papers and holds over 30 patents.

Hyo-Hoon Park received the Ph.D. degree in material science and engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1985. From 1985 to 1986, he worked in the area of compound semiconductor devices at Stanford University, Stanford, CA, as a Postdoctoral Scholar. From 1986 to 1997, he was with the Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea, working in the area of high-speed electronic devices and vertical-cavity surface-emitting lasers. Since 1998, he has been a Professor in the Optical Communication Group at the Information and Communications University (ICU), Daejeon, Korea. Since joining ICU, he has been studying optical interconnections for chip-to-chip and board-to-board data links, optical transceiver modules and optical switching components for optical communication systems and networks.