Comparison study of phase-shifted full bridge ZVS converters

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Abstrucr-The Phase-Shifted full bridge (PSFB) ZVS-PWM converter is widely adopted in medium to high power applications. But the conventional PSFB has ...
2004 35th Annual IEEE Power Neclronics Specialisis Conference

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Comparison Study of Phase-Shifted Full Bridge ZVS Converters J. M. Zhang X.G Xie X.K. Wu Zhaoming Qian College of Electrical Engineering, Zhejiang University Hangzhou 3 10027, Chma Phone: +86-571-87952245, Fax: +86-571-87952224 Email: [email protected]

Abstrucr-The Phase-Shifted full bridge (PSFB) ZVS-PWM converter is widely adopted in medium to high power applications. But the conventional PSFB has many limitations and many improved topologies have been proposed to improve the performance of the PSFB ZVS converter. This paper presents a detailed review for these techniques. The merits and limitations of these techniques are analyzed and their key features and characteristics are compared. Based on the review and comparison, an improved PSFB ZVS converter is proposed. A guidance of selection optimized topology for practical application is also discussed in this paper. Related Simulation results and experimental results are presented. INTRODUCTION The phase-shifted full bridge (PSFB) ZVS converter is one of the most widely used soft-switched topologies in industry applications. However, it suffers several problems, such as the narrow ZVS range, the large duty cycle loss, severe secondary side rectifier voltage rings and the large circulation energy etc. Many techniques have been proposed to solve these problems mentioned above [l-241. Generally, they can be classified into three catalogs, i.e. using saturable reactors (SRs) or magamps; using passive auxiliary circuits; and applying active auxiliary circuits. In this paper, we mainly focus on the first two methods. A comparison of these techniques on the conduction loss, the duty cycle loss, the ZVS range, the circuit complexity etc., is presented in this paper. The main purpose of this paper is to filter out the most suitable topology &om existing topologies for practical applications. Firstly, the topologies with SR or magamp will be reviewed and analyzed in Section 11. A comparison is presented based on the analysis. Section 111 presents the analysis of the topologies with passive auxiliary circuits. And an improved PSFB ZVS converter with coupled inductor is proposed. The optimized leakage inductance for these topologies is analyzed. Guidance on how to select optimized topology for practical application is also discussed in the paper. A conclusion is given in Section IV. I.

11. PSFB zvs CONVERTERS WITH SR OR MAGAMP According to the position of SR or magamp, these topologies can be divided into two types, i.e. primaty side located and secondary side located. The purpose of using SR or magamp is to use the energy stored in the output inductor or the magnetizing inductor to extend the ZVS range. First of all, a brief review of these topologies is presented. To simplify the discussion, the following definitions and

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assumptions are used throughout the text: Cos$: Drain-to-source capacitance of one MOSFET. T,: Dead time for lagging leg c: Switching period Kn: Input voltage L,: Resonant inductor Magnetizing inductance of the transformer L,: I,,: Output current Rdr-,,": MOSFET turn on resistance It is assumed that the transformer turns ratio is I, and the leakage inductance of the transformer can be ignored. The output inductor is large enough and the ripple current can be neglected.

Topology review To reduce the duty cycle loss and the circulation energy, a saturable inductor instead of the traditional linear inductor is employed as the resonant inductor, and the leakage inductance of the transformer is minimized [2]. However, the SR placed on the primary side has a thermal problem. The ZVS condition for lagging leg and the duty cycle loss still need trade-off. And the voltage rings across the rectifier diode still exists. The circuit diagram and the theoretical waveforms are shown in Fig. 1.

A.

(a) Circuit diagram

.I

i ",*.-.&la

...s. I \.

'i

(b) Steady state waveform

Fig. I Topology I:PSFB with SR at primary side [2]

In conventional PSFB topology, the magnetizing current can be used to achieve ZVS only when it is larger than the reflected load current. However, if the magnetizing current were increased to meet this requirement, the primary side conduction loss would increase a lot. With the SRs in series with the rectifier diodes as shown in Fig. 2, the magnetizing

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c u r r e n t does n o t need to be larger t h a n t h e reflected load current to a c h i e v e ZVS. When one switch in the l a g g i n g leg is switched off, the output current f r e e w h e e l s through t h e f r e e w h e e l i n g diode, a n d t h e s e c o n d q w i n d i n g of t h e transformer i s n o t s h o r t e d . T h e n t h e m a g n e t i z i n g c u r r e n t can be used to achieve ZVS for the l a g g i n g l e g switches. The main advantage of this topology is with wide ZVS range and without voltage rings of output rectifier diodes due to the SRs. However, when duty cycle at the steady state operation is small, the conduction loss becomes quite large.

(a) Circuit diagram

Tj Tz T I T J r T .

To

7,

(b) Steady state waveform

Mi

i- - - l

(b) Steady state waveform Fig. 2 Topology 2: ZVS using magnetizing current [3] Another type of PSFB using magnetizing current to achieve ZVS is shown in Fig. 3. By using two transformers, the magnetizing current for each leg is not varied with the duty cycle. And ZVS can be achieved at full load range. The voltage rings of the rectifier diode are also eliminated.

Fig. 4Topology 4: ZVS usingoutput current [5-91 The SR can b e substituted with magamp. Due to the turn on1 and turn off of magamp can be controlled,-the-topologies with magamp can be controlled at the secondary side, and no phase shiR of primary side switches is needed. The topology shown in Fig 5 is almost the same as that shown in Fig 2 but with more complex control circuit. The primary switch pair operates with 50% duty cycle and the magnetizing current is constant, therefore ZVS for these switches is very easy to achieve. Nevertheless, the additional control circuit complicates the whole topology.

(a) SLS4

II

1I

1 I S2.S) SI n E

SI.S4

m

s5

(a) Circuit diagram

Circuit diagram S2.SI

' I, ---I

L-:

&

.---

I

(b) Steady state waveform Fig. 5 Topology 5: ZVS using magnetizingcurrent and Magamp [IO] The topology shown in Fig 6 is similar to topology 4, but S5 and S6 should be conducted complementary. And the output ripple current is larger than other topologies. The topology shown in Fig 1 is similar to topology 6, but a freewheeling diode and SR is added to improve the performance of topology 6. ZVS for primary side switches is also achieved by the energy stored in the output filter inductor.

* , *

I 4 I 6

(b) Steady slate waveform Fig. 3 Topology 3: ZVS using magnetizingcurrent [4] The topology 4 shown in Fig 4 is very similar to that o f topology 2 but the freewheeling diode is removed here. However, the ZVS can be achieved by the energy stored in the output filter inductor in this topology due 10 the block effect of SR. The ZVS condition for the leading leg and lagging leg is same.

(a) Circuit diagram

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(7) I

For comparison, the minimum current required to achieve ZVS in a reasonable time is assumed to be same for each topology, which is also expressed as

(b) Steady state waveform Fig. 6 Topology 6: ZVS using output current and magamp [ I I I

The duty cycle loss can be normalized according to the base shown as

m;

For comparison, the normalized duty cycle conventional PSFB topology is given in Table 1.

for

(a) Circuit diagram

SISI

"'P 3

-_

S2.S

It can be seen that the duty cycle loss of topology 2 , 3 and 5 is the smallest one. The duty cycle loss of conventional PSFB topology is heavily depended on the ZVS range.

..____ .I -..___ ;

..__

Circulating Energv and the conduction loss The energy stored in the leakage inductor, in primary side SR or in the magnetizing inductor do not contribute to the power conversion, it is referred as circulation energy. Though the circulating energy helps soft switching, it also increases the conduction loss in the circuit. With the

b)

SRblo;*""K

IP

(b) Steady state waveform Fig. 7 Topology 7: ZVS using magnetizing current and magamp [IO]

Characteristics comparison

B.

therefore the duty cycle loss is given as 2.1c'Lr Td 4.C0.~.5 .v,n AD= +-= ,(2+:) (3) Vi" T, I 2 T, I 2 T, .1, For topology 2,3 and 5 , the required dead time to achieve ZVS and the duty cycle loss are given as

- 2 .C , .v,n

d -

1,

(4)

'n i' ,L ADD=--'d - 4' (5) T, 1 2 T, I, For topology 4, 6, and 7, ZVS is achieved by the output filter inductor, The required dead time and duty cycle loss can be expressed as T.,= 2 ' cos, ' V," (6)

1

O".,

0.5

I 0.55

"6

061

0 1

D

071

08

081 0.9

Fig 8 Circulating energy oftopalogy 6 vs. duty cycle D

The secondary side conduction loss is a'most the for all these topologies. Therefore, the comparison will focus on the primary side conduction loss. For simplification, the duty cycle loss is omitted and the conduction loss is normalked to the power base given in (10). With the

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2004 35th A n n u l IEEE Power Electronics Specialists Conference

Iperformance. Due to the high power loss of SR, the switching frequency and power level of topology 4 should Inot be too high.

assumption given in (8), the primary side conduction loss for each topology is given in (11) to (16) respectively. The conduction loss of topology 6 is the same as that of topology 4 as given in (14). The relationship between conduction loss and maximum duty cycle is shown in Fig. 9. Pmn-bo.?e

P,.!

=

2'12

.'&on

D ) . ( l h -1)

= 1+0-

2

Pcon3 = 1 + I r m m / 6 Pcon4 = pc0n6 = 2

Peons =D+Irmm / 3 + 2 . / r m o . D ' ( l - D )

Pcmj

I. I

(10)

_~I. .......I._..,,,,_,, Topology 2 --..%.. .. ~

Topology 3

(11)

(13) (14)

(15)

06 0.7 07

(16) From Fig. 9, it is clear that the conduction loss of topology 2 is much larger and it increases with the decreasing of the maximum duty cycle. Therefore, topology 2 is not suitable for those applications with wide input voltage range. The conduction loss for topology 1 is quite small, however the magnetic loss of SR is much larger with high switching frequency. Topology 7 has the smallest conduction loss. pon7 = D

0.75

0.8

0.85

0.9

0.95

D

Fig 9 Primary side conduction loss P-

I I

vs. duty cycle D

111. PSFB CONVERTERS WITH PASSIVE AUXILIARY CIRCUITS

ZVS range For topology 1, when the output current is below the critical value, ZVS will be lost. For topology 2 , in order to avoid large conduction loss, the soft switching can't he achieved at light load condition (small duty cycle). For topology 3 and 5, the magnetizing current does not change with the load condition and duty cycle, thus ZVS can be achieved at no load condition. For topology 4, 6 and 7, the output current is used to achieve ZVS and the ZVS range is very wide, but due to the limited dead time, sofl switching will lose at light load condition. Therefore, some trade-offs should be made between the ZVS range and duty cycle loss or conduction loss. c)

Parasilic rings of rectifier diode The reverse recovery problem and the parasitic voltage rings of the rectifier diode will contribute a large part of the total power loss. Though the parasitic ringing of topology 1 is improved, it is still an'open question due to the energy stored in the SR. And an extra snubber circuit is usually needed. For topology 2 to 7, the energy stored in the SR or magamp is very small, and the SRs or magamps has large inductance when the current is small, thus the reverse recovery problem is improved and no extra snubber circuit is needed for the rectifier diodes, which results in simple topology structure and improved EM1 performance. A detailed comparison for these topologies is summarized in Table 3. As shown in Table 3, the topology with magamp (topologies 5-7) is more suitable for multi-output applications. Among these three topologies, topology 6 has the worst performance, topology 7 is more complex due to more auxiliary magnetic components. For single output applications, topology 1-4 is more suitable than topology 5-7. Based on the comparison, topology 4 is more attractive in practical applications due to its simplicity and good

d)

'

The PSFB ZVS converter with passive auxiliary circuit falls into two types. One type is the auxiliary circuit is in series with the transformer and usually an inductor is adopted [12-15]. These topologies extend the ZVS range by storing the energy in the inductor. In order to alleviate the voltage ring of secondary rectifiers, usually a clamp circuit such as clamp diodes or auxiliary windings is also needed. However, these topologies still suffer from the large duty cycle loss and a limited ZVS range. Trade-offs must be made between the duty cycle loss and ZVS range. Another type is that the auxiliary circuit is paralleled to the lagging leg as shown in Fig.10. There are totally 4 types of passive auxiliary circuits as shown in Fig. I I . The current waveforms for these four auxiliary circuits are shown in Fig. 12 respectively. As shown in Fig. 12, the passive methods land 2 are the same[16-18]. Though the passive method 4 can reduce the conduction loss, the magnetic core loss is more severe and the SR block time is difficult to design when input voltage varies [19]. Therefore, the passive method 4 is seldom used in practical applications. The passive method 3 has a higher conduction loss than the passive method 2 but the volume of the passive component can be reduced due to smaller inductance and capacitance. A comparison of conduction loss of passive method 2 and 3 is shown in Fig. 13. From the point of efficiency and performance, passive method 2 is a better choice.

Fig I O PSFB topology structure with p&leled auxiliary circuit

A.

Topology review

A conventional ZVS PSFB converter using passive method 2 (referred as topology 8 hereafter) is shown in Fig.

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TABLE~ACOMPAR~SONOFTOPOLOG~ES 1-7

no

Passive method I

no

T

Passive method 2

no

no

1

Yes -

~I

yes

I

yes

I

topologies 9 and I O have problems when the converter powers on. The simulation results of the voltage waveform applied to the transformer of topology IO is shown in Fig. 14(d). It i s clear that the transformer will be saturated. An improved topology shown Fig. 15 is proposed in this paper to solve the start-up problems. The steady state operation of the proposed topology is the same as that of topology IO. The simulated transformer voltage waveform is given in Fig. 16.

Parrive method 3 Pasrive rnelhcd 4 Fig I I Four types of passive auxilialy method

(c, Topology

(d) Transformer voltage waveform of topology IO at start-up period Fig. 14 PSFB ZVS converter with passive method 2 [21, 221

Fig 12 Current waveforms of four types of passive auxiliary circuit I 2

Fig I5 Topology I I : proposed improved ZVS PSFB converteer

B.

Fig 16Transformervoltage waveform oftopology I I at start-up period

Characteristics Comparison A comparison of conduction losses of topologies 8 and 11 o n t 0.2 0.3 0 4 0.5 will be analyzed here. For comparison, the magnitude of the n O S I.atl0 current in the auxiliary circuit is the same in these two Fig 13 Conduction loss of passive method 2 and 3 topologies, which is given as 1 V,, 1 1 V,, 1- D 14(a). Another kind of ZVS PSFB converter using passive I =_.__.-=__ (17) 2 2 . L , 2 . f , 2 2.L, 2 . f , method 2 (referred as topology 9) is shown in Fig. 14@) [2O]. For both topologies, the soft switching of primary side 'Wo~ogY 10 shown in Fig. 14 (c) L21-221 has the Same operation principle as topology 9, which can be derived switches is achieved by the auxiliary circuit, from toPohY 9 using circuit transforming. US~IlY, therefore, the leakage inductance can be minimized and the Passive method 2

0.4

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duty cycle can be limited. The circulating energy for topology 8 is the energy stored in the auxiliary inductor La as shown in Fig. 14(a), which is given in (18). The circulating energy for topology I I is the energy stored in the coupled inductor as shown in (19). According to the assumption given in (17), the relation ship of the inductance of auxiliary inductor in these two topologies is given in (20).

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larger than that at full load condition. It is unacceptable for practical applications. Therefore, the maximum duty cycle for topology 9 should not be too larger if the auxiliary circuit is designed based on heavy load condition.

C o n d u s i i o n loss a t 2 2 .: ~.

Enr-9

I

=-'Lo, 2

2

'

1,

L,2 = ( l - D m , ) . L , , , (20) where LaI and L& is the inductance of auxiliary inductor in topology 8 and 9 respectively. D, is the maximum operating duty cycle. From (20), it is clear that the circulating energy of topology 9 at no load condition (D=O) will be l/(l- Dm,) times larger. Thus the maximum duty cycle for topology 9 should not be too large. If the current of auxiliary circuit is designed based on the no load condition (D=O), the auxiliary current at heavy load condition maybe too small to achieve

zvs.

The conduction loss for topology 8 and 9 is given in (21) and (22) respectively. For simplification, the conduction loss is also normalized base on (IO) and the I,,. is defined in (23). 2 Pcm.s = 1 + I , , , / 6 (21) Pcon-9 =1+Im,,, 2 /12+1~o,,o.D/6 (22) 'mm

................ ......

Conduction 101% a! .full load condition

(19)

9

.........................

:

" 2

"1

"6

om..

os UP

Fig 18 No load conduction loss oftopology 9-11 vs maximum D

The ZVS range for these two topologies is very wide. The current of auxiliary circuit also helps to achieve ZVS of leading lag in topology 9. The parasitic voltage ring of the output rectifier diode also exists for both topologies. A comparison of topologies 8 and 9 is summarized in Table 4. From Table 4 and Fig. 18, topology 9 is not suitable for the application with large input range, and the steady state duty cycle should not be too large. But it is more suitable for the application with stable input voltage and large holdup time requirement. TABLE~COUP~R~IONOFTOPOLOC.IFI RAND9

(23)

=

From the equations given above, the conduction loss for these two topologies is the same when D=0.5. When the duty cycle is above 0.5, the conduction loss of topology 9 be larger than topology S. The conduction loss VS is shown in Fig. 17. I25 ?..... ...........

II

~~

...

9 e: D=O.2 'pology

...............I ............I

. . . . . . . . .

I

o 95 0

0

02

0 4

06

08

1ra.o

I

I

Fig 11 Conduction loss of topology 8 and 9 VI. I,,

As mention above, the circulating energy at no load condition of topology 9 will much larger than that at full load condition if the auxiliary circuit is designed based on heavy load condition. In such a condition, the conduction loss will be very large at no load condition if the , D is large as shown in Fig. 18. If the maximum duty cycle can exceed 0.75, the conduction loss at no load condition will be

c.

Leakage inductance conriderotions

Using the passive method, the

zvs

for lagging leg is

achieved by the energy stored in the passive auxiliary circuit. Therefore, the leakage inductance can be minimized. ]f the leakage inductance is too small, ZVS will be lost at heaw load condition due to the fast current commutation, but thk ZVS is still achieved in light load condition. In order to maintain ZVS at heavy load condition, the current through auxiliary circuit needs to be much larger, and the conduction loss increases. It is preferred that the leakage inductance is scaled to a small value, such that, ZVS for lagging leg can be achieved in full load range and the conduction loss of auxiliary circuit remains a small value. The optimized leakage inductance is to prevent the load current exceed the auxiliary circuit current during the dead time of gate signal and is given below. It is preferred that the required inductance given in (24) is an external inductor, therefore, the diode clamp can be adopted to prevent the voltage ring on the output rectifier [ 121. L , 2 4 . Lo . T d , fs, (24) where Lk is the required leakage inductance, La is the inductance of auxiliary inductor. The experimental results from topology 8 are shown in Fig. 19. It is clear that the ZVS is lost at heavy load

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condition when leakage inductance is too small. With a increased leakage inductance according to (24), the ZVS is achieved at heavy load condition.

(a) Io=8A, Lr=2uH

.

/.n,... .

Aachen, Germany, 2004

[XI Junming Sun. Satorhi Hamadq Junyi Yoshitsugn, Bin Guo, Mutsuo

(b) lo=2A, LI =2uH

(c) lo=8A, Lk-9uH Fig. 19 Experimental results for ZVS of lagging leg in topology 8: Vm=400V, VF~OOV. f,=IOOkHz, Ib=4A

IV. SUMMARY In conclusion, this paper reviews ZVS PSFB topologies and a comparison for these topologies is carried out. Based on the comparison, an improved topology shown in Fig. 15 to solve the start-up problem is proposed to overcome the drawbacks of previous proposed topology. In order to optimize the performance of the ZVS PSFB with passive a u x i l i q circuit, the optimized leakage inductance is also presented. Simulation results and experimental results verified the theoretical analysis. ACKNOWLEDGEMENT This work is supported by China National Science Fund, No 50237030.

Nakaaka ‘Zero Voltage SoftCommutation PWM DC-DC Converter with Saturable Reactor Switch-Casaded Diode Rectifier”, IEEE Trans. on Circuit and System, vol. 45, No. 4, April, 1998, pp.348-354 [9] Akiko Kajiyamq S. Hamada M. Nakaoka, “Active Sahrable Reactor Switch and Lassless Capacitor-Assisted Zero-Voltage Transition Asymmetrical PWM DC-E€ Converter”, IEEE INTELEC’96, pp.289-296 [IO] Robert Waston, Fred C. Lee,.“Analysis, Design, and Experimental Results of a I-kW ZVS-FB-PWM Convener Employing Magamp Secondary-Side Control“, IEEE Trans. on I.E., vol. 45, No. 5, October, 1998, pp.806-813 [ I I] Milivoje Brkovic, Andrerej Pietkiewicz, Slobodan Cuk, “Novel Soft-Switching Full-Bridge Converter With Magnetic Amplifiers”, IEEE INTELEC’94, pp.155-162 [I21 Richard Redl, Nathan 0. Sokal, Laszlo Balogh, “A Novel Soft-Switching Full-Bridge DCIDC Converter: Analysis, Design Considerations, and Experimental Results al ISkW, IOOkHz”, IEEE Trans. P.E., vol. 6,No. 3, July, 1991,pp.408-418 [I31 Richard Redl, Laszlo Balogh, David W. Edwards, “Optimum ZVS Full-Bridge DCmC Convener with PWM Phase-Shift Control: Analysis, Design Considerations, and Experimental Results”, IEEE APEC’94 [I41 Stanimir Valtchev, Beatria V. Barges, “IKW/25OkHz Full Bridge Zero Voltage Switched Phase Shift DC-DC Converter wilh Improved Efficiency”, INTELEC‘95, pp.803-807 [ I S ] G. Moschopoulos, P.D. Ziogas, G. loos, “A Fixed Frequency ZVS High Power PWM SMR Converter wilh Zero to Rated Load Variation Capability, INTELEC’92, pp.35 1-358 [I61 Praveen K. Jian, Wen Kang, Harry Soin, Youhao Xi, “Analysis and Design Considerations of a Load and Line Independent Zero Voltage Switching Full Bridge DC/oc Converter Topology”. IEEE Trans. P.E.,vol. 17,No. 5,Sept. 2002 [I71 Praveen K. Jian, Wen Kang, Harry Soin, Youhao Xi, “Load and Line Independent Zero Voltage Switching Full Bridge DCKX Converter Topalogy”, INTELEC’98, pp.22-29 [I81 Geery Moschopoulos, Praveen Jaik ‘ZVS PWM Full-Bridge Converters with Dual Auxiliary Circuits’: MTELEC‘OO, pp.574-581 [I91 Da Feng Weng, S.Yuvarajan, “A Novel Full-Bridge Zero-Voltage-Transition PWM DCYIK Converter Using a Saturable Reactor”, IAS’96, pp.1125-1132 [20] Neil A. Kammiler, “Full Bridge Phase Displaced Resonant Transition Circuit for Obtaining Constant Resonant Transition Current From 0” Phase Angle to ISP Phase Angle”, U.S. Patent No.: 5563775, Oct. 8, 1996 1211 Yunmaek Jane. M. M. Jovanovic. Yu-Mine Chane. “A New ZVf-PWM FukBridge Converter”, IEEE Trans.on P.E.:vol. 18, No.

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