Control and Modulation Scheme for a Cascaded H-Bridge Multi-Level Converter in Large Scale Photovoltaic Systems C.D. Townsend1 , T.J. Summers2 , R.E. Betz3 School of Electrical Engineering and Computer Science University of Newcastle, Australia, 2308 email:1
[email protected] 2
[email protected] 3
[email protected]
Abstract—Multi-level Cascaded H-bridge (CHB) converters are ideal for implementing large scale photovoltaic systems. The improved quality of the voltage waveforms, high efficiency and ability to employ multiple Maximum Power Point Tracking (MPPT) algorithms are just some of the advantages. In this paper a three-phase CHB converter supplied with photovoltaic arrays is considered. A control and modulation structure based on Model Predictive Control (MPC) is described. The scheme inherently controls the DC link voltages while also providing the ability to modify any of those voltages to meet MPPT requirements. This avoids the cost and added complexity of extra DC/DC converters that are typically required to keep the DC link voltages uniform. Simulation and experimental results are presented that confirm the correct operation of the proposed approach.
I. I NTRODUCTION Globally, grid connected photovoltaics (PV’s) are the fastest growing source of renewable energy [1]. Given this trend there is a need to optimise the converter topologies and control structures used to interface PV’s with the wider electrical network. The main goal of the converter is to optimise the transfer of energy into the grid while minimising switching losses and meeting grid connection standards. Fig. 1 shows the CHB converter configuration which is increasingly being utilised to integrate distributed energy sources [2], [3]. The main reasons for the choice of this topology are: (i) multiple DC links allows separation of the PV arrays so that multiple MPPT algorithms can optimise the extraction of power; (ii) various control algorithms exist which control the balancing of capacitor voltages for high level numbers [4]; and (iii) the level number can be increased to allow direct connection of the converter to medium voltages which avoids the lossy and expensive connection transformer [5], [6]. To optimise the transfer of energy the output characteristic of the PV panels must be considered. A PV array under constant irradiance exhibits an output voltage-current characteristic with a particular point that produces maximum output power. Various algorithms have been proposed to track this point [7]. This paper is primarily concerned with the voltage and power balancing techniques employed in the control and modulation strategies therefore details of the MPPT algorithm
978-1-4673-0803-8/12/$31.00 ©2012 IEEE
Figure 1.
Circuit configuration for a CHB converter PV application.
are not given. It is assumed that the Perturb and Observe (P&O) MPPT technique is utilised. Traditional modulation techniques for a CHB converter use Phase Shifted Carrier (PSC) PWM [2], [3], [8], [9]. However to achieve optimum harmonic performance this technique severely limits the allowable DC link voltages. Additional DC/DC converters are required to perform MPPT on the output voltages of the solar arrays. This means the use of multiple MPPT algorithms is not possible without the extra DC/DC conversion stage on each H-bridge module. The converter configuration within this paper does not employ DC/DC converters. Therefore for the MPPT algorithms to operate successfully the control strategy must be able to modify and independently track the required DC link voltages. The control and modulation techniques used in this paper are based on the instantaneous power concept [10] coupled with MPC current control and PWM [11], [12]. The deadbeat nature of the control loops means that their bandwidth is very high. In addition the calculations are numerically simple and ideal for digital implementation. Furthermore, it
3707
Figure 2. Block diagram of the converter control with MPC and zero sequence injection.
is relatively simple to incorporate a very high performance capacitor voltage balancing algorithm into the MPC scheme. This algorithm uses a section of the cost function to share the leg cluster voltage (defined as the total sum of each capacitor voltage in a phase-leg) across the individual Hbridge capacitors. It is possible to regulate the DC links at different target values which are dependent on the MPPT characteristics. This removes the need for DC/DC converters and therefore increases the efficiency and decreases the cost of the converter. This paper extends previous work by further developing an MPC scheme [13], [14] for PV applications. The scheme optimises the trade-off between harmonic performance and switching losses while inherently balancing the capacitor voltages even in the presence of per-cell power imbalances caused by shading and non-uniform manufacture of PV panels. Per-phase power imbalances are also addressed using a zerosequence injection technique [15]. II. C ONTROL S TRATEGY Fig. 2 shows a block diagram of the control algorithm presented in [13]. With respect to Fig. 2: Qr is the demanded reactive power, Pr is real power which is set to zero to calculate the reactive power current reference. is the constituent current vector associated with reiQ r active power. iPr is the constituent current vector associated with real power. vrleg is the target cluster voltage for each phase. vla,b,c are the measured cluster voltages for each phase. ir is the reference current vector. vrlim is the limited voltage vector generated by the deadbeat controller. isc is the measured converter current vector. Vdc1..27 are the measured capacitor voltages and is the measured system voltage vector. vg As can be seen from Fig. 2, the control is hierarchical, with the inner part of the structure executing a dead-beat
current controller and MPC cost function with the outer level responsible for the control of real and imaginary power. The ‘PQ’ block uses instantaneous power theory [10] to decompose the reactive power into its constituent reactive current component given by (1). The reactive power is developed by adding the demanded reactive power to the output of the PI controller, which acts on the difference between the demanded and measured reactive power. The addition of the demanded reactive power at the output of the PI controller results in a faster response time for the system under start-up conditions. The presence of integral gain is needed to correct the steady state error between the demanded and measured reactive power. iQ r =
S v∗g
(1)
The ‘Leg Voltage Control’ block uses the component of the current associated with real power to regulate the cluster voltages. The real power current reference is calculated via (2). (2) iPr = K1 vrleg − vaveleg − Ppv where K1 is a chosen constant, Ppv is the total power entering the converter via the solar arrays, Ppv = v pv,a1 × i pv,a1 + .. + v pv,aN × i pv,aN + .. + v pv,b1 × i pv,b1 + .. + v pv,bN × i pv,bN + .. + v pv,c1 × i pv,c1 + .. + v pv,cN × i pv,cN
(3)
and vaveleg is the average cluster voltage, vla + vlb + vlc (4) 3 Controlling the real power current reference regulates the average cluster voltage. An additional control mechanism is required to ensure that the total voltage is shared evenly between the phases. Zero sequence voltage injection is utilised in this paper to meet this requirement. This technique is outlined in Section III. The current controller is based on the popular dead-beat current controller often used in variable speed drive applications [12], [16]. The basic equations used to calculate the required output converter voltage are (5) and (6). vaveleg =
L k+1 ˆk (i − isc ) + vˆk+0.5 (5) g T r T k k k−0.5 iˆsc = ik−1 ) (6) sc + (vrlim − vg L where k ∈ I, T is the length of the control interval in seconds, ik−1 sc is the sampled instantaneous current vector at time k t = (k − 1) T , iˆsc is the instantaneous predicted current vector at time t = kT and ik+1 is the instantaneous reference current r vector at time t = (k + 1) T . As for the voltage nomenclature, vkrlim is the actual voltage vector applied during the interval from (k − 1) T → kT , vk+1 is the desired (or reference) voltage r
3708
vk+1 = r
vector that the controller applies from kT → (k + 1) T , vgk+0.5 on the direction of instantaneous power flow) that has not is the predicted instantaneous supply voltage vector at the already been switched in by the MPC scheme. The application midpoint of the control interval from kT → (k + 1) T , and of the residual voltage provides excellent current tracking is the measured instantaneous supply voltage at the performance and reduces the Total Harmonic Distortion (THD) vk−0.5 g midpoint of the control interval from (k − 1) T → kT . The ˆ of the converter current. symbol denotes a predicted value. The authors have proposed an improved model for the The MPC block integrates dead-beat current control equa- voltage balancing that calculates the value for Vcap,error [14]. tions with a penalisation of the voltage balancing and switch- This model is based around a sorting algorithm that penalises ing loss. The dead-beat controller aims to calculate a desired the inclusion of capacitors (that synthesise the output voltage) voltage vector to inject the energy produced by the PV which will subsequently have their voltages driven away from arrays into the grid. The purpose of the MPC block is to their target values. The improvement in the model comes from choose one switching combination per phase that produces the not only sorting the capacitor voltages, but also the difference desired voltage vector. The relationship between the switching between each capacitor voltage and its target value. The combinations and the corresponding voltage vectors will be Vcap,error value within the cost function can then be modulated defined as: based on the need for the evaluated capacitor to be switched in. This reduces the capacitor voltage ripple and the number app vk+1 = Vdc • Si (7) of switching transitions. Additionally, the algorithm allows for each capacitor voltage app where vk+1 is the applied voltage vector generated by the to be independently controlled. This is achieved by modifying switching states Si , for the interval from kT → (k + 1) T . the reference each capacitor voltage is compared against, Once the desired output voltages for each phase have within the cost function, to calculate the associated error. This been calculated in the dead-beat current controller the MPC ability facilitates the inclusion of multiple MPPT algorithms. block firstly evaluates the corresponding voltage vector for This allows each individual H-bridge to regulate its DC link each switching combination using (7). By comparing to the voltage to track the maximum power point associated with a desired output voltages calculated in the dead-beat controller, particular PV array. This makes the voltage balancing model combinations that produce a residual voltage greater than the ideal for PV applications. lowest capacitor voltage are disregarded. This evaluation is Remark 1: The inclusion of multiple MPPT algorithms performed by disregarding any combinations that do not satisfy within the cost functions essentially increases the number of the condition in (8). competing objectives. The importance placed on the objectives is controlled through choice of the cost function coefficients. ref app (8) n vk+1 − vk+1 < Vdc,min where Vdc,min is the minimum capacitor voltage within the phase-leg and vref k+1 is the reference voltage for that phase (calculated within the dead-beat controller) that the scheme needs to apply from kT → (k + 1) T . The remaining switching combinations are evaluated in an MPC cost function that includes heuristic models of the voltage balancing and switching loss characteristics. The form of the cost function is: error = α1 Vcap,error + α2 (SWtransitions )
(9)
where SWtransitions is the number of transitions from the currently applied switching combination to the evaluated combination and Vcap,error is a measure of how far the evaluated combination will drive the capacitor voltages either towards or further from their target value. In Fig. 2, information passed from the ‘MPC’ block to the ‘PWM Gen’ block includes the chosen switching combination and the residual voltage error between the voltage determined by the dead-beat controller and the voltage chosen by the MPC controller. The ‘PWM Gen’ block uses the residual error to calculate the required duty cycle to be applied to an appropriate bridge. The most appropriate bridge is determined by first sorting the capacitor voltages then selecting the Hbridge with the lowest voltage (or highest voltage depending
III. Z ERO S EQUENCE VOLTAGE I NJECTION The Zero Sequence Injection block in Fig. 2 is included to address power imbalances between the three phases of the converter. Grid connection standards often require the magnitude of the three phase currents to be equal under non-fault conditions, meaning that an equal amount of power can be delivered to each phase of the load. In practice shading effects and manufacturing tolerances cause an unequal amount of power to be developed by the PV arrays in each of the phases. By injecting a zero sequence voltage it is possible to exchange any excess energy between the phases without affecting any of the outer control loops [15]. The only disadvantage of this technique is the need to increase the voltage rating of the converter to allow sufficient voltage overhead for the zero sequence component. Drawing from standard instantaneous power theory the total desired power entering or leaving the converter is given by (10).
3709
Ptot = vα iα + vβ iβ
(10)
iα = iα p + iαq
(11)
where,
iβ = iβ p + iβ q
(12)
The three-phase power entering or leaving the converter (Ptot ) is split evenly between the phases so, Ptot ˆ ˆ + V0 I p cos (θap − α0 ) 3 2π Ptot ˆ ˆ R{Sb } = + V0 I p cos θap − α0 − 3 3 Ptot ˆ ˆ 2π R{Sc } = + V0 I p cos θap − α0 + 3 3
and,
R{Sa } =
iPr
= iα p + jiβ p
iQ r
= iαq + jiβ q
(13) (14)
iPr and iQ r are derived from the control scheme according to (1) and (2). Therefore by utilising a phase locked loop to predict the system voltage i.e. vα and vβ , we can calculate the total power entering or leaving the converter via (10). To address power imbalances a zero sequence voltage is imposed on each phase such that the voltages across the a, b and c phases are given by, 0
0
0
0
V a = V a +V 0
(27)
(28)
If we let R{Sa } = Pa∗ , R{Sb } = Pb∗ and R{Sc } = Pc∗ then (26) and (27) can be written as, Ptot = Vˆ0 Iˆp cos (θap − α0 ) 3 2π Ptot Pb∗ − = Vˆ0 Iˆp cos θap − α0 − 3 3 Pa∗ −
(15)
(29)
(30)
Using the double angle formula (30) can be expressed as,
V b = V b +V 0 0
(26)
0
(16)
V c = V c +V 0
(17)
V 0 = Vˆ0 ∠α0
(18)
2π Ptot ˆ ˆ 2π = V0 I p cos (θap − α0 ) cos + sin (θap − α0 ) sin 3 3 3 (31) Dividing (31) by (29) gives,
Pb∗ −
where,
Pa∗ − P3tot
The apparent power per-phase will be given by, 0
Sa = V a I ∗ap 0
Sb = V b I ∗bp
Pb∗ − P3tot
(19)
2π cos (θap − α0 ) cos 2π 3 + sin (θap − α0 ) sin 3 = cos (θap − α0 ) 2π 2π + tan (θap − α0 ) sin (32) = cos 3 3
Therefore, (20)
0
Sc = V c I ∗cp
(21)
tan (θap − α0 ) =
I ∗p
where is the complex conjugate of the positive sequence current vector, I p = Iˆp ∠θap
= (22)
3 2 ∗ Ptot + 1 Pa − 3 √ 3
2π 3
P Pb∗ − tot 3
(33)
By substituting (34) into (29) the required zero sequence voltage magnitude is given by (35). Vˆ0 =
Vˆ0 2π ˆ ˆ R{Sc } = V I p cos (θap − θa ) + cos θap − α0 + 3 Vˆ (25) where θa is the angle of the positive sequence voltage and Vˆ is the peak magnitude of the positive sequence voltage.
sin
− cos 2π
So the required zero sequence angle is given by (34). ∗ Ptot Pb − 3 + 1 2 P Pa∗ − tot √3 (34) α0 = θap − arctan 3
(23)
Vˆ0 2π R{Sb } = Vˆ Iˆp cos (θap − θa ) + cos θap − α0 − 3 Vˆ (24)
P Pa∗ − tot 3
The real power in each phase is the real part of (19), Vˆ0 R{Sa } = Vˆ Iˆp cos (θap − θa ) + cos (θap − α0 ) Vˆ
P Pb∗ − tot 3
Pa∗ − P3tot Iˆp cos(arctan(F))
where,
3710
2 F=
P Pb∗ − tot 3 P Pa∗ − tot 3
√ 3
+1
(35)
For a PV application the desired extra power entering or leaving a particular phase-leg is made up of two components. One being the differential power entering the DC links via the PV arrays and the second being the power required to regulate the cluster voltages to their target value (differences in these voltages will arise naturally due to variation in losses between phase-legs). This observation is formalised through (36). Pj∗ = Ppv, j − Ppv,ave + K2 vl j − vaveleg (36) where the power entering the jth phase-leg via the PV panels is given by,
Ppv, j
= v pv, j1 × i pv, j1 + .. + v pv, jN × i pv, jN
(37)
and, Ppv,ave =
Ppv,a + Ppv,b + Ppv,c 3
(38)
IV. S IMULATION RESULTS A simulation of the MPC scheme has been implemented in Saberr , and is very accurate and comprehensive. It completely simulates the H-bridge phase legs, the start-up sequencing and all control loops. It is a multi-mode simulation, with the control implemented digitally with the timing as per the experimental system. The key control algorithms are implemented as ‘C’ DLLs, and this code is also used in the actual experimental system. Fig. 3 confirms the correct operation of the proposed control scheme and voltage balancing technique. These simulation results depict the condition where the PV arrays are initially supplying equal power, the total power being delivered to the grid is 3.4 kW. During this simulation the converter is also absorbing 2 kvar inductive, which demonstrates the dual capability of the control scheme and converter to manipulate real and reactive power. At 1.0 s a change in irradiance levels is simulated. The power being supplied from each phase-leg after 1.0 s is distributed in the following manner: Pa pv = 1350 W, Pb pv = 1130 W and Pc pv = 900 W. A power imbalance between the individual H-bridge cells is also simulated with the total power produced by the phase-leg distributed in the follow0.85 1.2 ing manner: Pj1 = 0.8 9 Pj pv , Pj2 = 9 Pj pv ... , Pj9 = 9 Pj pv . The bottom plot demonstrates an excellent current tracking performance while the middle plot shows the nine phase ‘a’ capacitor voltages which are successfully sharing the leg cluster voltage. The capacitor voltages converge to their MPPT references within four or five cycles. It is also possible to see that the output converter voltages (top plot) are modified at 1.0 s to include a zero sequence component that keeps the magnitude of the converter currents equal and balances the cluster voltages. It is now possible to quantify the trade-off between harmonic performance and switching losses for the control scheme developed in this paper. This can be done in various ways however many commercial converters use the switching
Figure 3. Simulation waveforms - Top plot: Output converter voltages, Middle plot: Nine phase ‘a’ capacitor voltages, Bottom plot: Converter currents.
frequency per component as the basis for their design choice [17], [18]. This trade-off can be expressed by (39). performance =
1 THD × fsw
(39)
where fsw is the switching frequency per component and THD is the total harmonic distortion of the converter current (given in (40)), for the respective modulation scheme. q 2 + I 2 + ... + I 2 Ih2 h3 hp THD = (40) I1 where, Vhk (41) kωo L where ωo is the system frequency, L is the value of the connection inductance, Vhk is the magnitude of the kth multiple voltage harmonic and the multiple of the system frequency p is chosen to be sufficiently high so as to consider any significant harmonic components present in the converter current waveforms. Fig. 4 shows the performance of the MPC scheme when the total power being delivered to the grid is again 3.4 kW. The power being supplied from each phase-leg after 0.3 s is distributed in the following manner: Pa pv = 1350 W, Pb pv = 1130 W and Pc pv = 900 W. The number of average switching transitions occurring on the switching components in phase ‘a’ is shown in the middle upper plot. For the 1.7 s period the average number of switching transitions is 524. The THD of the converter current is 3.0 %. Remark 2: In the simulation results depicted in Fig. 4 the proportional gain (K1 ) has been chosen such that the
3711
Ihk =
control loop which regulates the average cluster voltage (by controlling total real power) has a low bandwidth. This can cause over-shoot in the response of the cluster voltages when a sudden per-phase power imbalance occurs (such as that simulated at 0.3 s in Fig. 4). However, a low bandwidth outer loop also reduces any adverse control interactions with the inner loop which modifies the zero sequence voltage to achieve per-phase power balance. The bandwidth of the outer loop may be increased to improve the response to fast transient changes in the real power entering the converter (via the solar arrays). However significant changes in the solar irradiance which the PV’s are subject to, and hence the real power entering the converter, tend to occur on a slow scale compared to the dynamics associated with the current controller. Therefore in practice the bandwidth of the outer loop that controls the total power entering or leaving the converter can be kept quite low. n The average number of transitions (524) that was shown to occur on each switch is only slightly higher than the number of transitions obtained in [14] when the same converter and modulation strategy is used only for Var compensation i.e. without the PV arrays connected to the DC links. This demonstrates that even when the converter is compensating for dynamic real power applications the trade-off between harmonic performance and switching losses for the MPC scheme remains excellent. Traditionally the best trade-off between harmonic performance and switching loss has been achieved using PSCPWM. By developing a simulation that implements the PSCPWM scheme described in [19], it is possible to calculate the theoretical values of total harmonic distortion which can be achieved using this modulation strategy. It was noted that the THD of the converter current, when utilising the scheme described in this paper, was measured at 3.0%. To equal this harmonic performance for the same operational condition, the PSC-PWM scheme requires a carrier frequency of 200 Hz. For PSC-PWM each switching device will undergo two switching transitions per period of the carrier waveform, this is due to the fact that PSC-PWM switches in each H-bridge during every period of the carrier waveform. This means the total switching transitions per component for a 1.7s period of time will be 850. The MPC scheme is capable of reducing the number of switching transitions to 524, with a THD of 3.0 %. This 1 = 1081µ, corresponds to a performance rating of 3.0×(524/1.7) whereas the product for the PSC-PWM will be 1 3.0×2∗200 = 833µ. Therefore the MPC scheme has a superior performance than existing PSC-PWM schemes. V. E XPERIMENTAL R ESULTS In order to validate the simulation studies, the ‘C’ code dynamic-link libraries used in the Saber simulation were slightly modified for operation in the real-time control environment of a low voltage (415 VAC) 19-level H-bridge Converter.
Figure 4. Simulation waveforms - Top plot: Average number of switching transitions on leg ‘a’ switching devices, Middle lower plot: Converter cluster voltages, Middle lower plot: Nine phase ‘a’ capacitor voltages, Bottom plot: Converter currents.
The converter used to produce the experimental results is a scaled model of an 11kV converter. It has 9 H-bridges per phase, with each H-bridge designed with MOSFET power devices. The phase legs are Wye connected. A block diagram of the experimental system appears in Fig. 5. One can see that it is implemented as a multi-processor system, with individual processors implementing the control for each of the phase legs. These phase leg processors are responsible for switching in the desired capacitors and applying the PWM. The desired switching vectors which are passed to the phase leg controllers (via an optical fibre interface) are developed in the MPC algorithm, which is implemented in a central Pentium PC. The following experimental results were obtained when two of the H-bridges on phase ‘a’ of the converter are supplied by DC current sources, which for these purposes emulate PV arrays. In these experimental results the system was operated with a supply voltage of 140Vl−l RMS. It can be seen in Fig. 6 that the system achieves good current tracking performance with tight control over the capacitor voltages. The capacitors that are supplied by the DC sources are being regulated at two different voltage levels
3712
Figure 7. Experimental waveforms showing the transient performance of the control scheme under a significant step change in real power - Top plots: Nine phase ‘a’ capacitor voltages, Middle plot: Measured and reference converter currents, Bottom plot: Alpha and beta real power current reference. Figure 5.
Block diagram of the 415-V 10-kVA experimental system.
supplying power into the grid instead of absorbing power to supply the losses. For this condition the two DC sources are current controlled to provide 20 W of power each. It can be seen that balancing of the capacitor voltages is achieved within 5 cycles of the transient event. VI. C ONTRIBUTIONS & C ONCLUSIONS
Figure 6. Experimental waveforms when DC sources supplying a small amount of real power - Top plot: Nine phase ‘a’ capacitor voltages, Middle plot: Measured and reference converter currents, Bottom plot: Alpha and beta real power current reference.
to confirm the correct operation of the voltage balancing scheme when manipulating real power. This also confirms that multiple MPPT algorithms can be operated within a practical system. The bottom plot shows the alpha and beta real power components of the converter currents, it can be seen that the alpha magnitude is significantly reduced due to the DC sources providing the majority of required real power. The two DC sources are current controlled to provide 10 W of power each. Under these conditions this equates to the majority of losses within phase ‘a’ being supplied by the two DC sources. Fig. 7 demonstrates the transient performance of the control scheme. Initially there is no real power being supplied from the DC sources. At approximately 7.1 s the DC sources are turned on. It can be seen that the alpha real power current reference undergoes a 180◦ phase shift signifying that phase ‘a’ is now
This paper presents a control scheme for a cascaded Hbridge converter which achieves simultaneous optimisation of current reference tracking and voltage balancing when interfacing PV arrays to the grid. The MPC algorithm has demonstrated a capability to accommodate multiple MPPT algorithms by dynamically tracking the required voltage references for each of the H-bridge capacitors. The scheme provides a superior (when compared to PSC-PWM) harmonic performance trade-off with the switching losses [14] and avoids the cost, loss in efficiency and added complexity of the DC/DC converters within the PV to grid interface. Simulation and experimental results showing the performance of the algorithms have been presented. R EFERENCES [1] “Renewable energy policy network for the 21st century, renewables 2010 global status report,” 2010. [2] S. Rivera, S. Kouro, B. Wu, J. Leon, J. Rodriguez, and L. Franquelo, “Cascaded h-bridge multilevel converter multistring topology for large scale photovoltaic systems,” in Industrial Electronics (ISIE), 2011 IEEE International Symposium on, pp. 1837 –1844, june 2011. [3] E. Villanueva, P. Correa, J. Rodriguez, and M. Pacas, “Control of a single-phase cascaded h-bridge multilevel inverter for grid-connected photovoltaic systems,” Industrial Electronics, IEEE Transactions on, vol. 56, pp. 4399 –4406, nov. 2009. [4] T. Yoshii, S. Inoue, and H. Akagi, “Control and performance of a medium-voltage transformerless cascade pwm statcom with starconfiguration,” in Industry Applications Conference, 2006. 41st IAS Annual Meeting. Conference Record of the 2006 IEEE, vol. 4, pp. 1716 –1723, 2006.
3713
[5] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodriguez, M. Pe andrez, and J. Leon, “Recent advances and industrial applications of multilevel converters,” Industrial Electronics, IEEE Transactions on, vol. 57, pp. 2553 –2580, aug. 2010. [6] H. Iman-Eini, J.-L. Schanen, S. Farhangi, and J. Roudet, “A modular strategy for control and voltage balancing of cascaded h-bridge rectifiers,” Power Electronics, IEEE Transactions on, vol. 23, no. 5, pp. 2428 –2442, 2008. [7] A. Thenkani and N. Senthil Kumar, “Design of optimum maximum power point tracking algorithm for solar panel,” in Computer, Communication and Electrical Technology (ICCCET), 2011 International Conference on, pp. 370 –375, march 2011. [8] R. Naderi and A. Rahmati, “Phase-shifted carrier pwm technique for general cascaded inverters,” Power Electronics, IEEE Transactions on, vol. 23, pp. 1257 –1269, may. 2008. [9] C. Govindaraju and K. Baskaran, “Efficient sequential switching hybridmodulation techniques for cascaded multilevel inverters,” Power Electronics, IEEE Transactions on, vol. 26, pp. 1639 –1648, june 2011. [10] H. Akagi, E. H. Watanabe, and M. Aredes, Instantaneous Power Theory and Application to Power Conditioning. John Wiley and Sons, 2007. [11] P. Cortes, A. Wilson, S. Kouro, J. Rodriguez, and H. Abu-Rub, “Model predictive control of cascaded h-bridge multilevel inverters,” in Power Electronics and Applications, 2009. EPE ’09. 13th European Conference on, pp. 1–9, Sept. 2009. [12] R. Betz, B. Cook, and S. Henriksen, “A digital current controller for three phase voltage source inverters,” Conference Record of the IEEEIAS Annual Meeting, pp. 722–729, New Orleans, Oct. 1997. [13] C. Townsend, T. Summers, and R. Betz, “Multi-goal heuristic model predictive control technique applied to a cascaded h-bridge statcom,” Power Electronics, IEEE Transactions on, vol. PP, no. 99, p. 1, 2011. [14] C. Townsend, T. Summers, and R. Betz, “Optimisation of switching losses and harmonic performance using model predictive control of a cascaded h-bridge multi-level statcom,” in Energy Conversion Congress and Exposition (ECCE), 2011 IEEE, pp. 3159 –3166, sept. 2011. [15] T. Summers, R. Betz, and G. Mirzaeva, “Phase leg voltage balancing of a cascaded h-bridge converter based statcom using zero sequence injection,” in Power Electronics and Applications, 2009. EPE ’09. 13th European Conference on, pp. 1 –10, sept. 2009. [16] D. G. Holmes and D. A. Martin, “Implementation of a direct digital predictive current controller for single and three phase voltage source inverters,” in Industry Applications Conference, 1996. Thirty-First IAS Annual Meeting, IAS ’96., Conference Record of the 1996 IEEE, vol. 2, (San Diego, CA), pp. 906–913, Oct. 1996. [17] C. Davidson and G. de PrÈville, “The future of high power electronics in transmission and distribution power systems,” in Power Electronics and Applications, 2009. EPE ’09. 13th European Conference on, pp. 1–14, Sept. 2009. [18] R. Vargas, U. Ammann, and J. Rodriguez, “Predictive approach to increase efficiency and reduce switching losses on matrix converters,” Power Electronics, IEEE Transactions on, vol. 24, no. 4, pp. 894 –902, 2009. [19] H. Akagi, S. Inoue, and T. Yoshii, “Control and performance of a transformerless cascade pwm statcom with star configuration,” Industry Applications, IEEE Transactions on, vol. 43, pp. 1041 –1049, jul. 2007.
3714
