Cost of Ownership for Future Lithography Technologies

Cost of Ownership for Future Lithography Technologies Andrew J. Hazelton*a, Andrea Wüestb, Greg Hughesb, Lloyd C. Littb, Frank Goodwinb a

Nikon Corporation, Fuji Bldg., 2-3, Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-8331 Japan; b SEMATECH, 255 Fuller Road, Suite 309, Albany, NY, 12203, USA ABSTRACT

The cost of ownership (COO) of candidate technologies for 32 nm and 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. Results show lithography COO for leading edge layers will increase by roughly 50% from the 45 nm to the 32 nm half-pitch nodes. Double patterning and extreme ultraviolet lithography (EUVL) technologies have roughly the same COO under certain conditions. For 22 nm half-pitch nodes, EUVL has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst case EUVL mask cost assumptions. Sensitivity studies of EUVL COO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. In spite of these higher costs, total lithography costs for 32 nm and 22 nm half-pitches remain within reach of the Moore’s Law trend. Finally, the COO of 450 mm lithography is calculated and shows the expected cost reduction is between 0% and 15%. Keywords: Cost of ownership, lithography, double patterning, EUVL, mask costs

1.

INTRODUCTION

Extending lithography to the 32 nm and 22 nm half-pitches requires the introduction of new lithography technologies, such as EUVL or high index immersion, or new techniques, such as double patterning. All of these techniques introduce significant changes into the single exposure immersion lithography process used for the 45 nm half-pitch node. Therefore, cost per wafer is a concern. Certainly, the lowest cost technology should be a priority, but an additional requirement is that the technology should enable the cost reduction trend predicted by Moore’s Law. In simple terms, this trend says the cost per device function (e.g., bit of memory or processing capability), should go down by half every 2 years. As the cost of the leading edge lithography technology for the 32 nm and 22 nm half-pitch nodes is forecasted to increase dramatically, the cost per function must be considered to understand whether this increase in cost represents an end to the economic scaling of Moore’s Law. Increasing the wafer size to 450 mm has been proposed as another option to maintain the cost scaling of Moore’s Law. The expectation is that the wafer size change will reduce costs fabwide, and, in fact, the cost reductions for nonlitho processes are expected to be greater than for litho. Nonetheless, some cost reduction for litho processes is anticipated as well. This work will investigate the costs of future lithography technologies and aim to identify parameters for assuring these costs meet the cost per function trend.

2.

CANDIDATE TECHNOLOGIES FOR FUTURE LITHOGRAPHY

The single exposure 193 nm water immersion lithography solution used for 45 nm half-pitch lithography does not have sufficient resolution for the 32 nm half-pitch. In the past, several options were considered for 32 nm half-pitch lithography, but currently, some form of double patterning (DPL) is the leading candidate. In DPL, the desired pattern is split into two separate pieces and exposed separately on a single layer of the wafer. In the process called litho-etch-lithoetch (LELE), after the first exposure, the wafer is developed and the developed image is used to etch the pattern into a hardmask stack. The wafer is then recoated with photoresist, and the second pattern is exposed. The second pattern is also transferred into the hardmask. Finally, the hardmask is used to transfer the pattern into the underlying layer. Litho*

[email protected]; phone +81-3-3216-1004; www.nikon.co.jp Lithography Asia 2008, edited by Alek C. Chen, Burn Lin, Anthony Yen, Proc. of SPIE Vol. 7140, 71401Q © 2008 SPIE · CCC code: 0277-786X/08/$18 · doi: 10.1117/12.804711

Proc. of SPIE Vol. 7140 71401Q-1 2008 SPIE Digital Library -- Subscriber Archive Copy

litho-etch (LLE) is a variation of DPL in which the first image is fixed in the photoresist before recoating and the second exposure, thus eliminating an intermediate etching step. In spacer DP, the wafer is exposed only once with the primary pattern. After development and etch, sidewalls are conformally deposited on all sides of the pattern. These sidewalls can then be used as a mask for subsequent etching, and a trim pattern is exposed to remove the line ends. Alternatively, another material can be deposited in the spaces between the sidewalls, the sidewalls are then removed, and the second material is used as the mask for etching. EUVL replaces the ArF light source of current leading edge tools with a 13.5 nm light source. This creates a number of new requirements for exposure tool technology, but allows imaging of 32 nm half-pitches with k1 factors above 0.5, which reduces the requirements for sub-resolution features on the mask. High index immersion was previously a leading candidate for 32 nm lithography, but delays in material development have made it impossible to meet the 32 nm half-pitch single patterning timing. Thus, it has been removed from our consideration for 32 nm. For 22 nm half-pitches, many of the technology choices are basically the same. The three variations of DPL (LELE, LLE, spacer) are still considered. In addition, DPL using high index immersion lithography is an option. Single patterning with EUVL can be extended to the 22 nm half-pitch, but the tool requires a higher lens NA and possibly more complicated reticle designs. Candidate technologies and process flows are shown in Fig. 1 below. Deposit hardmask(s)

Coat, expose, develop

ArFi SE Etch hardmask, Strip resist


Freeze resist


DPL

LELE (Line) Freeze Etch hardmask

Deposit spacer, Remove hardEtch back spacer mask lines

Spacer EUV Imprint

Imprint

For all flows at end: Etch hardmask, Strip resist, Etch pattern, Strip hardmask

Fig. 1. Candidate technologies for 32 nm, 22 nm half-pitch lithography (The above description is an example only and should not be taken as instructions for using our device in a particular manner.)

3.

COO CALCULATION METHOD

The total layer cost including lithography, deposition, etching, and other process steps was calculated for each of the technology options. Typically, lithography COO includes the capital cost of the lithography cell equipment, consumables costs including photoresist, reticle costs, and labor and facilities costs necessary to install and support the equipment.1 Lithography costs were calculated using a simplified version of the SEMATECH cost of ownership model. Non-lithography process costs were obtained from internal cost models provided by the International SEMATECH Manufacturing Initiative (ISMI). Two models were used to estimate tool prices. In the first, historical data of tool price vs. information rate 2

⎛ NA ⎞ (effectively transistors per hour expressed as TP300 mm −equivalent ⎜ ⎟ ) were extrapolated to the 32 nm and 22 nm ⎝ λ ⎠

Proc. of SPIE Vol. 7140 71401Q-2

technologies. The second used historical data of leading edge tool prices vs. time.2 These models gave prices that generally agreed. Resist costs were estimated based on current costs and rough estimates for EUVL resists. Reticle costs were calculated by SEMATECH based on predicted increases in write and inspection times and tightened specifications for future generation masks.3 These mask costs are termed the rigorous mask model. In followup conversations with many device manufacturers, unrealistic mask costs were identified as a possible issue with our COO conclusions. A second set of mask costs was introduced based on the general opinions of several device manufacturers. These are termed the conventional wisdom (CW) mask model. Generally speaking, the CW model uses a 50% increase in mask cost per generation, with an added 50% premium when going to DPL. In addition to adjusting the future technology mask costs, in the CW model, the second exposure in the spacer process is assumed to be a KrF exposure. In comparing the different technologies, the following was assumed: 1.

All technologies are equally reliable

2.

All technologies support equal yield

These assumptions may not be realistic, but there is currently no quantitative basis to justify other assumptions. The parameters used for the lithography COO model are shown in Tables 1 and 2 below. Table 1. Parameters for 32 nm half-pitch lithography COO model 45 nm HP ArFi SE throughput (wph)

32 nm HP ArFi DPL LLE Spacer

LELE

EUVL

125

180

180

180

50

tool price

$40M

$49M

$49M

$49M

$54M

consumables (/year)

$3.4M

$4.6M

$4.6M

$4.6M

$3.5M

reticle cost per layer (rigorous model)

$200k

$584k

$584k

$466k

$178k

reticle cost per layer (CW model)

$200k

$400k

$400k

$240k

$300k

Table 2. Parameters for 22 nm half-pitch lithography COO model 45 nm HP ArFi SE throughput (wph)

125

22 nm HP

LELE 200

ArFi DPL LLE Spacer 200 200

Hi ArFi DPL LELE

EUVL

135

100

tool price

$40M

$52M

$52M

$52M

$53M

$89M

consumables (/year)

$3.4M

$5.0M

$5.0M

$5.0M

$4.7M

$6.5M

reticle cost per layer (rigorous model)

$200k

$1166k

$1166k

$752k

$1176k

$252k

$200k

$600k

$600k

$360k

$600k

$450k

reticle cost per layer (CW model)


4.

RESULTS

Layer COO was calculated as described above. Two cases were considered: mask usage of 1000 wafers/mask to reflect a lower volume logic process (less than about a half million parts produced) and mask usage of 20,000 wafers/mask to reflect a higher volume memory application (more than 10 million parts). Results are shown in Figs. 2–5 below. Reticle Clean Etch Metrology Deposition Litho

300%

250%

200%

Reticle Clean Etch Metrology Deposition Litho

200% 180% 160% 140% 120% 100%

150%

80% 100%

60% 40%

50%

20% 0%

0% 45 nm ArFi SE (125 wph)

32 nm ArFi DPL LELE (180 wph)

32 nm ArFi DPL Freeze (180 wph)

32 nm ArFi DPL Spacer (180 wph)

45 nm ArFi SE (125 wph)

32 nm EUVL (50 wph)




32 nm EUVL (50 wph)

Fig. 2. 32 nm layer costs with 1000 wafers/mask (rigorous model on the left, CW model on the right) 200% 180% 160% 140%

180%


160% 140% 120%

120%


100%

100% 80%

80%

60%

60%

40%

40%

20%

20% 0%





32 nm EUVL (50 wph)





32 nm EUVL (50 wph)

Fig. 3. 32 nm layer costs with 20,000 wafers/mask (rigorous model on the left, CW model on the right) At the 32 nm half-pitch node with 1000 wafers/mask, the COO is largely determined by the mask cost. In the rigorous model, EUVL is a clear winner, but the increase in EUVL mask cost and decrease in DPL mask costs in the CW model make the final result not so clear. For 20,000 wafers/mask, the layer cost for double patterning processes is about 40–50% higher than current ArF immersion layer costs. In addition, EUVL with a 50 wph throughput is competitive with DPL processes. The benefit of using a lower cost process for the second spacer exposure is clear as well.


300%

500% 450% 400% 350%


250%

200%


300% 250%

150%

200% 100%

150% 100%

50%

50% 0%





22 nm HI ArFi DPL LELE (135 wph)

22 nm EUVL (100 wph)







Fig. 4. 22 nm layer costs with 1000 wafers/mask (rigorous model on the left, CW model on the right) 200%

250%

200%


180% 160% 140%

150%


120% 100%

100%

80% 60%

50%

40% 20%

0%













Fig. 5. 22 nm layer costs with 20,000 wafers/mask (rigorous model on the left, CW model on the right) At the 22 nm half-pitch node for 1000 wafers/mask, EUVL is once again the lowest cost when the rigorous mask model is applied. Using the CW model, EUVL still has a significant advantage over most technologies, but the spacer process incurs the lowest cost due to the low cost process for the second exposure. For 20,000 wafers/mask, EUVL cost the least using the rigorous mask model, but with the CW model, EUVL is about the same cost as DP processes.

5.

EUVL SENSITIVITY ANALYSIS

For EUVL, there is considerable uncertainty whether the process technology can meet specifications for throughput, uptime, consumable costs, reticle defects, and other requirements. We investigated the sensitivity of EUVL COO to these cost-related performance areas to better understand the required performance parameters. Mask cost assumptions were addressed in the previous section with the rigorous and CW models; consumables are beyond the scope of this


paper. Therefore, we investigated the effects of throughput and uptime on the layer cost. The results are shown in Figs. 6 and 7 below.

Normalized Cost per wafer (vs. ArFi DP LELE)

1.7 32 nm EUVL (rigorous)

1.6

32 nm EUVL (CW )

1.5

ArFi DPL LELE

1.4

22 nm EUVL (rigorous)

1.3

22 nm EUVL (CW )

1.2 1.1 1.0 0.9 0.8 0.7 20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

110.0

EUVL Throughput (wph)

Fig. 6. Sensitivity of EUVL layer cost to exposure tool throughput 3.0

Normalized Cost per wafer (vs. ArFi DPL LELE, 70% Uptime)

32 nm EUVL (rigorous) 32 nm EUVL (CW) ArFi DPL LELE 22 nm EUVL (rigorous)

2.5

22 nm EUVL (CW)

2.0

1.5

1.0

0.5 0%

10%

20%

30%

40%

50%

60%

70%

EUVL Uptime

Fig. 7. Sensitivity of EUVL layer cost to exposure tool uptime Under the rigorous mask cost assumptions, EUVL with a throughput of around 40 wph is sufficient to match the lithography cost of DPL at both the 32 nm and 22 nm half-pitch nodes. Using the CW mask costs, throughputs of 50 wph (32 nm) and 70 wph (22 nm) are required to match the DPL costs. For uptime (assuming throughput as described in Tables 1 and 2 and assuming a DPL available production time, including idle and engineering times, of 70%), EUVL


with rigorous mask model assumptions can match the layer cost with an uptime of around 35%. Under other conditions, the uptime needs to be similar to DPL to achieve the same layer costs.

6.

OVERALL DEVICE COST TREND

Traditionally, Moore’s Law dictates a reduction of cost per function of around 30%–35% per year. These cost reductions typically come from device design improvements, better yield, miniaturization, and productivity gains. Since lithography typically affects the latter two items, we target a lithography cost reduction of 17% per year to meet the requirements of Moore’s Law. To see if the current lithography costs support this trend, the lithography cost for all layers of a representative DRAM device was calculated. This device contains five critical layers, seven middle layers, and 22 rough layers at the 32 nm half-pitch and eight critical layers, eight middle layers, and 19 rough layers for the 22 nm half-pitch. Mask and reticle costs for the non-critical layers were estimated based on current costs. The CW model was used for critical mask costs. The resulting total lithography costs were then normalized by the transistor size of the node. For these purposes, the transistor size was estimated as proportional to the resolution squared. The end result, relative lithography cost per function, is shown in Fig. 8. 1.2

Relative Cost (vs. 45 nm hp)

1

LELE, Freeze

EUV

LELE, Freeze

0.8

Spacer

Spacer

0.6

EUV

0.4

20,000 wafers / mask 0.2

45 nm

32 nm

22 nm

Fig. 8. Total lithography cost per function for future technologies (20,000 wafers/mask) These results show that the total lithography cost is a little higher than the trend for 32 nm half-pitch devices, but can be close to the target cost if EUVL is adopted for 22 nm half-pitch lithography.


7.

450 MM LITHOGRAPHY COSTS

A wafer size transition from 300 mm to 450 mm has been proposed as a way to reduce device costs in the future. Two of the underlying assumptions for 450 mm wafer cost reductions are as follows: •

Tool cost ≤ 1.3 times 300 mm tool costs

•

Wafer output same as 300 mm output

With these and a few other assumptions, the expectation is a 30% cost reduction per die. We investigated the cost reduction for lithography using our current COO model. First, we assumed tool price is correlated to the die throughput assuming the same lithography technology. In this case, a tool with the same die throughput as 300 mm wafers should have the same price, and a tool with the same wafer throughput would incur 1.55 times the tool price. Because consumable costs are proportional to the number of exposures, they are the same for a tool with the same die throughput and about 2.2 times higher for a tool with the same wafer throughput. In addition, the reticle lifetime is largely determined by the product run (i.e., number of die); consequently, the reticle cost per die remains constant in the transition from 300 mm to 450 mm wafers. Our assumptions are summarized in Table 3. Table 3. Parameters for the 450 mm lithography COO model

units

Relative Throughput

wph

Relative tool price Relative consumables

/wafer

300 mm

450 mm (same die TP)

450 mm (same wafer TP)

1

0.45

1

1

1

1.55

1

1

2.2

It should be noted that simply scaling current lithography tools to achieve the same wafer throughput for 450 mm wafers is unrealistic. This case is shown only to define a reasonable bound on the COO. The COO for these three cases is calculated and shown in Fig. 9. As expected, since the tool price, reticle costs, and consumables costs are the same for the same die throughput, the die COO is the same, and the wafer COO is roughly 2.25 times. In the same wafer throughput case, the COO contribution from the tool price improves, but the consumables and reticle costs per die are the same; therefore, the die COO drops by only about 10%–15%. This cost reduction is less than the target, but greater reductions in other process costs are expected. More study of 450 mm wafer COO is required to draw reasonable conclusions about its cost merits.


2.5 Wafer CoO Die CoO 2

1.5

1

0.5

0 300 mm

450 mm Same die TP

450 mm Same wafer TP

Fig. 9. 450 mm wafer COO

8.

CONCLUSIONS

In this paper, a comprehensive cost of ownership model including deposition, etching, and other process costs was presented for 32 nm and 22 nm half-pitch lithography technology. Based on these results, comparison charts for mask usages of 1000 wafers/mask and 20,000 wafers/mask were shown. These results show single layer, leading edge costs for the 32 nm half-pitch node will be approximately 1.5 times higher than current ArF immersion layer costs. In addition, LLE using resist freeze processes offers about a 10% cost reduction over LELE processes. EUVL is shown to be competitive with DPL processes under different mask cost assumptions at a throughput of 50 wph. For the 22 nm half-pitch node, EUVL has a significant cost advantage over other technologies. Under certain mask cost assumptions, however, DPL is competitive with EUVL. EUVL COO sensitivity to throughput and uptime was calculated, showing that under certain mask cost assumptions, lower throughput or uptime may be acceptable. Because these analyses are very sensitive to mask cost assumptions, more study is required for accurate results. The total lithography cost was calculated for all layers of 45 nm, 32 nm, and 22 nm DRAM devices. These results show that the 32 nm lithography costs are slightly higher than the Moore’s Law trend, but EUVL at 22 nm is in line with the trend. This suggests lithography will continue to be affordable under many scenarios. Expected lithography COO under two scenarios for 450 mm wafer throughput was also calculated. These results show 450 mm lithography COO reductions are between 0% and 15%. Since other processes are expected to contribute greater cost reductions, it may still be possible to achieve the overall 30% cost reduction target of the 450 mm wafer transition.

9.

ACKNOWLEDGMENTS

The authors would like to thank Obert Wood, Harry Levinson, Paul Ackmann (AMD), Céline Lapeyre (CEA-LETI Minatec), Will Conley (Freescale), Eric Panning (Intel), Gary Zhang (Rohm and Haas), Rob Crowell (TEL), Hiroyuki Mizuno (Toshiba), Dennis Fandel, Jacque Georger, Chawon Koh, Bob Rulliffson, Phil Seidel, Larry Smith, Robert Wright (SEMATECH), and Kazuaki Suzuki (Nikon Corporation)


SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

REFERENCES 1

International Technology Roadmap for Semiconductors, 2007 Update, Lithography chapter. www.itrs.org Seidel, Phil, “EUV Lithography Cost-of-Ownership Considerations,” 2007 EUVL Symposium, Sapporo, Japan. October 29, 2007. 3 Hughes, Greg, “Mask and wafer cost of ownership from 65 to 22nm half-pitch nodes,” to be published in Proc. of SPIE Vol. 7028, 7028-60 (2008). 2
