BST09. Course DEVICES & CIRCUITS. Chapter: CMOS. Michael E. Auer. Source
of figures: Jaeger/Blalock: Microelectronic Circuit Design,. McGraw-Hill ...
DEVICES & CIRCUITS - CMOS
Course DEVICES & CIRCUITS Chapter: CMOS Michael E. Auer
Source of figures: Jaeger/Blalock: Microelectronic Circuit Design, McGraw-Hill
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Course Content
Introduction and Milestones in Microelectronics Solid-state Electronics Solid-state Diodes and Diode Circuits Field-effect Transistors (FET) Bipolar Junction Transistors (BJT) Introduction to Digital Microelectronics NMOS Logic Circuits Complemetary MOS Logic (CMOS) Bipolar Logic Circuits Semiconductor Memories Application Specific Integrated Circuits (ASIC)
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Technology •
Complementary MOS, or CMOS, needs both PMOS and NMOS devices for the logic gates to be realized
•
The concept of CMOS was introduced in 1963 by Wanlass and Sah, but it did not become common until the 1980’s as NMOS microprocessors were dissipating as much as 50 W and an alternative design technique/technology was needed
•
Michael E.Auer
CMOS dominates digital IC design today
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
MOTOROLA‘s PowerPC 620 (32/64 Bit RISC)
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Inverter
(a) (b) (c)
Michael E.Auer
Circuit schematic for a CMOS inverter Simplified operation model with a high input applied Simplified operation model with a low input applied
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Inverter Technology •
•
Michael E.Auer
The CMOS inverter consists of a PMOS device and an NMOS device, but they need to be fabricated on the same wafer To accomplish this, the technique of “n-well” implantation is needed as shown in this cross-section of a CMOS inverter
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
PMOS & NMOS Transistors Drain Currents
NMOS Transistor
NMOS
(v GS ≥ VTN )
PMOS
Linear (Triode) Region : iD = K n'
Saturation Region :
Michael E.Auer
W v vGS − VTN − DS v DS L 2
K n' W 2 iD = (vGS − VTN ) (1+ λv DS ) 2 L
29.09.2013
iD = K 'p
(v GS ≤ VTP ) W v vGS − VTP − DS v DS L 2
K 'p W 2 iD = (vGS − VTP ) (1+ λv DS ) 2 L
BST09
DEVICES & CIRCUITS - CMOS
Static Characteristics of the CMOS Inverter
Michael E.Auer
29.09.2013
•
The figure shows the two static states of operation with the circuit and simplified models
•
Notice that VH = 5V and VL = 0V, and that ID = 0A which means that there is no static power dissipation
BST09
DEVICES & CIRCUITS - CMOS
CMOS Voltage Transfer Characteristics (1) •
The VTC shown is for a CMOS inverter that is symmetrical (Kp = Kn)
•
Region 1: vO = VH vI < VTN Region 2: |vDS| ≥ |vGS – VTP| Region 4: vDS ≥ vGS – VTN Region 5: vO = VL vI > VDD – |VTP|
• • •
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Voltage Transfer Characteristics (2)
Michael E.Auer
29.09.2013
•
The simulation results show the varying VTC of the inverter as VDD is changed
•
The minimum voltage supply for CMOS technology is VDD = 2VT ln(2) V
BST09
DEVICES & CIRCUITS - CMOS
Noise Margins for the CMOS Inverter (1) Noise margins are defined by the points shown in the given figure
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Noise Margins for the CMOS Inverter (2) KR =
VIH
KN KP
VIL =
Michael E.Auer
NM H = VOH − VIH
2 K R (VDD − VTN + VTP ) (VDD − K RVTN + VTP ) − = K R −1 (K R − 1) 1 + 3K R
VOL =
VOL
NM L = VIL − VOL
(K R + 1)VIH − VDD − K RVTN − VTP 2K R
2 K R (VDD − VTN + VTP )
( VDD − K RVTN + VTP ) −
(K R − 1) K R + 3 ( K R + 1)VIL + VDD − K RVTN − VTP =
K R −1
2
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Noise Margins for the CMOS Inverter (3) CMOS inverter noise margins versus KR with a 5V power supply and 1V thresholds
KR = 1 corresponds to a symmetrical design
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Inverter Layout
Michael E.Auer
29.09.2013
•
Two methods of laying out a CMOS inverter are shown
•
The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the psubstrate
•
Polysilicon is used to form common gate connections, and metal is used to tie the two drains together
BST09
DEVICES & CIRCUITS - CMOS
CMOS Inverter Layout
Michael E.Auer
29.09.2013
•
Two methods of laying out a CMOS inverter are shown
•
The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the psubstrate
•
Polysilicon is used to form common gate connections, and metal is used to tie the two drains together
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Propagation Delay Estimate (1)
Discharging the load
Michael E.Auer
Charging the load
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Propagation Delay Estimate (2) VH − VTN t PHL = RonN C ln 4 VH + VL 1 RonN = K n (VH − VTN )
2VTN − 1 + VH − VTN
t PHL + t PLH tp = = t PHL 2 •
Michael E.Auer
If it is assumed the inverter is “symmetrical” with (W/L)P = 2.5(W/L)N, then tPLH = tPHL 29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Rise and Fall Times •
The rise and fall times are given by the following approximate expressions:
t f = 2t PHL
Symmetrical inverter:
t r = 2t PLH
Michael E.Auer
tf = tr
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Inverter Design Example (1) Design a reference inverter to achieve a delay of 250ps with a 0.1pF load given the following information:
VDD = 3.3V C = 0.1 pF t p = 250 ps VTN = −VTP = 0.75V
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Inverter Design Example (2) Given:
K = 25 ' n
K = 10 ' p
µA V
2
µA 2
VTN = 0.75 V VTP = −0.75 V
V t p = t PHL = t PLH = 250 ps We assume the inverter is symmetrical.
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Inverter Design Example (3) Solve for Ronn: RonN =
t PHL VDD − VTN C ln 4 VDD
2VTN − 1 + − V V DD TN
= 1890 Ω V
DD
M
Now solve for the transistor ratios: W L W L
Michael E.Auer
1 8.30 = = ' 1 n K n RonN (VDD − VTN ) 20.8 W 2 . 5 = = 1 p L n
29.09.2013
v
= 3.3 V
20.8 P
1 v
I
O
M
N
8.3 1
BST09
DEVICES & CIRCUITS - CMOS
Static Power Dissipation
Michael E.Auer
•
CMOS logic is considered to have no static power dissipation
•
This is not completely accurate since MOS transistors have leakage currents associated with the reverse-biased drainto-substrate connections as well as sub-threshold leakage current between the drain and source
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Dynamic Power Dissipation
•
There are two components that add to dynamic power dissipation:
1)
Capacitive load charging at a frequency f given by: PD = CV2DDf The current that occurs during switching which can be seen in the figure
2)
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Power Delay Product The power-delay product is given as:
PDP = Pav t P Pav = CV
2 DD
f
1 f = T
The figure shows a symmetrical inverter switching waveform.
2t r 2(2τ P ) T ≥ t r + t a + t f + tb = = = 5τ P 0.8 0.8 2 2 CVDD CVDD PDP ≥ τP = 5τ P 5
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS NOR Gate
Y=A+B
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS NOR Gate Layout
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS NOR Gate
Y=A+B+C
It is possible to extend this same design technique to create multiple input NOR gates
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS NAND Gate
Y=A·B
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Multi-Input CMOS NAND Gates
Y=A·B·C·D·E
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Complex CMOS Logic Gate Design
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Complex CMOS Logic Gate Example
Y = A + B · (C + D)
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate
Michael E.Auer
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
CMOS Transmission Gate
Michael E.Auer
29.09.2013
•
The CMOS transmission gate (T-gate) is a useful circuits for both analog and digital applications
•
It acts as a switch that can operate up to VDD and down to VSS
BST09
DEVICES & CIRCUITS - CMOS
CMOS Transmission Gate (2) •
The main consideration that needs to be considered is the equivalent on-resistance which is given by the following expression:
REQ
Michael E.Auer
RonP RonN = RonP + RonN
29.09.2013
BST09
DEVICES & CIRCUITS - CMOS
Summary • • • •
•
•
Michael E.Auer
In CMOS logic each gate contains both an NMOS and a PMOS switching network and every logical input is connected to at least one NMOS and one PMOS transistor. The high and low output voltage are VDD and VSS and therefore the noise margins are maximal. NAND gates, NOR gates and complex CMOS logic gates can all be designed as for NMOS circuitry. The NMOS and the PMOS switching networks are behavioral or structural dual. CMOS power dissipation is determined by the energy required to charge and discharge the load capacitance at the desired switching frequency. The static power dissipation is nearly disappearing. During switching of the CMOS gate a pulse of current occursbetween the positive and negative power supplies. This current causes an additional component of the power dissipation in CMOS gates that can be as much as 20 to 30 percent of the dissipation resulting from charging and discharging the load capacitance. A new bidirectional circuit element, the CMOS transmission gate that utilizes the parallel connection of an NMOSand a PMOS transitor was introduced. When the transmission gate is on, it provides a low-resistance connection between it‘s input and output terminals over the entire input voltage range.
