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(A/D) converter for serial-link receivers has been investigated. The. A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, ...
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

A 600-MS/s 5-Bit Pipeline A/D Converter Using Digital Reference Calibration Aida Varzaghani, Student Member, IEEE, and Chih-Kong Ken Yang, Member, IEEE

Abstract—The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mVp-p at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with 0.35 LSB of DNL and 0.15 LSB of INL. The 180 1500 m2 chip is fabricated in a 0.18- m standard CMOS technology and consumes 70 mW of power at 600 MS/s. Index Terms—Analog-to-digital converter, calibration, effective number of bits (ENOB), pipeline, resolution, signal-to-noise and distortion ratio.

a low input capacitance of 170 fF. Unlike the flash A/D converter (especially with distributed track/hold) where large accumulated parasitic capacitance of comparators limits the input bandwidth, the input capacitance is determined by the comparators and sample/hold of the first stage alone. To reach the sampling rates required for serial-link applications, a speed-optimized sample/hold design is proposed. Section II describes the circuit architecture. To increase the sampling rate beyond the limits of amplifier settling, a method of digital reference calibration is proposed. The technique adapts the reference of each stage to compensate for the limited settling. Section III describes the implementation and how the reference values are calibrated for maximum signal-to-noise and distortion ratio (SNDR). In Section IV, the measurement results from a test chip are presented. Comparisons with other similar speed A/D converters in 0.18- m CMOS technologies are made using standard figures of merit.

I. INTRODUCTION

S

ERIAL-LINK receivers with baud rates exceeding tens of gigabits per second are of growing interest. Such high data rates for channels that have 3 dB frequencies less than 1 GHz is only possible with a large amount of channel equalization. Modulation and coding [1]–[4] have been demonstrated as means to efficiently utilize the bandlimited channel. Low to medium resolution, large bandwidth, Nyquist analog-to-digital (A/D) converters are needed as critical components of the receivers. The multi-gigasamples per second (GS/s) converters often employ interleaving to increase the sampling speeds and have been demonstrated using various architectures such as flash [4], flash with averaging [5]–[7], open-loop pipeline [8], and folding [9]. This paper suggests closed-loop pipeline as an alternate architecture that offers multiple advantages when the A/D converter is specifically designed for interleaving. In addition to the low input capacitance, the step-by-step data conversion also enables implementing an equalizer with feasible timing requirement when the A/D converter is used as a part of an interleaved serial-link receiver [10]. In this paper, a 5-bit 600-MS/s closed-loop pipeline A/D converter is demonstrated in a 0.18- m CMOS technology. It has

Manuscript received December 6, 2004; revised July 28, 2005. This work was supported by UC Micro, Intel, National Semiconductor, Panasonic, and Broadcom. The authors are with the University of California, Los Angeles, CA 900951594 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2005.862350

II. A/D CONVERTER ARCHITECTURE The pipeline A/D converter consists of four differential stages of 1.5 bits per stage and a 2-bit flash at the end. Fig. 1 shows the architecture of first four stages. The added 0.5-bit redundancy per stage absorbs comparator offsets that arise from using small devices, as well as errors resulting from sampling time mismatch between the comparators and samplers. The sample/hold was chosen to be 70 fF. The value guarantees capacitor both a small input capacitance for the A/D converter and better than 5 bits of matching of capacitor values. The total input capacitance is 170 fF and comprises two first-stage comparators (15 fF each) and two sampling capacitors (70 fF each). To avoid charge injection from the input differential switches, the input . The sampling switches turn off with a delayed clock amplifier and hence its parasitics are disconnected during sampling to improve the sampling time constant [11]. When is HIGH, a pair of switches disconnects the amplifier from the sampling capacitors while another pair of feedback switches reis HIGH, the sets the amplifier. In the hold mode, when amplifier is switched back to the residue generation circuit. A. Amplifier Design and Speed Optimization Fig. 2 depicts the amplifier used in each pipeline stage. The gain-boosted architecture increased the low frequency gain from roughly 80 (for a simple folded-cascode) to 3000. The high gain further reduces gain errors. To maximize the A/D converter sampling rate, the settling time of the closed-loop amplifier during hold mode is minimized. One of the key contributors of the settling time is the time constant of the amplifier.

0018-9200/$20.00 © 2006 IEEE

VARZAGHANI AND YANG: A 600-MS/s 5-BIT PIPELINE A/D CONVERTER USING DIGITAL REFERENCE CALIBRATION

Fig. 1.

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(a) Single-ended illustration of each pipeline stage. (b) Clock signals. (c) Residue plot.

Fig. 2. Gain-boosted, folded-cascode amplifier of each pipeline stage.

The time constant,

Fig. 3. The amplifier’s settling time-constant versus the input transistor area for various tail currents.

, can be expressed as follows: (1) (2)

is the sample (and hold) capacitance, is the amwhere is the load capacitance. For plifier input capacitance, and a given load capacitance, sample and hold capacitances, and power consumption, the settling time constant can only be deof the input transistor pair. creased through increasing the and are monotonically increasing functions of Both ; is a linear function of with minimum channel saturates as increases. An optimum value length, and of exists at which is minimum. versus for three tail currents , Fig. 3 plots fF, fF and 1, 2, and 4 mA, with m. The plot implies that for all three cases, there is an

optimum size for transistors that minimizes the time constant. The minimum time constant is 68 ps and 54 ps for tail currents of 2 mA and 4 mA respectively. Doubling the current (and power consumption) only improves the speed by a factor of 1.26. For a reasonable power tradeoff, the current is selected to be 2 mA and an input device width of 62- m is used in this design. To settle to 4 bits of accuracy, the amplifier alone needs 240 ps. In addition to the amplifier’s time constant, the pipelined stage settling time also depends on the degrading effects of switches, nondominant poles, and more importantly, critical feed-forward path settling (i.e., comparators, logical gates, switches and reference voltage settling times). Simulation results predict a sampling rate of 550 MHz for settling to 4 bits and have a duty cycle of 45% of accuracy, assuming and a rise/fall time of 50 ps. Simulated feed-forward settling

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time is 335 ps. As will be shown in Section IV, the measured maximum clock frequency for 4 bits of settling is 480 MHz. At 600 MS/s, the settling time needs to be 0.8 times smaller, for complete settling to 4 bits of accuracy. To resolve this, at least two options exist: 1) doubling the current (and power consumption) to speed up the amplifiers (as was stated above) and 2) digitally correcting the incomplete settling. Here, a digital reference calibration has been used that not only consumes no steady-state power and corrects for incomplete settling of amplifiers but is also potentially able to correct any kinds of gain error. The time constant for resetting the amplifier in the sample mode is

Fig. 4.

Comparator used in each pipelined stage.

Fig. 5.

(a) Impact of amplifier incomplete settling (b) on residue plot.

(3) In this design, is 23 ps, which is close to 1/3 of the hold mode time constant. Therefore, the sample mode time constant does not limit the A/D converter speed. Furthermore, it guarantees that any residual values from the previously held values are fully reset. The amplifier is designed to have a phase margin of 72 in the hold mode where the closed-loop gain is 2. This avoids peaking in transient response in the hold mode and is needed for optimum reference calibration, as will be described in Section IV. Accordingly, in the sample mode when the amplifier is in the unity-gain configuration, the phase margin is 58 , which ensures the stability. The amplifier common-mode voltage is set to 0.8 V by an active common-mode feedback circuit using a single-stage amplifier. The common-mode voltage is maintained in both sample and hold modes. In the sample mode, when the amplifier is in a unity-gain configuration, the common-mode feedback circuit resets the amplifier’s input to 0.8 V.

III. DIGITAL REFERENCE CALIBRATION To further increase the sampling rate, the amplifier and reference buffers can potentially be redesigned for a lower settling time. However, the higher speed is at the cost of substantial increase in power and input capacitance. Instead, this paper introduces digital reference calibration, a technique that is based on digitally adapting the reference voltage of each pipeline stage. This section first describes the implementation, followed by some design considerations and the method of calibration.

B. Comparator Design

A. Implementation

The comparator design is shown in Fig. 4. Each comparator consists of a pre-amplifier and a latch [12]. To minimize the A/D converter’s power consumption, the design does not use a dedicated input sample/hold, and the comparators sample the input signal directly. Timing mismatch between sampling capacitors and comparators can introduce errors in the conversion of high frequency inputs. To avoid the mismatch, the common-mode voltages of the input signal and output of the pre-amplifier are . Similarly, the sizes designed to be equal of the sampling switches (S1 in Fig. 1 and S2 in Fig. 4) are is a single the same. In the layout, the sampling clock metal trace and only splits at the gates of S1 and S2. Furthermore, the sampling clocks are designed to have a sharp transition to reduce the sampling aperture. Residual mismatch in the sampling moments appears as error voltage in the comparator. With a 1.5 bit/stage code-overlapping, the SNDR of the con[13]. verter is tolerant to total comparator errors within The input devices of comparators are sized sufficiently large so range. as to not result in offsets that use up the entire

At high sampling frequencies, the amplifiers fail to settle to their final values during the hold mode. Fig. 5 shows an amplifier settling transient. When the cycle time shortens, the error is initially linearly related to the final value (point B compared with point A). The error is linear as long as point B is in the exponential portion of the amplifier settling transient. The linear error results in a gain error in the residue plot. To calibrate for the gain error, the reference voltage of each stage is reduced to cover the entire output voltage range of the previous stage. This reference adjustment can then recover the lost SNDR (Fig. 6). For instance, if the reference voltage for the first stage , stages 2, 3, 4, and 5 then have reference voltages equal is and , respectively (where to ). Fig. 7 shows the concept in the form of the original and calibrated residue plots. In our implementation, both the reference voltages and the comparator thresholds are adjusted digitally. The references for each stage can be adjusted independently. A single chip-wide globally distributed bias and reference voltage is connected to switches that digitally program the reference voltage for each

VARZAGHANI AND YANG: A 600-MS/s 5-BIT PIPELINE A/D CONVERTER USING DIGITAL REFERENCE CALIBRATION

Fig. 6.

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Illustration of the signal dynamic range through the pipeline stages, (a) without calibrated references, and (b) with calibrated reference values.

Fig. 7. Residue plots for consecutive stages (a) before, and (b) after calibration. Output swing of each stage determines the input signal range of the following stage. The reference calibration adjusts the desired input dynamic range of each stage to match the output swing of previous stage.

stage [14]. Because of the switches, the reference voltages suffer from charge-injection variations and capacitive coupling. Buffer amplifiers buffer the voltages/currents in order to reduce the recovery time constant of these voltages. The injection can be further corrected via the calibration. Fig. 8 shows the circuitry for the reference voltage generator, their digital adjuster, and the class-AB buffers. The class-AB buffers consume 8% of total power consumption. Digital reference calibration is a modification of the reference-refreshing technique for cyclic A/D converters [15] that removes the dependency of the conversion on the loop gain accuracy by refreshing the references. The main differences between this work and [15] are: 1) the reference voltages are adjusted digitally and automatically through a calibration method and 2) the references are adjusted to improve the sampling speed of the converter rather than to correct for capacitor mismatches and finite amplifier gain. In contrast to [16], the analog residue is not calibrated to a particular value. Instead, the comparator decision levels are adjusted for each pipeline stage. It should also be mentioned that

although the full-scale residue may reduce in amplitude as the signal approaches the final stage, the LSB still receives a stage amplification of 2 as long as is not significantly less than one. B. Design Considerations Since digital reference calibration is effectively correcting for a gain error in the residue plot, it can correct linear errors such as capacitor mismatch and amplifier gain. However, nonlinear errors cannot be corrected. As the sampling rate increases further, the amplifier output settling becomes nonlinear due to the feed-forward path (comparators, logical gates, and switches) time constant, charge injection of the switches, and difference in initial output voltages of various portions of residue plot. Fig. 9(a) shows impact of the amplifier settling on the residue plot when the error is linear. Based on simulation results of our design, and assuming 8 bits of resolution for reference calibration, a linear error is apparent at sampling frequencies above 550 MS/s and the error is linear up to 850 MS/s.

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Fig. 8. Adjustable and buffered reference voltage generation.

Fig. 9. The impact of errors on the residue plot: (a) linear and (b) nonlinear errors.

A second consideration is that the amplifier must not be slew limited in order for the amplifier settling to appear as a gain error. Slewing of the amplifier occurs when the differential where voltage on amplifier inputs becomes larger than 1.4 is the overdrive voltage and is 50 mV for this design. Slewing is most likely to happen at the start of hold mode when the differential voltage at the amplifier inputs is largest in amplitude. Fig. 10(a) and (b) shows the approach of calculating at the amplifier inputs. The the initial voltage voltage can be expressed as

amplifier differential pair is less than 70 mV for most of the input range. However, the voltage difference can be as large as 110 mV. When the amplifier slews, the capacitors are charged/discharged with the amplifier tail current of 2 mA. In ), based on (5), the amplifier the worst case (i.e., only requires 16 ps to exit slewing. The slewing time of the amplifier is only 2% of the total hold mode time ( 833 ps for a 600-MHz clock) and therefore has a negligible effect on the settling behavior.

(4) ps. (5) where and

fF,

fF,

fF. represents the voltage change at the input of the pipeline or depending on the value of stage and is either . Fig. 10(c) illustrates the versus the input voltage , and shows that the voltage difference at the input of the

C. Calibration Methodology The reference values of each pipeline stage are digitally controlled and the calibration requires an explicit phase of operation. An optimum set of reference values is found iteratively to

VARZAGHANI AND YANG: A 600-MS/s 5-BIT PIPELINE A/D CONVERTER USING DIGITAL REFERENCE CALIBRATION

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Fig. 10. Capacitor configuration (a) in sample mode and (b) at the start of hold mode. (c) Initial voltage on amplifier inputs at the start of hold mode. (d) Amplifier model when slewing.

Fig. 11.

Offline calibration scheme.

maximize the SNDR (Fig. 11). The algorithm allows independent reference adjustment for each stage in order to adjust for possible closed-loop gain mismatches between pipelined stages. As shown in Fig. 12, during the calibration phase, an off-chip calibration signal which is a full-scale sinusoid at roughly 1/100 of the sampling frequency is digitized by the pipeline A/D converter with initial values for the reference voltages. The digitized sinusoid is stored in a memory. To compute the SNDR, each point of the digitized sinusoid is assigned to a digital code that maps to an analog value (or conversion level). This assignment can only be done if the phase of the digitized off-chip sinusoid is known. The proper timing of digitized sinusoid is determined by maximizing its cross-correlation with an ideal sinusoid that has been digitized. For reasonable hardware requirement, while computing the cross-correlation, a few LSBs of reference and input sinusoids may be discarded. Due to quantization, multiple points of the digitized sinusoid may be assigned to a single digital code. For example, sam-

ples at times , and which are , , respectively, are all converted to a single digital code and (Fig. 12). Each digital code is then mapped to an analog conand used to calculate SNDR. The mapping version level and the digitized sinusoid between the conversion level , and ) can be generalized as an arbivalues ( trary function. and

(6)

The mapping that maximizes SNDR is desirable. SNDR can be expressed as SNDR (7) (8)

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Fig. 12.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

Find and maximize SNDR as part of the calibration scheme.

where is a sub-index for digitized sinusoid points that are mapping to a single analog conversion level, and is the number of points mapping to a conversion level. In Fig. 12, is shown at each conversion level to be 3. If the quantization error can be calis minimized (maximizing SNDR), the optimum culated by setting the gradient of to 0. (9) (10) (11) Equations (9)–(11) indicate that using a numerical average of ’s as the mapping function maximizes SNDR. the The SNDR can be calculated for different choices of reference values and compared. The references of each stage that maximizes SNDR are chosen. Because the necessary operations are simple arithmetic, only modest hardware is needed for this calibration. In the test setup, the calibration is performed off-chip. Fig. 12 shows the size of the memory and the number of bits for additions needed at each step of the calibration. The

entire calibration process can be implemented with a 16-bit integer processor. IV. MEASUREMENT RESULTS The die photo and layout view are shown in Fig. 13. The logic elements to store the digital tuning occupy 6% of the entire A/D converter area. Fig. 14(a) illustrates the SNDR after calibration for various sampling frequencies. Fig. 14(b) shows the SNDR improvement which increases from 0 at 300 MS/s (when the amplifiers completely settled) to 4.4 dB and 6.8 dB at 600 MS/s and 670 MS/s, respectively. The SNDR improvement at these frequencies is mainly limited by reference adjustment resolution (8 bits). For higher frequencies, residue plots start to show severe nonlinearities. At 600 MS/s, the equivalent stage gain is 1.6 instead of 2. The efficiency of the technique then drops to only 1 dB of SNDR improvement at 800 MS/s. With a for all pipelined stages at 600 MS/s, the A/D relative converter achieves 5 bits of resolution and 4 effective number of bits (ENOB). Since all pipelined stages have similar closed-loop gains, a similar relative is found for all of them. The differential nonlinearity (DNL) and integral nonlinearity (INL) plots are shown in Fig. 15. The residue gain error results in DNLs and

VARZAGHANI AND YANG: A 600-MS/s 5-BIT PIPELINE A/D CONVERTER USING DIGITAL REFERENCE CALIBRATION

Fig. 13.

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(a) Die photo and (b) layout view.

Fig. 15. DNL and INL plots after calibration. They were calibration.

60.6 LSB before

Fig. 14. (a) SNDR after calibration. (b) SNDR improvement versus sampling frequency.

INLs as large as 0.6 LSB. Due to underestimating the loading of the clock buffer, the supply voltage must be increased to 2.05 V for sampling frequencies higher than 600 MS/s; otherwise the clock slew rate is insufficient to properly sample the data. Fig. 16 illustrates the SNDR at 600 MS/s versus input frequency up to 3 GHz. The measured receiver 3 dB bandwidth is 2.4 GHz. An additional 3.2 dB of SNDR drop at this frequency is caused by the clock jitter of 20 ps peak to peak. Even though simulation shows a bandwidth as high as 6 GHz, packaging loss limits the bandwidth. Two types of figure-of-merit (FOM) are widely used to compare the performance of A/D converters: (12) (13)

Fig. 16.

SNDR versus input frequency at 600-MS/s.

where is total power consumption, ENOB is the effective number of bits, is sampling frequency, and ERBW is the effective resolution bandwidth.

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TABLE I FOM COMPARISONS

1,2,3,4 This is the power consumption of the core A/D converter and excludes the power of digital back-end. 5 Insufficient data to extract the power of output drivers. 6 Excludes the power of back-end and input BiCMOS buffer. 7 Includes the power consumption of logic and PLL. 8 Excludes the power of digital back-end but includes the power of clock buffers.

TABLE II PERFORMANCE SUMMARY

pacitance (170 fF) and large ERBW (1.1 GHz), the FOM2 is also presented. Most A/D converters have FOM2 between 2 and 7 pJ. The FOM2 for this design is the lowest at 2 pJ/conversion-step for A/D converters realized in 0.18- m CMOS.1 The performance of the proposed A/D converter is summarized in Table II. The total power consumption including the reference generator is 70 mW. V. CONCLUSION

In applications such as digital oscilloscopes and serial-link receivers where large ERBW and small input capacitor is needed, FOM2 is a better indicator of the performance of the A/D con. verter. In such cases, ERBW is usually larger than Table I shows a list of recent A/D converters with similar or higher sampling rates. Both FOM1 and FOM2 have been demonstrated for each A/D converter. The FOM1 for this design is 7.5 pJ/conversion-step. To highlight the small input ca-

A pipeline A/D converter for multi-level serial links has been demonstrated. The pipeline stage has been optimized for speed. The SNDR is then further improved beyond the amplifier settling time constant limitation using digital reference calibration. The digital calibration technique is shown to improve the ENOB at high sampling speeds while maintaining a low power consumption for A/D converter but is ultimately limited by nonlinearities as sampling frequency exceeds 800 MHz. The closedloop pipeline architecture along with digital reference calibration presents a very good figure-of-merit among A/D converters with similar or higher sampling frequencies in 0.18- m CMOS. With the small input capacitance and high ERBW, this converter 1Although the A/D converter in [8] has higher FOM, it has a very high sampling rate of 20 GS/s and a resolution of 8 bits.

VARZAGHANI AND YANG: A 600-MS/s 5-BIT PIPELINE A/D CONVERTER USING DIGITAL REFERENCE CALIBRATION

can be used as part of an interleaved architecture of a serial-link receiver with multi-GS/s performance. ACKNOWLEDGMENT The authors acknowledge the help of L. Lee in designing the clock generator, V. Stojanovic for technical discussions, and National Semiconductor for fabrication. REFERENCES [1] C. Menolfi, T. Toifl, R. Reutemann, M. Ruegg, P. Buchmann, M. Kossel, T. Morf, and M. Schmatz, “A 25 Gb/s PAM4 transmitter in 90 nm CMOS SOI,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 72–73. [2] J. T. Stonick, G.-Y. Wei, J. L. Sonntag, and D. K. Weinlader, “An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25 m CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 436–443, Mar. 2003. [3] J. L. Zerbe, C. W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. F. Stonecypher, A. Ho, T. P. Thrush, R. T. Kollipara, M. A. Horowitz, and K. S. Donnelly, “Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell,” IEEE J. SolidState Circuits, vol. 38, no. 12, pp. 2121–2130, Dec. 2003. [4] C. -K. K. Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick, “A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-m CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1684–1692, Nov. 2001. [5] P. Scholten and M. Vertregt, “A 6 b 1.6 Gsample/s flash ADC in 0.18 m CMOS using averaging termination,” in IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2002, pp. 168–457. [6] X. Jiang and M. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS with power efficient averaging,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 532–535, Feb. 2005. [7] G. Geelen, “A 6 b 1.1 Gsample/s CMOS A/D converter,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 128–129. [8] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montij, “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18-m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 318–496. [9] R. Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons, “A 1.8 V 1.6 GS/s 8b self-calibrating folding ADC with 7.26 ENOB at nyquist frequency,” in IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2004, pp. 252–526. [10] A. Varzaghani and C. -K. K. Yang, “A 6 GS/s, 4-bit analog-to-digital converter with embedded DFE,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 322–325. [11] S. H. Lewis, H. S. Fetterman, G. F. Gross, R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, Mar. 1992. [12] B. Razavi, Data Conversion System Design. New York: Wiley/IEEE Press, 1994. [13] T. Cho and P. R. Gray, “A 10 b, 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar. 1995.

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[14] J. G. Maneatis, J. Kim, L. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795–1803, Nov. 2003. [15] C.-C. Shih and P. R. Gray, “Reference refreshing cyclic analog-to-digital and digital-to-analog converters,” IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 544–554, Aug. 1986. [16] J. Ming and S. H. Lewis, “An 8-bit 80-Msample/s pipelined analog-todigital converter with background calibration,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1489–1497, Oct. 2003. [17] D. Draxelmayr, “A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2004, pp. 264–527. [18] A. Varzaghani and C. -K. K. Yang, “A 600 MS/s 5-bit pipelined analog-to-digital converter for serial-link applications,” in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 2004, pp. 276–279.

Aida Varzaghani (S’05) received the B.S. and M.S. degrees (both with honors) in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2001, respectively. Since 2001, she has been working toward the Ph.D. degree in integrated circuits and systems at the University of California, Los Angeles. From 1999 to 2001, she was with Emad Semiconductor Company as an Analog Circuit Designer. She designed a low-power binary receiver for IBM, Yorktown Heights, NY, in summer 2004. Her current research interests include high-speed, large-bandwidth A/D converters, equalization techniques for very high-speed serial I/O links, and switched-capacitor and switched-opamp A/D converters. Ms. Varzaghani was the recipient of a UCLA fellowship for Fall 2001.

Chih-Kong Ken Yang (S’94–M’98) was born in Taipei, Taiwan, R.O.C. He received both the B.S. and M.S. degrees and Ph.D. degree from Stanford University, Stanford, CA, in 1992 and 1998, respectively, all in electrical engineering. He has been with the University of California at Los Angeles (UCLA), as an Assistant Professor since 1999 and as an Associate Professor since 2004. His current research is high-performance mixed-mode circuit design for VLSI systems such as clock generation, high-performance signaling, low-power digital design, and analog-to-digital conversion. Dr. Yang was the recipient of the 2003 and 2004 IBM Faculty Development Fellowship and the 2003 Northrup-Grumman Outstanding Teaching Award.