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IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 1, JANUARY 2016
Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior Chunlei Wu, Student Member, IEEE, Ru Huang, Senior Member, IEEE, Qianqian Huang, Student Member, IEEE, Jiaxin Wang, Student Member, IEEE, and Yangyuan Wang, Fellow, IEEE
Abstract— In this letter, design guideline for complementary heterostructure tunnel FETs (C-HTFETs) is proposed based on the insight into the tradeoff between n-type and p-type HTFETs optimization. For the first time, the contradiction of source/channel material selection between n-type and p-type HTFETs is addressed, indicating that HTFETs integrated on the same materials system cannot achieve optimized n-type and p-type devices simultaneously. Optimized complementary III–V HTFETs based on two different source/channel materials systems are studied as design examples for further validation of the proposed design guideline, exhibiting both steep subthreshold swing and improved output behavior in the n-type and p-type HTFETs. The conclusions are helpful to the prospective C-HTFETs design for low-power complementary logic applications. Index Terms— Band-to-band tunneling (BTBT), heterojunction, superlinear onset, complementary tunnel field-effect transistor.
I. I NTRODUCTION HE TUNNEL Field-Effect-Transistor (TFET) has been investigated intensely in recent years as one of the most promising candidates for ultra-low power IC applications [1]–[3]. To date, significant efforts have been made on the investigation of narrow bandgap materials such as Ge and III-V based TFETs to enhance tunnel efficiency. Through numerous exploration of alternative heterojunctions with staggered- or broken-bandgap alignments, the drain current of HTFETs has been dramatically boosted with on current of hundreds of μA/μm [4]. In order to meet the requirements of complementary logic applications, both n-type and p-type HTFETs should be properly designed for complementary performance. Generally, the reported n-type HTFETs mainly focus on III-V materials, p-type HTFETs mainly focus on group IV materials such as
T
Manuscript received October 5, 2015; revised November 4, 2015; accepted November 6, 2015. Date of publication November 9, 2015; date of current version December 24, 2015. This work was supported in part by the National Natural Science Foundation of China under Grant 60625403 and Grant 61421005, in part by the 973 Projects under Grant 2011CBA00601, and in part by the National Science and Technology Major Project 02 under Grant 2009ZX02035-001. The review of this letter was arranged by Editor M. Passlack. The authors are with the Key Laboratory of Microelectronics Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871, China (e-mail:
[email protected] ). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2015.2499183
Ge or SiGe, and the two device types usually are studied separately. N-type and p-type TFETs studied simultaneously are mostly Si homojunction [5], or III-V heterojunction devices based on the same materials system [6] which exhibit degraded p-type device performance and accordingly unsatisfactory complementary behavior. The operating principles of TFETs are fundamentally different from that of MOSFETs, it is the band-to-band tunnel probability at the tunnel junction rather than the channel mobility that plays a key role in the drive current enhancement due to the tunnel-limited operation [7]. Consequently, channel material selection for n-type and p-type heterostructure TFETs with respect to complementarity should be reconsidered. Besides, despite plentiful reports on alternative hetero junctions with reduced effective tunnel barrier for on current enhancement of HTFETs, few work is reported for improving the output characteristics while maintaining steep sub-threshold swing(SS). It is known that the superlinear onset behavior [8], [9] in TFETs significantly degrades the dynamic properties by drastically increasing the rise/fall time of a TFET-based inverter, and the delayed saturation voltage leads to lower static noise margin in digital circuits [10]. Therefore, apart from band-alignment engineering, design optimization for HTFETs with both improved transfer and output characteristics is significantly required for future low power circuit application. In this letter, heterojunction optimization of HTFETs for both steep SS and improved output behavior is studied. New design guideline for complementary HTFETs considering the contradiction of source/channel heterojunction optimization between n-type and p-type devices is proposed and verified. II. C HANNEL M ATERIAL O PTIMIZATION OF C-TFETs Source material optimization of TFETs has been widely studied. It is known that the SS of TFETs can be fundamentally lower than 60mV/dec due to the filtering function of the high energy tail of source Fermi–Dirac distribution [7], hence high density of states(DOS) source materials are preferred for steep transfer characteristics [11]. Apart from the source material selection, the channel material optimization of TFETs should also be taken into consideration. Different from that of MOSFETs, the channel surface potential ϕch of TFETs is alternatively controlled by both the gate bias and the drain
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WU et al.: DESIGN GUIDELINE FOR C-HTFETs WITH STEEP SLOPE
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Fig. 1. The schematic structure of the studied devices. The effective gate oxide thickness is 2nm. The body thickness is 20nm.The gate length is 200nm.
bias [12], the channel material properties are crucial to the output characteristics of TFETs. In the n-type TFETs for example, there is a drain-control band-to-band tunneling switching-on process at small drain bias due to the rather small energy window for tunneling ΔΦ at V D S = 0V, exhibiting the superlinear onset behavior in the output curves. To suppress the detrimental exponential onset, the energy window ΔΦ at V D S = 0V should be remarkably enlarged to significantly enhance the tunneling probability and thus skip the drain-control BTBT switching-on process. Larger energy window ΔΦ at V D S = 0V can be achieved through either increasing the source degenerate-window ΔΦs or increasing the channel degenerate-window ΔΦch . Since high source degeneracy would result in severe SS degradation, larger ΔΦch via channel engineering is studied deliberately here to suppress the superlinear onset without degrading the transfer behavior. Low density of states channel material is required to enlarge the degenerate-window ΔΦch . Particularly, materials with low density of states in the conduction band NC are required for n-type TFETs, while materials with low density of states in the valence band NV are required for p-type TFETs. To gain a better insight into the impacts of channel materials properties, n-type and p-type HTFETs with modified channel materials are simulated using Synopsys TCAD Sentaurus simulator. The device structure is shown in Fig.1, and the channel materials have all properties of silicon only with artificially-modified NC or NV values. The dynamic nonlocal band-to-band tunneling model and the Shockley-Read-Hall recombination model are included. The devices studied are conventional planar TFETs, so the quantum confinement effect is reasonably neglected in the simulation. In order to assess the output performance, the onset voltage VO N S E T is defined as the drain voltage corresponding to 10% of the output saturation current for superlinear onset assessment, and the saturation voltage V D S,S AT is defined as the drain voltage corresponding to 90% of the saturation current. As shown in Fig. 2(a) and (c), lower DOS channel material (low NC for n-type/low NV for p-type) leads to larger ΔΦch and thus larger energy window ΔΦ at V D S = 0V, consequently the superlinear onset behavior is remarkably suppressed in both n-type and p-type HTFETs. The onset voltage VO N S E T is seen to reduce with decreasing NC /NV value. In addition, reduced saturation voltages V D S,S AT can also be observed. The saturation voltages V D S,S AT is inversely proportional to channel inversion condition (ϕch = ϕch,inv ) [12], [13], yet channel material with lower density of states has lower intrinsic carrier density n i , which results in larger ϕch,inv and thus reduced V D S,S AT . In addition, since the source degeneracy remains unaffected, steep SS can still be expected.
Fig. 2. a) The band diagrams at the tunnel junction of n-type TFETs with reduced NC values of the channel at V DS = 0V. b) The corresponding output curves of n-type TFETs at VG S = 1.0V. c) The band diagrams of p-type TFETs with reduced NV values of the channel at V DS = 0V. d) The corresponding output curves of p-type TFETs at VG S = −1.0V. The doping concentrations of the p+/n+ source, p-/n- channel and n/p drain are 1×1020 , 5×1014 /cm3 , 1×1018 /cm3 respectively for n-/p-type TFETs. The gate workfunction is 3.75eV/4.95eV for n-/p-type TFETs. The non-local BTBT model parameters are the same with that of silicon that are calibrated based on the experimental results of [2].
Fig. 3. a) Schematic illustration of optimized source/channel heterojunctions for n-type HTFETs and b) p-type HTFETs. c) Corresponding source/channel heterojunctions for p-type HTFETs and d) n-type HTFETs based on the same materials systems of a) and b).
III. D ESIGN G UIDELINE FOR C OMPLEMENTARY HTFETs According to above analysis, it can be concluded that source materials with high NV and channel materials with low NC are preferred in n-type HTFETs, while source materials with high NC and channel materials with low NV are preferred in p-type HTFETs, as shown schematically in Fig. 3(a) and (b). It should be noted that there is a trade-off between the source and channel materials selection, which introduces an
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IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 1, JANUARY 2016
TABLE I M ATERIAL S ELECTIONS FOR C-HTFETs AND P ERTINENT PARAMETERS
Fig. 4. a) The transfer curves and b) the normalized output curves of device AN and device AP , the gate WF is 4.05eV/4.45eV for n-/p-type. c) The transfer curves and d) the normalized output curves of device BP and device BN , the gate WF is 4.15eV/3.45eV for p-/n-type. The doping concentrations of the p+/n+ source, p-/n- channel and n/p drain are 1×1020 , 5×1014 /cm3 , 1×1018 /cm3 respectively for n-/p-type HTFETs. The nonlocal BTBT model parameters for III-V HTFETs were derived based on the experimental calibration results based on [15] and the parameters definitions in [16].
inherent contradiction of the source/channel heterojunction optimization between n-type and p-type HTFETs. One particular hetero -junction could achieve either good n-type device performance and degraded p-type device performance, or good p-type device performance and degraded n-type device performance. In other words, HTFETs integrated on the same materials system cannot achieve optimized n-type and p-type device performance at the same time. Therefore, n- and p-type HTFETs based on different heterojunctions are required for complementary performance. To further check the validity of the design optimization proposed, n- and p-type III-V HTFETs based on staggeredgap heterojunctions of Al0.4 Ga0.6 Sb/In0.53 Ga0.47 As (materials system A) and In0.6 Al0.4 As/GaAs0.1 Sb0.9 (materials system B) are studied as an example, as listed in Table I. In order to achieve both steep SS and improved output behavior, source/channel hetero-junction of Al0.4 Ga0.6 Sb/In0.53 Ga0.47 As is preferred for n-type HTFET(Device AN ), where the source material Al0.4 Ga0.6 Sb has high NV value and channel material In0.53 Ga0.47 As has low NC value. And the source/channel heterojunction of In0.6 Al0.4 As/GaAs0.1 Sb0.9 is
preferred for p-type HTFET(Device B P ), where the source material In0.6 Al0.4 As has high NC value and channel material GaAs0.1 Sb0.9 has relative lower NV value. Meanwhile, p-type HTFET (Device AP ) based on the same materials system of Device AN with opposite choice for source and channel, and n-type HTFET(Device BN ) based on the same materials system of Device BP with opposite choice for source and channel are also studied for comparative analysis. To gain a reasonable evaluation of the performance trade-off caused purely by the materials system, the device dimensions and source/drain doping concentrations of n-type and p-type HTFETs are kept the same. In materials system A, as shown in Fig.4(a) and (b), the n-type Device AN exhibits both steep slope (SSmin. = 14mV/dec at V D S = 0.5V) and improved output behavior, however, the p-type Device AP , which bases on the same materials system of Device AN , shows degraded SS (SSmin. = 30mV/dec at V D S = −0.5V) and superlinear onset behavior. In contrast, in materials system B, as shown in Fig.4(c) and(d), the p-type Device BP exhibits steep slope (SSmin. = 18mV/dec at V D S = −0.5V) and improved output behavior, while the n-type Device BN , which bases on the same materials system of Device BP , exhibits degraded SS (SSmin. = 27mV/dec at V D S = 0.5V) and severe superlinear onset behavior. The results further confirm that HTFETs integrated on the same materials system cannot achieve both optimized n-type and p-type device performance, and different source/channel hetero–junctions should be adopted respectively for complementary performance.Since the contradiction of source/channel material optimization between n-type and p-type HTFETs always exists, the above analysis and related design guideline can also be well extended to HTFETs with further scaled device dimensions or based on other semiconducting materials. IV. C ONCLUSION In this letter, the contradiction of the source/channel material selection between n-type and p-type HTFETs is emphasized, highlighting that HTFETs integrated on the same materials system cannot achieve both optimized n-type and p-type devices and different source/channel heterojunctions should be adopted respectively. Complementary n-type and p-type HTFETs based on two different heterojunctions are studied and analyzed as design examples. The conclusions are helpful to the possible exploitation of HTFETs based ultra-low power complementary logic applications. R EFERENCES [1] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energyefficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011. DOI: 10.1038/nature10679 [2] Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, and Y. Wang, “A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration,” in Proc. IEDM, Dec. 2012, pp. 8.5.1–8.5.4. DOI: 10.1109/IEDM.2012.6479005 [3] Z. Zhan, Q. Huang, R. Huang, W. Jiang, and Y. Wang, “A combgate silicon tunneling field effect transistor with improved on-state current,” Sci. China Inf. Sci., vol. 56, no. 7, pp. 1–6, Jul. 2013. DOI: 10.1007/s11432-012-4713-5
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