Design of a Multi-Frequency Bio-Impedance Spectroscopy System Analog Front-End and Digital Back-End with On-Chip Implementation Wen-Yaw Chung1*, Angelito A. Silverio1, Vincent F.S. Tsai2, Shu-Yu Chang1, Ming-Ying Zhou1, Si-Yuan Chen3 1
Department of Electronic Engineering, Chung Yuan Christian University, Taiwan, ROC 2 Department of Urology, Ten Chen General Hospital, Taoyuan County, Taiwan, ROC 3 Department of Electronic Engineering, Jimei University, Xiamen City, China
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[email protected] Abstract - In this paper, the design of a Bio-Impedance Spectroscopy system is presented. The system consists of a Direct Digital Synthesis Sine-Wave Generator (DDS-SWG), an Analog Front-End (AFE), an Analog-Digital Converter (ADC), and a Digital Back-End implemented using a Field Programmable Gate Array (FPGA). The FPGA also drives the ADC, the DDS-SWG, and the LCD. The AFE consists of a high output impedance Load-In-Loop Current Source (LLCS) and a set of High Common-Mode Rejection Ratio (CMRR) Instrumentation Amplifiers (IA). It uses a simple and straightforward impedance extraction algorithm using just division and constant multiplication. The CMOS implementation of the AFE using the TSMC 0.35um 2P4M is also presented. The system forms part of a platform that aims to predict a urolithiasis (urinary stone) event.
the extracted bio-modulated voltage at the input; meanwhile, the IA’s high CMRR reduces the offset voltages, gain errors brought about by the electrode’s parasitic impedance [5], as well as attenuates the noise signals such as electromagnetic interference (EMI), power supply hum, and half-cell potentials at the interface between the circuit and the SUT. There have been some reported literature about the implementation of a BIS system [6-8]. One uses an Improved Howland CS, an IA to extract the impedance voltage signal (VIMP), and a set of Root-Mean-Square (RMS) detectors to convert the VIMP as well as the excitation current level into DC voltages prior to processing [6]. The current is extracted from the voltage drop across a known resistor in series with the SUT. Another uses the lock-in approach to extract the impedance magnitude and phase [7]. To obtain the magnitude, the VIMP is multiplied to the in-phase reference voltage (VREF); whereas for the phase, the VIMP is multiplied to the quadrature VREF. These are then coupled to low pass filters to extract the DC voltages corresponding to the amplitude and the phase shift of VIMP, respectively. A third approach uses a set of IAs that detect the potential difference across the sample, a synchronous full-wave rectifier to get the amplitude through a low pass filter, and comparators XOR gates and an integrator to get the phase shift [8]. This paper is organized as follows: Section I presents the background information about the BIS and the design issues of a BIS system; Section II presents the BIS Analog FrontEnd (BIS-AFE) design implemented both on-board and onchip, and the Application Specific IC (ASIC) synthesized on Field Programmable Gate Array (FPGA); Section III presents the measured results using the on-board system along with preliminary urine tests, as well as the HSPICE simulation results of the on-chip version of the BIS-AFE; and Section IV presents the conclusion and future works.
Keywords— Bio-Impedance Spectroscopy (BIS), Voltage Controlled Current Source (VCCS), Second Generation Current Conveyor (CCII), Differential Voltage Current Conveyor (DVCC)
I. INTRODUCTION Bio-Impedance Spectroscopy (BIS) is a growing technology used as a potential diagnostic tool in medicine [1-3]. The typical BIS system involves the injection of a high frequency AC current onto a sample and the extraction of the bio-modulated voltage across it, or vice versa. In [4], the different excitation frequencies and the corresponding responses of cellular suspensions have been detailed. From this, three dispersion frequency ranges have been identified namely: alpha (10Hz– 10kHz), beta (10kHz – 10MHz), and gamma (˚ 10MHz). Most of the clinical studies mentioned previously utilize either the alpha and beta dispersion bandwidths [1-3]. In a typical BIS system, a high output impedance current source (CS) injects a high frequency current onto the Sample Under Test (SUT). The high output impedance ensures that majority of the excitation current is directed onto the SUT, and not dissipated by the CS. The current source usually takes the form of a Howland Circuit or a Load-in-Loop structure (LL-CS). A high Common-Mode Rejection Ratio (CMRR) and high input impedance Instrumentation Amplifier (IA) is used to detect the voltage developed across the sample. The high input impedance of the IA ensures that the parasitic electrode impedances have minimal effects on
II. BIS SYSTEM DESIGN A. BIS-AFE On-Board Implementation The functional block diagram of the BIS-AFE is shown in Fig. 2. The input signal is generated from a Direct Digital Synthesis Sine Wave Generator (DDS-SWG) chip – AD9837. The output amplitude is 0.39V, and the DC offset is 0.36V. This chip is controlled by an FPGA to produce the frequencies: 10k, 50k, 100k and 250kHz. The output of the DDS-SWG is coupled to a high pass filter and a gain stage
(OTA_CS1) to remove the DC offset and to provide x2 amplification. This is then coupled to the LL-CS formed by an inverting amplifier (OTA_CS2) with a large resistor feedback (1M). The output excitation current is extracted from the amplifier’s feedback loop via IOUT+ and IOUT-. Two IA chips are used – INA128. The first IA (IA_REF) is used to extract the VREF which is directly proportional to the excitation current level; the second IA (IA_IMP) is used to extract the VIMP via the four point probe interface.
appropriately used. In CMIAs, high CMRR can be achieved by minimizing the intrinsic X-terminal impedance (rx). Figs. 3 and 4 show the operational blocks and matrices of the CCII+ and the DVCC, respectively.
Fig. 3. CCII+’s Operational Block Diagram and Matrix
Fig. 4. DVCC’s Operational Block Diagram and Matrix
Based from the matrices, the current drained on X (IX) is conveyed to Z (IZ) (IX = IZ). The voltage at X is equal to the input at Y or the difference between Y+ and Y- in the case of a DVCC. The DVCC can amplify this differential signal by the ratio of the external resistors: RZ/RX. The CMOS implementation of the DVCC is shown in Fig. 5. The circuit is a combination of NMOS and PMOS DVCCs sharing a common output stage [10]. The use of the complementary structure extends the ICMR of the DVCC and reduces the intrinsic X-terminal impedance rx; the latter being inversely proportional to CMRR. The non-linearity in transconductance within the input voltage range, caused by the complementary differential pairs, is compensated by the circuit’s current feedback nature [10].
Fig. 1. BIS-AFE On-Board Implementation (Note that the OTA used is the AD4891 chip)
The unknown impedance can be obtained by division and multiplication by a constant following Eq. (1). ܼூெ ൌ ൬
ಾುିಾುሺಲೇಶሻ ೃಶಷ ିೃಶಷሺಲೇಶሻ
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ೇሺಲሻ ூಶಾು ೇሺಲሻ ூಶோೄ
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(1)
B. BIS-AFE On-Chip Implementation The block diagram of the on-chip BIS-AFE is shown in Fig. 2. An on-chip design has been undergone as a step towards a System-on-Chip (SoC) BIS platform.
Fig. 5. DVCC CMOS Implementation
In reference to Fig. 2, the LL-CS is formed by the CCII and the resistors RZ and RX, the Folded-Cascode OTA (FCOTA), and the PMOS Pseudo-Resistor (PR) at the FCOTA’s feedback. The LL-CS consists of a high gain and wide swing OTA (OTA1) that is driven by a CCII. The CCII behaves as a Norton current source whose output impedance adds to the effective output impedance of the LL-CS [11]. The output impedance can be expressed by: § § ·· 1 Z out (s) = R f || ¨¨ Z o (s) + ((RZ + Z Z ( s)) || Z i ( s))( Ad ( s) + 1)¨¨1 − ¸¸ ¸¸ 2 CMRR ( s ) © ¹¹ ©
Fig. 2. BIS-AFE On-Chip Implementation
CMIAs are usually realized using a set of Second Generation Current Conveyors (CCII) with a floating Z terminal, current inversion, and subtraction by an op-amp [9]. However, since the BIS application requires a differential input and high input impedance, a DVCC is more
(2)
where: Zi is the input impedance of the OTA, Zo is the OTA’s output impedance, Rf is the feedback resistance, Ad is differential gain of the OTA, ZZ is the intrinsic Z-terminal impedance of the CCII. It can be seen that by increasing the RF and the addition of ZZ, ZOUT can be improved. The LL-CS
architecture is shown in Fig. 9 wh hich has been synthesized on Altera Duo II FPGA. Fig. 10 shows the complete onboard BIS System.
was able to maintain a high output impedancce even at very high frequencies (>500kHz) with the help off the CCII. The other factor that affects ZOUT is the feedbackk impedance of the OTA. A high value is necessary so thatt the excitation current is fully conveyed onto the samplee and not just dissipated by the CS. Using on-chip resistors available in the technology is not area efficient in terms of layyout, especially in submicron and deep submicron technologgy, because of their relatively small sheet resistances. To prrovide the large Rf value, a PMOS PR has been used. The PR is formed by a diode connected subthreshold PMOS whose ddrain current is in the pico- to nano-ampere range. An arraay of 4 PMOS (W/L=4u/10u) was used as shown in Fig. 6. M Meanwhile, the complete LL-CS circuit is shown in Fig. 7.
LCD Sin_Wave
DDS (AD9837)
LCD_CTRL
DDS_CTRL
8
ADC_CTRL
VSS VDD 5V
Impedance Readout Circuit
FPGA
8
CU
Div_Clk
Timer
I/O
Comparattor 16
Min Detector
12
+ 12 bits SAR ADC (ADS7841)
Clock
Memory
Imp pedance Detector
Imp_Sin Wave Ref_Sin Wave
Registters
12
Max Detector
12
Pea ak Detector
12
REF_Peak
Aver rage Detector
19 Extend
í
12
12
Divider
12
ZIMP
12
×
19
12 IMP_Peak
Fig. 9. ASIC architecture synthesized d on FPGA (Altera II Duo)
Fig. 6 Four PMOS Pseudo-resistor Series A Array
Since the BIS system will be powered by a single supply of 3.3V, the analog ground needs to be shiftted to 1.65V to achieve maximum signal swing and avoid turning-off the differential pair transistors. To achieve this, a Low Dropout (LDO) regulator has been added on-chipp. A Bandgap Reference (BGR) circuit has been used tto provide the reference voltage for the LDO. The complete LDO circuit with BGR is shown in Fig. 8. The output oof the LDO has been tailored to provide 1.65V.
Fig. 10. Complete On-Boaard BIS System
III. RESULTS AND DISCUSSION A. BIS-AFE On-Chip a open loop DC gain The designed FC-OTA has an average of 87.2dB, a Unity Gain Bandwidtth (UGBW) of 17.29MHz, a Phase Margin (PM) of 53.9deg, impedances of 241.7k output) at 10MHz, and a (input_differential), and 15.5k (o CMRR of 53.7dB at 10MHz, for thee five corner cases. Meanwhile, the CCII has a lineear range for VY and VX of: 0.11V ~ 2.05V. The current gain n (IZ/IX) and voltage gain (VX/VY) are: 0.92 and 0.94, respecttively. The offset voltages measured at X and Z are: 108mV and a 51.8mV, respectively. The VX/VY gain is constant at a ban ndwidth of 10MHz with < 10o phase shift. VZ can be scaled lin nearly with the RZ/RX ratio. The dimensions of the PRs co ontribute to their effective resistance. Lowering the PRs asp pect ratio or raising the number of elements, increases the array’s resistance. In this work, an aspect ratio of 4u/10u was used. The PR array provides an average total DC resisstance of 7.58 G, and an impedance of 958k at 10MHz for the five process corners. MRR of 134.8dB (DC), an The DVCC has achieved a CM output offset voltage of -9.25uV, ICMR I of 0.31V ~ 2.85V, input referred noise of 0.649mV/¥((Hz) from 0.001 ~ 10kHz, and a DC input impedance of 45.5 5T (common-mode), and 151T (differential-mode). The Bandgap B reference has an average Temperature Coefficient (TCF) ( of 10.08ppm and a PSRR of 40.1dB for the five corner cases. FE has been verified using The performance of the BIS-AF known impedance values rangin ng from 120 to 10k corresponding to the urine impedan nce of stone and non-stone patients [12]. A graph of the measu ured (ZMEAS) vs theoretical (ZTHEO) impedances is shown in Fig g.12. A linear trend can be
Fig. 7. LL-CS Complete Circuit
Fig. 8. LDO with the BGR drive CMOS Implem mentation
C. ASIC Interface to On-Board BIS Module The ASIC performs the following functiions: drive the DDS-SWG chip to produce the excitation sinne wave signals driving the LL-CS circuit; control the ADC chhip (ADS784112-bit SAR) to obtain the VIMP and VREF signnals; extract the average of the two signals, perform digittal subtraction, division using a 19-bit divider, and multiiplication by a constant (RS = 10k) following Eq. (1) to obtain the LCD. The ASIC impedance magnitude ZMAG; and control the L
observed between ZMEAS and ZTHEO implying that they are in correspondence for the impedance range and ~100kHz of frequency. ZMEAS is obtained using Eq. (1).
tested, and impedance correlations to other urine indices shall be undergone to analyze the chemistry of urolithiasis. TABLE I. BIS SYSTEMS STATE-OF-THE ART
IV. CONCLUSION AND FUTURE WORKS We have presented the design of a BIS system with the AFE implemented both on-board and on-chip using TSMC 0.35um CMOS technology. The system’s impedance extraction algorithm is relatively simple and straightforward involving only division and multiplication by a constant. Such simplicity can readily be implemented into an ASIC digital chip. The on-chip AFE has shown a satisfactory performance with regard to load detection and operating frequency. The system is applicable in BIS studies involving the alpha and beta dispersion frequencies. The next step is to measure the impedance of more urine samples from stone and non-stone patient groups and correlate this to urine quality indices directly related to urolithiasis.
Fig. 12. Comparison of ZMEAS and ZTHEO for various load resistances and frequencies
B. BIS-AFE On-Board Module with FPGA The responses of the BIS-AFE to a DC input stimuli with varying load resistance is shown in Fig. 13. The change in output voltage slope correlates to the ratio between the series resistor (10k) and the load. The extracted VREF signal is not affected by the load variation. The resistance read out by the system displayed in the LCD corresponds to the real sample resistance with a correction factor of 0.9867, and just an offset of 0.2133. The ZMEAS and ZTHEO are linearly correlated by a factor of 0.999 as shown in Fig. 14. The performance of the BIS on-board module is comparable to the existing state-of –the art, as shown in Table I, and is applicable to our target application in measuring urine impedance/ conductivity as part of our urolithiasis research.
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Fig. 13. BIS-AFE VIMP vs VIN for various load resistances
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[9]
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Fig. 14. BIS-AFE VREF vs VIN for various load resistances
Preliminary results using 14 spot urine samples from stone (7) and non-stone (7) patients acquired from Ten-Chen General Hospital have an average impedance of 1.06k (ı=79.7), and 978 (ı=111), respectively, at 100kHz. Paired two-tailed TTest with unequal variances reveal a pvalue of 0.128. More urine samples shall be acquired and
predicting formation of urolithiasis by simple electrical conductivity and comparison on performance with ion-related indices, urine color and specific gravity. The 2nd European Association of Urology Section of Urolithiasis Biennial Congress 2013 Sep. 5-7. Copenhagen , Denmark .
